WO2020103147A1 - 芯片散热结构、芯片结构、电路板和超算设备 - Google Patents

芯片散热结构、芯片结构、电路板和超算设备

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Publication number
WO2020103147A1
WO2020103147A1 PCT/CN2018/117260 CN2018117260W WO2020103147A1 WO 2020103147 A1 WO2020103147 A1 WO 2020103147A1 CN 2018117260 W CN2018117260 W CN 2018117260W WO 2020103147 A1 WO2020103147 A1 WO 2020103147A1
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WO
WIPO (PCT)
Prior art keywords
chip
heat dissipation
metal layer
layer
dissipation structure
Prior art date
Application number
PCT/CN2018/117260
Other languages
English (en)
French (fr)
Inventor
周涛
高雍
Original Assignee
北京比特大陆科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Priority to PCT/CN2018/117260 priority Critical patent/WO2020103147A1/zh
Priority to CN201921868059.7U priority patent/CN210668333U/zh
Priority to CN201911053463.3A priority patent/CN110767619A/zh
Priority to CN201911053347.1A priority patent/CN110783205A/zh
Priority to CN201911053263.8A priority patent/CN110767553A/zh
Publication of WO2020103147A1 publication Critical patent/WO2020103147A1/zh
Priority to US17/327,027 priority patent/US20210280489A1/en

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Definitions

  • the present application relates to the field of heat dissipation of chips, in particular to a chip heat dissipation structure, chip structure, circuit board and supercomputer equipment.
  • heat-dissipating glue is usually used on the top of the chip to dissipate heat for the chip on the circuit board.
  • the thermal conductivity of the traditional thermal conductive adhesive is generally lower than 2 watts / meter ⁇ degree (W / (m ⁇ C)), which results in a poor heat dissipation effect of the chip.
  • the present application provides a chip heat dissipation structure, chip structure, circuit board, and supercomputing equipment to solve the problem that the heat dissipation effect of the existing chip is not ideal.
  • An embodiment of the present application provides a chip heat dissipation structure, which is disposed on a chip.
  • the chip heat dissipation structure includes: a metal layer, wherein the metal layer covers the chip.
  • the chip heat dissipation structure further includes: a heat sink connected to the metal layer.
  • the chip includes a wafer and a plastic package structure
  • the metal layer covers the wafer and the plastic encapsulation structure of the chip.
  • the upper surface of the wafer is exposed.
  • the area of the metal layer is the same as the area of the upper surface of the chip.
  • the metal layer is a silver glue layer.
  • the thickness of the silver glue layer is 1 to 5 microns.
  • the heat sink is soldered on the metal layer through a solder layer.
  • solder in the solder layer is tin.
  • the thickness of the solder layer is 0.1-0.15 mm.
  • the area of the solder layer is the same as the area of the metal layer, or the area of the solder layer is the same as the area of the lower surface of the heat sink.
  • the metal layer is a metal layer with a uniform thickness
  • the metal layer is embedded in the plastic encapsulation structure
  • the wafer is embedded in the metal layer.
  • An embodiment of the present application further provides a chip structure, including a chip body and a chip heat dissipation structure as described in any one of the above provided on the chip body.
  • An embodiment of the present application further provides a circuit board, which is provided with at least one chip structure as described above.
  • An embodiment of the present application further provides a supercomputing device, and the supercomputing device is provided with at least one circuit board as described above.
  • the chip heat dissipation structure composed of a metal layer
  • the metal layer covers the wafer and the plastic packaging structure of the chip
  • the metal layer can be connected to heat dissipation Device.
  • the epoxy resin material has a higher thermal conductivity, which solves the problem of the heat dissipation bottleneck of the glue material in the chip; it can improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • FIG. 1 is a schematic structural diagram 1 of a chip heat dissipation structure provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram 2 of a chip heat dissipation structure provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram 3 of a chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram 1 of a heat sink provided by an embodiment of the present application.
  • FIG. 5 is a second schematic structural diagram of a heat sink provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram 1 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 7 is a second schematic structural diagram of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram 3 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram 4 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram 5 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram 6 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural view 7 of another chip heat dissipation structure provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a diced wafer provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram 1 of a process flow of a chip provided by an embodiment of the present application.
  • 15 is a second schematic flowchart of a chip process provided by an embodiment of the present application.
  • 16 is a schematic diagram 3 of a process flow of a chip provided by an embodiment of the present application.
  • 17 is a schematic diagram 4 of a process flow of a chip provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram 1 of a chip structure provided by an embodiment of the present application.
  • 19 is a second schematic structural diagram of a chip structure provided by an embodiment of the present application.
  • 21 is a schematic structural diagram of a supercomputing device provided by an embodiment of this application.
  • the embodiment of the present application is applied to a chip. It should be noted that when the solution of the embodiment of the present application is applied to a current chip or a chip that may appear in the future, the names of various structures may change, but this does not affect the implementation of the solution of the embodiment of the present application.
  • exposing the wafer to the die package refers to exposing the wafer to achieve better heat dissipation.
  • the silicon wafer may be simply referred to as a wafer.
  • the traditional thermal paste is used to paste the heat sink on the top of the chip, but the thermal conductivity of the traditional thermal paste is generally lower than 2W / (m ⁇ C), which leads to poor heat dissipation of the chip and becomes the system cooling bottleneck.
  • solder with high thermal conductivity becomes an ideal substitute for thermally conductive adhesives.
  • the thermal conductivity of solder is higher than 60W / (m ⁇ C), which can greatly improve the heat dissipation efficiency of the chip. But solder can't be well welded to the plastic structure of wafers and chips.
  • the chip heat dissipation structure, chip structure, circuit board and supercomputing equipment provided by the present application are intended to solve the above technical problems of the prior art.
  • FIG. 1 is a schematic structural diagram 1 of a chip heat dissipation structure provided by an embodiment of the present application
  • FIG. 2 is a structural schematic diagram 2 of a chip heat dissipation structure provided by an embodiment of the present application
  • FIG. 3 is a chip provided by an embodiment of the present application Schematic diagram 3 of the heat dissipation structure.
  • the chip heat dissipation structure is provided on the chip.
  • the chip heat dissipation structure includes: a metal layer 1, wherein the metal layer 1 covers the chip.
  • the chip heat dissipation structure provided by the present application may be disposed on the chip.
  • the chip includes a wafer 6, a plastic encapsulation structure 8 and a substrate 9; a groove is formed in the plastic encapsulation structure 8, the wafer 6 can be disposed in the groove, and then the plastic encapsulation structure 8 encapsulates the wafer 6
  • the upper surface of the circle 6 is exposed, that is, exposed die structure; the plastic encapsulation structure 8 is fixedly disposed on one side of the substrate 9; in addition, at least one solder ball 9 can also be disposed on the other side of the substrate 9 9 is used to connect with the circuit board, and then fix the chip on the circuit board.
  • the present application covers the wafer 8 and the plastic encapsulation structure 10 with a metal layer 1 at the same time to achieve soldering Way to connect the chip and the external heat sink 2.
  • the shape of the wafer 6 may be circular, or rectangular, or square, or trapezoidal, or other regular shapes, or other irregular shapes; the shape of the wafer 6 is not limited by this application. For the material of wafer 6, this application does not limit.
  • the shape of the plastic encapsulation structure 8 is not limited in this application, only the plastic encapsulation structure 8 is needed to encapsulate the wafer 6.
  • the material of the plastic sealing structure 8 is not limited in this application.
  • the metal layer 1 may be grid-shaped, so that the cost of the metal layer 1 can be saved.
  • the chip heat dissipation structure further includes a heat sink 2, wherein the metal layer 1 covers the chip, that is, the metal layer 1 covers the wafer 6 and the plastic encapsulation structure 8; between the heat sink 2 and the metal layer 1 Connect by soldering.
  • the shape and size of the radiator 2 are not limited in this application.
  • FIG. 4 is a schematic structural diagram 1 of a heat sink provided by an embodiment of the present application.
  • the heat sink 2 is composed of a bottom plate 3 and at least one heat dissipation fin 4. The connection is fixed, and the bottom sheet 3 is welded to the surface of the metal layer 1.
  • FIG. 5 is a schematic structural diagram 2 of a heat sink provided by an embodiment of the present application.
  • the second plate is formed, and there is a preset angle between the first plate and the second plate, the preset angle may be in the range of 180 degrees to 90 degrees;
  • the bottom sheet 3 is fixedly disposed on the lower surface of the connecting portion 5; in addition, a gripper may be provided on one of the heat dissipation fins 6 of the heat sink 2.
  • the chip heat dissipation structure composed of a metal layer 1
  • the chip heat dissipation structure is used to be disposed on the chip, and the metal layer 1 covers the wafer 6 and the plastic encapsulation structure 8 of the chip; Connect radiator 2.
  • the layer has a higher thermal conductivity, thereby solving the problem of the heat dissipation bottleneck of the adhesive material in the chip; it can improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • FIG. 6 is a schematic structural diagram 1 of another chip heat dissipation structure provided by an embodiment of the present application
  • FIG. 7 is a structural schematic diagram 2 of another chip heat dissipation structure provided by an embodiment of the present application, based on the embodiment shown in FIG. 1
  • the area of the metal layer 1 is the same as the area of the upper surface of the chip.
  • the metal layer 1 is a silver glue layer.
  • the thickness of the silver glue layer is 1 to 5 microns.
  • the heat sink 2 is soldered on the metal layer 1 through the solder layer 7.
  • the solder in the solder layer 7 is tin.
  • the thickness of the solder layer 7 is 0.1-0.15 mm.
  • the area of the solder layer 7 is the same as the area of the metal layer 1, or the area of the solder layer 7 is the same as the area of the lower surface of the heat sink 2.
  • the metal layer 1 is a metal layer 1 with a uniform thickness; if the upper surface of the wafer 6 is lower than the upper surface of the plastic encapsulation structure 8, the metal layer 1 is embedded in the plastic encapsulation structure 8; if the upper surface of the wafer 6 is higher than the upper surface of the plastic encapsulation structure 8, the wafer 6 is embedded in the metal layer 1.
  • the metal layer 1 is covered on the upper surfaces of the wafer 6 and the plastic encapsulation structure 8.
  • the material of the metal layer 1 is silver glue, that is, the metal layer 1 is a silver glue layer, and then the silver glue layer covers the upper surfaces of the wafer 6 and the plastic encapsulation structure 8.
  • the thickness of the silver adhesive layer can be set as the following parameters; the thickness of the silver adhesive layer is 1 ⁇ 5 microns, preferably, the thickness of the silver glue layer is 1 micron.
  • a solder layer is provided on the silver glue layer; the heat sink 2 and the solder layer 7 are soldered.
  • the material of the solder layer 7 is tin.
  • the thickness of the solder layer 7 is 0.1-0.15 mm; preferably, the thickness of the solder layer 7 is 0.13 mm.
  • the thermal conductivity of the solder layer 7 is higher than 60 W / (m ⁇ C), which can improve the heat dissipation effect of the chip.
  • the area of the silver paste layer is the same as the area of the upper surface of the chip, that is, the area of the silver paste layer is equal to the sum of the area of the upper surface of the wafer 6 and the area of the upper surface of the plastic encapsulation structure 8. As shown in FIG. 7, the area of the silver paste layer is the same as the area of the upper surface of the chip.
  • the area of the solder layer 7 provides the following methods.
  • the area of the solder layer 7 is the same as the area of the silver paste layer, and the area of the silver paste layer is the same as the area of the upper surface of the chip.
  • FIG. 8 is a schematic structural diagram 3 of another chip heat dissipation structure provided by an embodiment of the present application. As shown in FIG. 8, the area of the solder layer 7 and the area of the silver glue layer are Differently, the area of the silver paste layer is the same as the area of the upper surface of the chip.
  • FIG. 9 is a schematic structural diagram 4 of another chip heat dissipation structure provided by an embodiment of the present application.
  • the area of the solder layer 7 and the lower surface of the heat sink 2 The area of is the same; wherein, the area of the solder layer 7 is different from the area of the silver paste layer, and the area of the silver paste layer is the same as the area of the upper surface of the chip.
  • the area of the solder layer 7 is the same as the area of the bottom surface of the heat sink 2, which is favorable for a good connection between the heat sink 2 and the solder layer 7.
  • the area of the solder layer 7 is the same as the area of the lower surface of the heat sink 2; wherein, the area of the solder layer 7 is the same as the area of the silver glue layer, The area of the silver paste layer is the same as the area of the upper surface of the chip.
  • the positional relationship between the silver glue layer and the chip includes the following embodiments.
  • FIG. 10 is a schematic structural diagram 5 of another chip heat dissipation structure provided by an embodiment of the present application. As shown in FIG. 10, if the upper surface of the wafer 6 is molded with plastic The upper surface of the structure 8 is flush, and the silver adhesive layer is a silver adhesive layer with a uniform thickness.
  • FIG. 11 is a schematic structural diagram 6 of another chip heat dissipation structure provided by an embodiment of the present application. As shown in FIG. 11, if the upper surface of the wafer 6 is lower than On the upper surface of the plastic packaging structure 8, the thickness of the silver adhesive layer is not uniform, and the silver adhesive layer will be embedded in the groove of the plastic packaging structure 8.
  • FIG. 12 is a schematic structural view 7 of another chip heat dissipation structure provided by an embodiment of the present application. As shown in FIG. 12, if the upper surface of the wafer 6 is higher than On the upper surface of the plastic packaging structure 8, the thickness of the silver paste layer is not uniform, and the wafer 6 is embedded in the silver paste layer.
  • the process of obtaining the chip heat dissipation structure is the following process.
  • the first step is wafer cutting.
  • FIG. 13 is a schematic structural diagram of a diced wafer according to an embodiment of the present application. As shown in FIG. 13, the wafer 6 is first diced to obtain the diced wafer 6 shown in FIG.
  • the second step is wafer mounting.
  • FIG. 14 is a schematic diagram 1 of a process flow of a chip provided by an embodiment of the present application. As shown in FIG. 14, the cut wafer 6 is respectively mounted on the substrate 9 of each chip.
  • the third step is chip molding.
  • FIG. 15 is a second schematic flowchart of the chip process provided by the embodiment of the present application. As shown in FIG. 15, the wafer 6 on each substrate 9 is subjected to plastic packaging, that is, the plastic packaging structure 8 is used to encapsulate the wafer 6.
  • the fourth step is silver offset printing.
  • FIG. 16 is a schematic diagram 3 of a process flow of a chip provided by an embodiment of the present application. As shown in FIG. 16, a silver paste printing technology is used to provide a silver paste layer on the upper surface of the chip.
  • the silver glue is cured.
  • the silver glue curing process is performed to cure the silver glue layer on the upper surface of the chip.
  • the sixth step is the separation process.
  • FIG. 17 is a fourth schematic flowchart of the chip process provided by the embodiment of the present application. As shown in FIG. 17, each chip is subjected to strip separation processing (Strip Simulation) to obtain each chip.
  • Strip Simulation strip separation processing
  • the eighth step soldering.
  • the solder layer 7 may be provided on the silver glue layer, and then the heat sink 2 and the solder layer 7 are soldered.
  • a chip heat dissipation structure composed of a metal layer 1 is provided.
  • the chip heat dissipation structure is provided on the chip.
  • the metal layer 1 covers the wafer 6 and the plastic encapsulation structure 8 of the chip.
  • the heat sink 2 is soldered through the solder layer 7 On the metal layer 1; wherein, the metal layer 1 is a silver glue layer.
  • the heat sink 2 can be soldered to the silver paste layer through the solder layer, and then the radiator 2 is fixed to the top of the chip;
  • the main component of the solder layer is metal
  • the tin and silver adhesive layers have a higher thermal conductivity than the epoxy adhesive materials mounted on traditional radiators, thus solving the problem of the heat dissipation bottleneck of the adhesive materials in the chip; the silver adhesive layer and the solder layer 7 further accelerate the chip Heat dissipation; it can improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • FIG. 18 is a schematic structural diagram 1 of a chip structure provided by an embodiment of the present application
  • FIG. 19 is a structural schematic diagram 2 of a chip structure provided by an embodiment of the present application.
  • the chip structure includes a chip body and a chip The chip heat dissipation structure on the body, wherein the chip heat dissipation structure adopts the chip heat dissipation structure provided in the above embodiment.
  • the chip body includes a wafer 6, a plastic encapsulation structure 8 and a substrate 9; a groove is formed in the plastic encapsulation structure 8, the wafer 6 can be disposed in the groove, and then the plastic encapsulation structure 8 encapsulates the wafer 6, And the upper surface of the wafer 6 is exposed; the plastic encapsulation structure 8 is fixedly arranged on one side of the substrate 9; in addition, at least one solder ball 9 can also be provided on the other side of the substrate 9, the solder ball 9 is used for Connect with the circuit board, and then fix the chip on the circuit board.
  • the chip heat dissipation structure provided in the above embodiment is provided on the chip body, and the metal layer 1 of the chip heat dissipation structure is provided on the wafer 6 and the plastic encapsulation structure 8 of the chip body.
  • the structure and principle of the chip heat dissipation structure can be referred to the above embodiments, and will not be repeated here.
  • At least one hole may be formed in the plastic packaging structure 8; one or more holes in the at least one hole are provided with a heat conductive structure.
  • the heat conductive structure is a metal heat conductive structure or a non-metal heat conductive structure. Therefore, by opening a hole in the plastic packaging structure 8 and providing a heat conducting structure in the hole, the chip structure is further radiated.
  • the material of the metal heat conduction structure includes at least one or more of copper, aluminum, silver, tin, gold, iron, and aluminum alloy.
  • the material of the non-metallic heat conductive structure includes at least one or more of resin, ceramic, graphite, graphene, and water.
  • the chip heat dissipation structure provided in the above embodiment is provided on the chip body.
  • the chip heat dissipation structure is used to be disposed on the chip, and the metal layer 1 covers the wafer 6 and the plastic encapsulation structure 8 of the chip; in addition, a heat sink can be connected to the metal layer 1.
  • the heat sink By adding a silver paste layer on the top of the chip by silver paste printing, the heat sink can be soldered to the silver paste layer through the solder layer, and then the radiator is fixed to the top of the chip; the main component of the solder layer is metal tin,
  • the silver adhesive layer has a higher thermal conductivity than epoxy adhesive materials mounted on traditional radiators, thus solving the problem of the heat dissipation bottleneck of the adhesive materials in the chip; the silver adhesive layer and the solder layer further accelerate the heat dissipation of the chip; Improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • FIG. 20 is a schematic structural diagram of a circuit board provided by an embodiment of the present application. As shown in FIG. 20, the circuit board 11 of the embodiment of the present application is provided with at least one chip structure of the foregoing embodiment.
  • the circuit board 11 is provided with at least one chip structure of the foregoing embodiment, and the chip structure is fixedly connected with the solder ball and the circuit board 11.
  • At least one chip structure may be provided on the upper surface of the circuit board 11; or, at least one chip structure may be provided on the upper surface of the circuit board 11, and at least one chip structure may be provided on the lower surface of the circuit board 11.
  • the specific structure of the chip structure on the circuit board 11 may be the same or different.
  • the upper surface of the wafer in one chip structure on the circuit board 11 is flush with the upper surface of the plastic encapsulation structure, and the upper surface of the wafer in the other chip structure on the circuit board 11 is lower than the upper surface of the plastic encapsulation structure.
  • a chip heat dissipation structure provided by the above embodiment is provided on the chip body.
  • the heat sink can be soldered to the silver paste layer through the solder layer, and then the radiator is fixed to the top of the chip; the main component of the solder layer is metal tin,
  • the silver adhesive layer has a higher thermal conductivity, which solves the problem of the heat dissipation bottleneck of the adhesive in the chip; the silver adhesive layer and the solder layer further accelerate the heat dissipation of the chip Improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • FIG. 21 is a schematic structural diagram of a supercomputing device provided by an embodiment of the present application. As shown in FIG. 21, at least one circuit board 11 provided by the foregoing embodiment is provided in the supercomputing device provided by the embodiment of the present application.
  • circuit boards 11 in the supercomputing device are connected in parallel with each other.
  • the chassis of the supercomputing device may be provided with a chute, and the chute is used for sliding connection with each circuit board 11 in the supercomputing device.
  • fans can be provided on both sides of the chassis of the supercomputing device, and the cooling air channels of the fans can be consistent with the heat dissipation cavity of the radiator on the circuit board 11, so as to quickly dissipate the heat generated by the circuit board 11 in the chassis To the outside of the chassis, to provide the performance of supercomputing equipment.
  • circuit board 11 is provided in the supercomputing device, and the circuit board 11 uses the circuit board 11 provided in the foregoing embodiment.
  • the structure and function of the circuit board 11 can be referred to the introduction of the above embodiments, and will not be repeated here.
  • a plurality of circuit boards 11 may be connected in parallel, and then the parallel circuit boards 11 may be installed in a supercomputing device.
  • the supercomputing device may be a supercomputing server.
  • connection method between the circuit board 11 and the supercomputing device can be a fixed connection method or a sliding connection method.
  • one or more sliding slots may be provided on the chassis of the supercomputing device, and then the circuit board 11 is disposed in the sliding slot, so that the circuit board 11 may slide on the sliding slot.
  • each circuit board 11 in the multiple circuit boards 11 may be the same or different.
  • Each circuit board 11 is provided with at least one chip structure of the above embodiment, and the chip structure is fixedly connected with the solder ball and the circuit board 11.
  • one or more circuit boards 11 are provided by providing the above embodiments in a supercomputing device, at least one chip structure of the above embodiments is provided on each circuit board 11, and the above embodiments are provided on the chip structure Provided chip heat dissipation structure.
  • the heat sink By adding a silver paste layer on the top of the chip by silver paste printing, the heat sink can be soldered to the silver paste layer through the solder layer, and then the radiator is fixed to the top of the chip; the main component of the solder layer is metal tin
  • the silver adhesive layer has a higher thermal conductivity than epoxy adhesive materials mounted on traditional radiators, thus solving the problem of the heat dissipation bottleneck of the adhesive materials in the chip; the silver adhesive layer and the solder layer further accelerate the heat dissipation of the chip; Improve the heat dissipation effect of the chip and prevent a large amount of heat from damaging the chip.
  • first, second, etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element” are consistently renamed and all occurrences of The “second component” can be renamed consistently.
  • the first element and the second element are both elements, but they may not be the same element.

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Abstract

本申请实施例涉及一种芯片散热结构、芯片结构、电路板和超算设备，该芯片散热结构包括：金属层，其中，金属层覆盖在芯片上。通过在芯片顶部增加一个金属层，从而可以通过焊料层将散热器焊接在金属层上，进而将散热器固定到芯片的顶部；焊料层的主要成分为金属锡，金属层相对于传统散热器贴装的环氧树脂胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；可以提升芯片的散热效果，防止大量的热量损伤芯片。

Description

芯片散热结构、芯片结构、电路板和超算设备 技术领域
本申请涉及芯片的散热领域，尤其涉及一种芯片散热结构、芯片结构、电路板和超算设备。
背景技术
目前的计算设备中，通常利用导热胶在芯片顶部粘贴散热器的方式来为电路板上的芯片进行散热。
但是，传统导热胶的导热系数普遍低于2瓦/米·度(W/(m·C))，导致芯片的散热效果并不理想。
发明内容
本申请提供一种芯片散热结构、芯片结构、电路板和超算设备，以解决现有的芯片的散热效果并不理想的问题。
本申请实施例提供了一种芯片散热结构，设置在芯片上，所述芯片散热结构包括：金属层，其中，所述金属层覆盖在所述芯片上。
进一步地，所述芯片散热结构还包括：与所述金属层连接的散热器。
进一步地，所述芯片包括晶圆和塑封结构；
并且，所述金属层覆盖在所述芯片的晶圆和塑封结构上。
进一步地，所述晶圆的上表面裸露。
进一步地，所述金属层的面积与所述芯片的上表面的面积相同。
进一步地，所述金属层为银胶层。
进一步地，所述银胶层的厚度为1～5微米。
进一步地，所述散热器通过焊料层焊接在所述金属层上。
进一步地，所述焊料层中的焊料为锡。
进一步地，所述焊料层的厚度为0.1-0.15毫米。
进一步地，所述焊料层的面积与所述金属层的面积相同，或者，所述焊料层的面积与所述散热器的下表面的面积相同。
进一步地，若所述晶圆的上表面与所述塑封结构的上表面齐平，所述金 属层为厚度均匀的金属层；
若所述晶圆的上表面低于所述塑封结构的上表面，所述金属层嵌入到所述塑封结构中；
若所述晶圆的上表面高于所述塑封结构的上表面，所述晶圆嵌入到所述金属层中。
本申请实施例还提供了一种芯片结构，包括芯片本体以及设置在所述芯片本体上的如上任一项所述的芯片散热结构。
本申请实施例还提供了一种电路板，所述电路板上设置有至少一个如上所述的芯片结构。
本申请实施例还提供了一种超算设备，所述超算设备中设置有至少一个如上所述的电路板。
在以上的各方面中，通过提供由金属层构成的芯片散热结构，芯片散热结构用于设置在芯片上，金属层覆盖在芯片的晶圆和塑封结构上；此外，可以在金属层上连接散热器。在芯片顶部增加一个金属层，从而可以通过焊料层将散热器焊接在金属层上，进而将散热器固定到芯片的顶部；焊料层的主要成分为金属锡，金属层相对于传统散热器贴装的环氧树脂(epoxy)胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；可以提升芯片的散热效果，防止大量的热量损伤芯片。
附图说明
一个或多个实施例通过与之对应的附图进行示例性说明，这些示例性说明和附图并不构成对实施例的限定，附图中具有相同参考数字标号的元件示为类似的元件，附图不构成比例限制，并且其中：
图1为本申请实施例提供的一种芯片散热结构的结构示意图一；
图2为本申请实施例提供的一种芯片散热结构的结构示意图二；
图3为本申请实施例提供的一种芯片散热结构的结构示意图三；
图4为本申请实施例提供的散热器的结构示意图一；
图5为本申请实施例提供的散热器的结构示意图二；
图6为本申请实施例提供的另一种芯片散热结构的结构示意图一；
图7为本申请实施例提供的另一种芯片散热结构的结构示意图二；
图8为本申请实施例提供的另一种芯片散热结构的结构示意图三；
图9为本申请实施例提供的另一种芯片散热结构的结构示意图四；
图10为本申请实施例提供的另一种芯片散热结构的结构示意图五；
图11为本申请实施例提供的另一种芯片散热结构的结构示意图六；
图12为本申请实施例提供的另一种芯片散热结构的结构示意图七；
图13为本申请实施例提供的切割后的晶圆的结构示意图；
图14为本申请实施例提供的芯片的工艺流程示意图一；
图15为本申请实施例提供的芯片的工艺流程示意图二；
图16为本申请实施例提供的芯片的工艺流程示意图三；
图17为本申请实施例提供的芯片的工艺流程示意图四；
图18为本申请实施例提供的芯片结构的结构示意图一；
图19为本申请实施例提供的芯片结构的结构示意图二；
图20为本申请实施例提供的电路板的结构示意图；
图21为本申请实施例提供的超算设备的结构示意图。
附图标记：
1-金属层 2-散热器 3-底片
4-散热翅片 5-连接部 6-晶圆
7-焊料层 8-塑封结构 9-基板
10-锡球 11-电路板  
具体实施方式
本申请实施例应用于芯片中。需要说明的是，当本申请实施例的方案应用于现在芯片或未来可能出现的芯片时，各个结构的名称可能发生变化，但这并不影响本申请实施例方案的实施。
需要指出的是，本申请实施例中涉及的名词或术语可以相互参考，不再赘述。
现有技术中，对晶圆进行露die封装，是指把晶圆外露，进而可以达到更好的散热目的，其中，硅晶圆可以简称为晶圆。在露die封装的同时采用传统的导热胶在芯片顶部粘贴散热器，但是传统导热胶的导热系数普遍低于2W/(m·C)，进而导致芯片的散热效果不佳，成为系统散热瓶颈。为了达到更 好的散热效果，具有高导热性能的焊料(solder)成为导热胶的理想替代材料，solder的导热系数高于60W/(m·C)，能够极大程度的改善芯片的散热效率。但是solder并不能和晶圆以及芯片的塑封结构进行很好的焊接。
本申请提供的芯片散热结构、芯片结构、电路板和超算设备，旨在解决现有技术的如上技术问题。
为了能够更加详尽地了解本申请实施例的特点与技术内容，下面结合附图对本申请实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本申请实施例。在以下的技术描述中，为方便解释起见，通过多个细节以提供对所披露实施例的充分理解。然而，在没有这些细节的情况下，一个或多个实施例仍然可以实施。在其它情况下，为简化附图，熟知的结构和装置可以简化展示。
图1为本申请实施例提供的一种芯片散热结构的结构示意图一，图2为本申请实施例提供的一种芯片散热结构的结构示意图二，图3为本申请实施例提供的一种芯片散热结构的结构示意图三，如图1-图3所示，该芯片散热结构设置在芯片上，该芯片散热结构包括：金属层1，其中，金属层1覆盖在芯片上。
示例性地，本申请提供的芯片散热结构可以设置在芯片上。其中，芯片包括了晶圆6、塑封结构8和基板9；在塑封结构8上开设凹槽，可以将晶圆6设置在凹槽内，进而塑封结构8将晶圆6进行封装，并且与晶圆6的上表面是外露的，即为露die结构；将塑封结构8固定设置在基板9的一个侧面上；另外，还可以在基板9的另一个侧面上设置至少一个锡球9，锡球9用于与电路板连接，进而将芯片固定在电路板上。
正如前述记载，由于solder并不能和晶圆8以及芯片的塑封结构10进行很好的焊接，因此，本申请通过在晶圆8和塑封结构10上同时覆盖一层金属层1，以实现通过焊接的方式连接芯片和外部的散热器2。
晶圆6的形状可以是圆形、或者可以是长方形、或者是正方形、或者是梯形、或者是其他规则形状、或者是其他不规则形状；对于晶圆6的形状，本申请不做限制。对于晶圆6的材质，本申请不做限制。
对于塑封结构8的形状，本申请不做限制，只需要塑封结构8可以将晶圆6进行塑封即可。对于塑封结构8的材质，本申请不做限制。
可选的，金属层1可以是网格状，从而可以节约金属层1的成本。
另一种实施方式中，芯片散热结构还包括散热器2，其中，金属层1覆盖在芯片上，即金属层1覆盖在晶圆6和塑封结构8上；散热器2与金属层1之间通过焊接方式进行连接。
对于散热器2的形状、大小等，本申请不做限制。
举例来说，图4为本申请实施例提供的散热器的结构示意图一，如图4所示，散热器2由底片3和至少一个散热翅片4构成，每一个散热翅片4与底片3固定连接，并且底片3与金属层1的表面进行焊接。
再举例来说，图5为本申请实施例提供的散热器的结构示意图二，如图5所示，还可以在散热器2上设置有一个连接部5，连接部5由包括第一板和第二板构成，并且第一板与第二板之间呈预设角度，该预设角度可以在180度至90度的范围内；并且，各散热翅片4固定设置在连接部5的上表面，底片3固定设置在连接部5的下表面；此外，在散热器2的其中一个散热翅片6上可以设置一个抓手。
本实施例，通过提供由金属层1构成的芯片散热结构，芯片散热结构用于设置在芯片上，金属层1覆盖在芯片的晶圆6和塑封结构8上；此外，可以在金属层1上连接散热器2。在芯片顶部通过物理溅射的方式增加一个金属层，从而可以通过焊料层将散热器2焊接在金属层上，进而将散热器2固定到芯片的顶部；焊料层的主要成分为金属锡，金属层相对于传统散热器贴装的epoxy胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；可以提升芯片的散热效果，防止大量的热量损伤芯片。
图6为本申请实施例提供的另一种芯片散热结构的结构示意图一，图7为本申请实施例提供的另一种芯片散热结构的结构示意图二，在图1所示实施例的基础上，如图6和图7所示，金属层1的面积与芯片的上表面的面积相同。
可选的，金属层1为银胶层。银胶层的厚度为1～5微米。
可选的，散热器2通过焊料层7焊接在金属层1上。焊料层7中的焊料为锡。焊料层7的厚度为0.1-0.15毫米。
可选的，焊料层7的面积与金属层1的面积相同，或者，焊料层7的面 积与散热器2的下表面的面积相同。
可选的，若晶圆6的上表面与塑封结构8的上表面齐平，金属层1为厚度均匀的金属层1；若晶圆6的上表面低于塑封结构8的上表面，金属层1嵌入到塑封结构8中；若晶圆6的上表面高于塑封结构8的上表面，晶圆6嵌入到金属层1中。
示例性地，在图1所示实施例的基础上，将金属层1覆盖在晶圆6和塑封结构8的上表面上。
本实施例中，金属层1的材料为银胶，即金属层1为银胶层，进而银胶层覆盖在晶圆6和塑封结构8的上表面上。
为了有利于上述银胶层与芯片、散热器2的连接，以及有利于上述银胶层进行导热和对芯片进行散热，可以设置上述银胶层的厚度为以下参数；银胶层的厚度为1～5微米，优选的，银胶层的厚度为1微米。
本实施例中，在银胶层上设置一层焊料层；散热器2与焊料层7进行焊接。焊料层7的材料为锡。可选的，焊料层7的厚度为0.1-0.15毫米；优选的，焊料层7的厚度为0.13毫米。焊料层7导热系数高于60W/(m·C)，可以提高芯片的散热效果。
本实施例中，银胶层的面积与芯片的上表面的面积相同，即银胶层的面积等于晶圆6的上表面的面积与塑封结构8的上表面的面积之和。如图7所示，银胶层的面积与芯片的上表面的面积相同。
本实施例中，焊料层7的面积提供了以下几种方式。
焊料层7的面积的第一种实施方式：如图7所示，焊料层7的面积与银胶层的面积相同，银胶层的面积与芯片的上表面的面积相同。
焊料层7的面积的第二种实施方式：图8为本申请实施例提供的另一种芯片散热结构的结构示意图三，如图8所示，焊料层7的面积与银胶层的面积是不同的，银胶层的面积与芯片的上表面的面积相同。
焊料层7的面积的第三种实施方式：图9为本申请实施例提供的另一种芯片散热结构的结构示意图四，如图9所示，焊料层7的面积与散热器2的下表面的面积是相同；其中，焊料层7的面积与银胶层的面积不同，银胶层的面积与芯片的上表面的面积相同。焊料层7的面积与散热器2的底面面积相同，有利于将散热器2与焊料层7进行良好的连接。
焊料层7的面积的第四种实施方式：如图7所示，焊料层7的面积与散热器2的下表面的面积是相同；其中，焊料层7的面积与银胶层的面积相同，银胶层的面积与芯片的上表面的面积相同。
银胶层与芯片的位置关系包括以下几种实施方式。
银胶层与芯片的位置关系的第一种实施方式：图10为本申请实施例提供的另一种芯片散热结构的结构示意图五，如图10所示，如果晶圆6的上表面与塑封结构8的上表面齐平，则银胶层为厚度均匀的银胶层。
银胶层与芯片的位置关系的第二种实施方式：图11为本申请实施例提供的另一种芯片散热结构的结构示意图六，如图11所示，如果晶圆6的上表面低于塑封结构8的上表面，则银胶层为厚度并不均匀，银胶层会嵌入到塑封结构8的凹槽中。
银胶层与芯片的位置关系的第三种实施方式：图12为本申请实施例提供的另一种芯片散热结构的结构示意图七，如图12所示，如果晶圆6的上表面高于塑封结构8的上表面，则银胶层为厚度并不均匀，晶圆6嵌入到银胶层中去。
本实施例中，得到芯片散热结构的工艺过程为以下过程。
第一步，晶圆切割。
图13为本申请实施例提供的切割后的晶圆的结构示意图，如图13所示，首先对晶圆6进行切割，得到如图13所示的切割后的晶圆6。
第二步，晶圆贴装。
图14为本申请实施例提供的芯片的工艺流程示意图一，如图14所示，将切割后的晶圆6分别贴装到每一个芯片的基板9上。
第三步，芯片塑封。
图15为本申请实施例提供的芯片的工艺流程示意图二，如图15所示，对每一个基板9上的晶圆6进行塑封处理，即采用塑封结构8封装晶圆6。
第四步，银胶印刷。
图16为本申请实施例提供的芯片的工艺流程示意图三，如图16所示，采用银胶印刷技术，在芯片的上表面设置银胶层。
第五步，银胶固化。
进行银胶固化处理，使得芯片的上表面的银胶层固化。
第六步，分离处理。
图17为本申请实施例提供的芯片的工艺流程示意图四，如图17所示，对各个芯片进行带状分离处理(Strip Singulation)，得到每一个芯片。
第八步，焊料焊接。
可以在银胶层上设置焊料层7，然后将散热器2与焊料层7进行焊接。
本实施例，通过提供由金属层1构成的芯片散热结构，芯片散热结构用于设置在芯片上，金属层1覆盖在芯片的晶圆6和塑封结构8上，散热器2通过焊料层7焊接在金属层1上；其中，金属层1为银胶层。通过在芯片顶部通过银胶印刷的方式增加一个银胶层，从而可以通过焊料层将散热器2焊接在银胶层上，进而将散热器2固定到芯片的顶部；焊料层的主要成分为金属锡，银胶层相对于传统散热器贴装的epoxy胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；银胶层和焊料层7进一步的加快了芯片的散热；可以提升芯片的散热效果，防止大量的热量损伤芯片。
图18为本申请实施例提供的芯片结构的结构示意图一，图19为本申请实施例提供的芯片结构的结构示意图二，如图18和图19所示，芯片结构包括芯片本体以及设置在芯片本体上的芯片散热结构，其中，芯片散热结构采用上述实施例提供的芯片散热结构。
示例性地，芯片本体包括了晶圆6、塑封结构8和基板9；在塑封结构8上开设凹槽，可以将晶圆6设置在凹槽内，进而塑封结构8将晶圆6进行封装，并且与晶圆6的上表面是外露的；将塑封结构8固定设置在基板9的一个侧面上；另外，还可以在基板9的另一个侧面上设置至少一个锡球9，锡球9用于与电路板连接，进而将芯片固定在电路板上。
然后在芯片本体上设置上述实施例提供的芯片散热结构，芯片散热结构的金属层1设置在芯片本体的晶圆6和塑封结构8上。芯片散热结构的结构和原理可以参见上述实施例，不再赘述。
本实施例中，可以在塑封结构8上开设有至少一个孔；至少一个孔中的一个或多个孔中设置有导热结构。可选的，导热结构为金属导热结构或非金属导热结构。从而通过在塑封结构8上开孔，并在孔中设置导热结构，进一步的对芯片结构进行散热。
例如，金属导热结构的材料包括铜、铝、银、锡、金、铁、铝合金中的至少一种或多种。非金属导热结构的材料包括树脂、陶瓷、石墨、石墨烯、水中的至少一种或多种。
本实施例，通过在芯片本体上设置上述实施例提供的芯片散热结构。通过提供由金属层1构成的芯片散热结构，芯片散热结构用于设置在芯片上，金属层1覆盖在芯片的晶圆6和塑封结构8上；此外，可以在金属层1上连接散热器。通过在芯片顶部通过银胶印刷的方式增加一个银胶层，从而可以通过焊料层将散热器焊接在银胶层上，进而将散热器固定到芯片的顶部；焊料层的主要成分为金属锡，银胶层相对于传统散热器贴装的epoxy胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；银胶层和焊料层进一步的加快了芯片的散热；可以提升芯片的散热效果，防止大量的热量损伤芯片。
图20为本申请实施例提供的电路板的结构示意图，如图20所示，本申请实施例的电路板11上设置有至少一个上述实施例的芯片结构。
示例性地，电路板11上设置有至少一个上述实施例的芯片结构，芯片结构同锡球与电路板11进行固定连接。
对于电路板11上的芯片结构的位置和个数不做限制。例如，可以在电路板11的上表面设置至少一个芯片结构；或者，可以在电路板11的上表面设置至少一个芯片结构，并且，在电路板11的下表面设置至少一个芯片结构。
电路板11上的芯片结构的具体结构，可以相同或不同。例如，电路板11上的一个芯片结构中晶圆的上表面与塑封结构的上表面齐平，电路板11上的另一个芯片结构中晶圆的上表面低于塑封结构的上表面。
其中，芯片结构的结构和原理可以参见上述实施例，不再赘述。
本实施例，通过在电路板11上设置有至少一个上述实施例的芯片结构，在芯片本体上设置上述实施例提供的芯片散热结构。通过在芯片顶部通过银胶印刷的方式增加一个银胶层，从而可以通过焊料层将散热器焊接在银胶层上，进而将散热器固定到芯片的顶部；焊料层的主要成分为金属锡，银胶层相对于传统散热器贴装的epoxy胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；银胶层和焊料层进一步的加快了芯片的散热； 可以提升芯片的散热效果，防止大量的热量损伤芯片。
图21为本申请实施例提供的超算设备的结构示意图，如图21所示，本申请实施例提供的超算设备中设置有至少一个上述实施例提供的电路板11。
可选的，超算设备中的各电路板11之间相互并联。
可选的，超算设备的机箱上可设置有滑槽，滑槽用于与超算设备中的各电路板11滑动连接。
可选的，超算设备的机箱两侧还可设置有风扇，风扇的散热风道可与电路板11上的散热器的散热腔保持一致，从而快速的将机箱内电路板11产生的热量散发到机箱外，进而提供超算设备的性能。
示例性地，在超算设备中设置一个或多个电路板11，该电路板11采用上述实施例提供的电路板11。电路板11的结构和功能，可以参见上述实施例的介绍，不再赘述。
本实施例中，可以将多个电路板11进行并联，然后将并联的电路板11设置在超算设备中。在一种实施方式中，超算设备可以为超算服务器。
电路板11与超算设备的连接方式可以选择固定连接或滑动连接的方式。示例性地，可以在超算设备的机箱上设置有一个或多个滑槽，然后将电路板11设置在滑槽中，使得电路板11可以在滑槽上滑动。
其中，在超算设备中设置多个电路板11的时候，多个电路板11中的每一个电路板11的结构可以相同或不同。
每一个电路板11上设置有至少一个上述实施例的芯片结构，芯片结构同锡球与电路板11进行固定连接。
其中，芯片结构的结构和原理可以参见上述实施例，不再赘述。
本实施例，通过在超算设备中设置上述实施例提供一个或多个的电路板11，在每一个电路板11上设置有至少一个上述实施例的芯片结构，在芯片结构上设置上述实施例提供的芯片散热结构。通过在芯片顶部通过银胶印刷的方式增加一个银胶层，从而可以通过焊料层将散热器焊接在银胶层上，进而将散热器固定到芯片的顶部；焊料层的主要成分为金属锡，银胶层相对于传统散热器贴装的epoxy胶材，具有更高的导热系数，从而解决了芯片中胶材的散热瓶颈的问题；银胶层和焊料层进一步的加快了芯片的散热；可以提升 芯片的散热效果，防止大量的热量损伤芯片。
当用于本申请中时，虽然术语“第一”、“第二”等可能会在本申请中使用以描述各元件，但这些元件不应受到这些术语的限制。这些术语仅用于将一个元件与另一个元件区别开。比如，在不改变描述的含义的情况下，第一元件可以叫做第二元件，并且同样第，第二元件可以叫做第一元件，只要所有出现的“第一元件”一致重命名并且所有出现的“第二元件”一致重命名即可。第一元件和第二元件都是元件，但可以不是相同的元件。
本申请中使用的用词仅用于描述实施例并且不用于限制权利要求。如在实施例以及权利要求的描述中使用的，除非上下文清楚地表明，否则单数形式的“一个”(a)、“一个”(an)和“所述”(the)旨在同样包括复数形式。类似地，如在本申请中所使用的术语“和/或”是指包含一个或一个以上相关联的列出的任何以及所有可能的组合。另外，当用于本申请中时，术语“包括”(comprise)及其变型“包括”(comprises)和/或包括(comprising)等指陈述的特征、整体、步骤、操作、元素，和/或组件的存在，但不排除一个或一个以上其它特征、整体、步骤、操作、元素、组件和/或这些的分组的存在或添加。
所描述的实施例中的各方面、实施方式、实现或特征能够单独使用或以任意组合的方式使用。
上述技术描述可参照附图，这些附图形成了本申请的一部分，并且通过描述在附图中示出了依照所描述的实施例的实施方式。虽然这些实施例描述的足够详细以使本领域技术人员能够实现这些实施例，但这些实施例是非限制性的；这样就可以使用其它的实施例，并且在不脱离所描述的实施例的范围的情况下还可以做出变化。比如，流程图中所描述的操作顺序是非限制性的，因此在流程图中阐释并且根据流程图描述的两个或两个以上操作的顺序可以根据若干实施例进行改变。作为另一个例子，在若干实施例中，在流程图中阐释并且根据流程图描述的一个或一个以上操作是可选的，或是可删除的。另外，某些步骤或功能可以添加到所公开的实施例中，或两个以上的步骤顺序被置换。所有这些变化被认为包含在所公开的实施例以及权利要求中。
另外，上述技术描述中使用术语以提供所描述的实施例的透彻理解。然 而，并不需要过于详细的细节以实现所描述的实施例。因此，实施例的上述描述是为了阐释和描述而呈现的。上述描述中所呈现的实施例以及根据这些实施例所公开的例子是单独提供的，以添加上下文并有助于理解所描述的实施例。上述说明书不用于做到无遗漏或将所描述的实施例限制到本申请的精确形式。根据上述教导，若干修改、选择适用以及变化是可行的。在某些情况下，没有详细描述为人所熟知的处理步骤以避免不必要地影响所描述的实施例。

Claims (15)

  1. 一种芯片散热结构，设置在芯片上，其特征在于，所述芯片散热结构包括：金属层，其中，所述金属层覆盖在所述芯片上。
  2. 根据权利要求1所述的芯片散热结构，其特征在于，所述芯片散热结构还包括：与所述金属层连接的散热器。
  3. 根据权利要求1所述的芯片散热结构，其特征在于，所述芯片包括晶圆和塑封结构；
    并且，所述金属层覆盖在所述芯片的晶圆和塑封结构上。
  4. 根据权利要求3所述的芯片散热结构，其特征在于，所述晶圆的上表面裸露。
  5. 根据权利要求1所述的芯片散热结构，其特征在于，所述金属层的面积与所述芯片的上表面的面积相同。
  6. 根据权利要求1-5任一项所述的芯片散热结构，其特征在于，所述金属层为银胶层。
  7. 根据权利要求6所述的芯片散热结构，其特征在于，所述银胶层的厚度为1～5微米。
  8. 根据权利要求2所述的芯片散热结构，其特征在于，所述散热器通过焊料层焊接在所述金属层上。
  9. 根据权利要求8所述的芯片散热结构，其特征在于，所述焊料层中的焊料为锡。
  10. 根据权利要求9所述的芯片散热结构，其特征在于，所述焊料层的厚度为0.1-0.15毫米。
  11. 根据权利要求8所述的芯片散热结构，其特征在于，所述焊料层的面积与所述金属层的面积相同，或者，所述焊料层的面积与所述散热器的下表面的面积相同。
  12. 根据权利要求3或4所述的芯片散热结构，其特征在于，若所述晶圆的上表面与所述塑封结构的上表面齐平，所述金属层为厚度均匀的金属层；
    若所述晶圆的上表面低于所述塑封结构的上表面，所述金属层嵌入到所述塑封结构中；
    若所述晶圆的上表面高于所述塑封结构的上表面，所述晶圆嵌入到所述 金属层中。
  13. 一种芯片结构，其特征在于，包括：包括芯片本体以及设置在所述芯片本体上的如权利要求1-12任一项所述的芯片散热结构。
  14. 一种电路板，其特征在于，所述电路板上设置有至少一个如权利要求13所述的芯片结构。
  15. 一种超算设备，其特征在于，所述超算设备中设置有至少一个如权利要求14所述的电路板。
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