CN110767619A - 芯片封装的方法、芯片和芯片封装组件 - Google Patents

芯片封装的方法、芯片和芯片封装组件 Download PDF

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Publication number
CN110767619A
CN110767619A CN201911053463.3A CN201911053463A CN110767619A CN 110767619 A CN110767619 A CN 110767619A CN 201911053463 A CN201911053463 A CN 201911053463A CN 110767619 A CN110767619 A CN 110767619A
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China
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metal layer
chip
layer
substrate
hole
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CN201911053463.3A
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赵源
周涛
郭函
曹流圣
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Bitmain Technologies Inc
Beijing Bitmain Technology Co Ltd
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Beijing Bitmain Technology Co Ltd
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Publication of CN110767619A publication Critical patent/CN110767619A/zh
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Abstract

本申请提供一种芯片封装的方法，在利用金属层实现对芯片散热的同时，可以防止该金属层发生翘曲。该方法包括：在基板上制作开孔；将所述芯片嵌埋至所述开孔内；在所述基板的第一表面上，制作用于对所述芯片进行散热的第一金属层和第二金属层，其中，所述第一金属层和所述第二金属层之间设置有间隔层，所述间隔层中设置有至少一个通孔，所述第二金属层覆盖所述间隔层且填充所述至少一个通孔；在所述基板的第二表面上，制作至少一个布线层。

Description

芯片封装的方法、芯片和芯片封装组件
技术领域
本申请实施例涉及芯片技术领域，并且更具体地，涉及一种芯片封装的方法、芯片和芯片封装组件。
背景技术
高密度集成的芯片在运行时所产生的热量会大幅增加，若不及时排除，将会导致芯片封装组件过热而威胁芯片寿命。可以在芯片背面制作金属层 (BacksideMetallization，BSM)对芯片进行散热。但是，由于芯片封装组件的上下两侧的应力不均衡，可能会造成该金属层的翘曲。
发明内容
本申请实施例提供一种芯片封装的方法、芯片和芯片封装组件，在利用金属层实现对芯片散热的同时，可以防止该金属层发生翘曲。
第一方面，提供了一种芯片封装的方法，包括：在基板上制作开孔；将所述芯片嵌埋至所述开孔内；在所述基板的第一表面上，制作用于对所述芯片进行散热的第一金属层和第二金属层，其中，所述第一金属层和所述第二金属层之间设置有间隔层，所述间隔层中设置有至少一个通孔，所述第二金属层覆盖所述间隔层且填充所述至少一个通孔；在所述基板的第二表面上，制作至少一个布线层。
在一种可能的实现方式中，所述在所述基板的第一表面上，制作第一金属层和第二金属层，包括：在所述基板的第一表面上溅射所述第一金属层；在所述第一金属层上覆盖所述间隔层；在所述间隔层上刻蚀出所述至少一个通孔；在具有所述至少一个通孔的所述间隔层上溅射所述第二金属层。
在一种可能的实现方式中，所述至少一个通孔设置于所述间隔层中位于所述芯片上方的部分。
在一种可能的实现方式中，所述第一金属层和所述第二金属层覆盖所述基板和所述芯片的表面。
在一种可能的实现方式中，所述第一金属层和/或所述第二金属层的材料为铜。
在一种可能的实现方式中，所述间隔层为ABF层。
在一种可能的实现方式中，所述方法还包括：对所述第二金属层的表面，进行表面处理。
在一种可能的实现方式中，所述对所述第二金属层的表面，进行表面处理，包括：采用OSP方式，对所述第二金属层的表面进行表面处理。
在一种可能的实现方式中，所述方法还包括：在所述至少一个布线层的表面，制作焊接掩膜，并进行表面处理。
在一种可能的实现方式中，所述在所述至少一个布线层的表面，制作焊接掩膜，并进行表面处理，包括：在所述至少一个布线层的表面，制作焊接掩膜，并采用ENEPIG技术进行表面处理。
在一种可能的实现方式中，所述多个芯片为具有相同结构的算力芯片，所述多个芯片设置于同一电路板上。
第二方面，提供了一种芯片，所述芯片基于第一方面或第一方面的任意可能的实现方式中的方法进行封装。
在一种可能的实现方式中，封装后的所述芯片为算力芯片，具有相同结构的多个所述算力芯片设置于同一电路板上。
第三方面，提供了一种芯片封装组件，包括：基板；芯片，嵌埋在所述基板的开孔内；金属层，制作于所述基板的第一表面，用于对所述芯片进行散热，其中，所述金属层包括第一金属层和第二金属层，所述第一金属层和所述第二金属层之间设置有间隔层，所述间隔层中设置有至少一个通孔，所述第二金属层覆盖所述间隔层且填充所述至少一个通孔；至少一个布线层，制作于所述基板的第二表面。
在一种可能的实现方式中，所述至少一个通孔设置于所述间隔层中位于所述芯片上方的部分。
在一种可能的实现方式中，所述第一金属层和所述第二金属层覆盖所述基板和所述芯片的表面。
在一种可能的实现方式中，所述第一金属层和/或所述第二金属层的材料为铜。
在一种可能的实现方式中，所述间隔层为ABF层。
在一种可能的实现方式中，所述芯片封装组件为算力芯片，具有相同结构的多个所述算力芯片设置于同一电路板上。
基于上述技术方案，在进行芯片封装时，通过将芯片嵌埋至基板的开孔内，并在芯片表面制作双层结构的用于散热的金属层，在实现对芯片散热的同时，可以防止该金属层发生翘曲。
附图说明
图1是本申请实施例的芯片封装方法的示意性流程图。
图2是本申请实施例的金属层的示意图。
图3是本申请实施例的金属层的制作方法的示意性流程图。
图4a至图4d是基于图3所示的方法的工艺流程图。
图5是本申请另一实施例的金属层的示意图。
图6a至图6f是基于图1所示的方法的一种可能的实现方式的示意图。
图7是本申请实施例的芯片封装组件的示意性框图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
高密度集成的芯片在运行时所产生的热量会大幅增加，为了解决芯片顶部的散热问题，可以在芯片背面制作金属层，从而通过该金属镀层实现散热。但是，由于芯片封装组件的上下两侧的应力不均衡，可能会造成金属层的翘曲，影响其使用寿命。
为此，本申请实施例提出了一种芯片封装方案，能够有效地利用金属层对芯片进行散热，在实现对芯片散热的同时，可以防止该金属层发生翘曲。
图1是本申请实施例的芯片封装方法的示意性流程图。如图1所示，该方法包括以下步骤中的部分或全部。
在110中，在基板上制作开孔。
在120中，将芯片嵌埋至该开孔内。
在130中，在基板的第一表面上，制作用于对芯片进行散热的金属层。
其中，该金属层包括第一金属层和第二金属层。
并且，第一金属层和第二金属层覆盖芯片和基板的表面。其中，第一金属层和第二金属层之间设置有间隔层，该间隔层中设置有至少一个通孔，第二金属层覆盖该间隔层且填充该至少一个通孔。
在140中，在基板的第二表面上，制作至少一个布线层。
该实施例中，需要在基板上进行开孔，并将芯片嵌埋至该开孔内。在基板和芯片的一侧制作有第一金属层和第二金属层，第一金属层和第二金属层覆盖芯片和基板的表面。芯片产生的热量可以依次通过第一金属层和第二金属层进行传导，从而实现散热。在基板和芯片的另一侧制作有至少一个布线层，该至少一个布线层包括一个或多个金属层，这些金属层具有特殊的线路结构，用来实现相应的电气功能。
用于对芯片进行散热的第一金属层和第二金属层可以通过背面金属化(Backside Metallizing，BSM)工艺形成，因此，金属层也可以称为BSM层。并且，该BSM层上方还可以焊接散热器，从而进一步改善导热性能。
用于对芯片进行散热的该金属层采用了多层结构，例如图2所示，该金属层405可以包括第一金属层4051和第二金属层4052，其中，第一金属层 4051和第二金属层4052之间设置有间隔层4053，间隔层4053中设置有至少一个通孔，第二金属层4052覆盖间隔层4053且填充该至少一个通孔。相比于单层结构，该BSM层405能够更好地均衡基板另一侧的布线层所产生的应力，防止金属层发生翘曲。
可选地，如图3所示，步骤130可以包括步骤131至134，从而制作出如图2所示的金属层405。
在131中，在基板的第一表面上溅射第一金属层。
在132中，在第一金属层上覆盖间隔层。
在133中，在间隔层上刻蚀出至少一个通孔。
例如，可以采用干刻蚀的方式形成至少一个通孔。
在134中，在具有至少一个通孔的该间隔层上，溅射第二金属层。
其中，采用溅射的方式，可以使第二金属层覆盖间隔层的表面，并且将金属材料溅射至间隔层上的通孔内。这样，芯片顶面的热量可以依次通过第一金属层、通孔内的金属、以及第二金属层传导出去。
例如图4a至图4d所示，其中，图4a所示为第一金属层4051；如图4b所示，在第一金属层表面覆盖间隔材料4053；如图4c所示，在该间隔材料 4053上刻蚀通孔；如图4d所示，在间隔层4053上溅射第二金属层4052。
从图2可以看出，基板401下方设置有布线层403，布线层403中包括金属层M1、金属层M2和金属层M3，由于基板401下侧分布的金属层数量较多，因此容易导致基板401上下两侧的应力分布不均匀，从而使基板上侧的金属层405易发生翘曲。因此，将金属层405设置为双层结构，增加了基板401上侧的支撑强度，能够均衡基板401上下两侧的应力分布，从而尽量避免翘曲，提高封装可靠性。
该实施例对间隔层上的通孔数量、密度和位置等均不作限定。例如，间隔层上的至少一个通孔，可以设置在该间隔层中位于该芯片上方的部分，从而实现对芯片顶部的散热；或者，例如图5所示，该至少一个通孔也可以均匀地分布在间隔层4053。
第一金属层和/或第二金属层可以采用高导热性材料，例如铜、铝等。
该间隔层的材料例如可以是ABF或者导热硅脂等。
应理解，基板上的开孔可以是开通孔，但本申请实施例并不限于此，也可以采用开盲孔的方式替换开通孔的方式。
可选地，该方法还包括：对第二金属层的表面，进行表面处理。
例如，采用有机可焊性抗氧化处理(Organic Solder-ability Preservatives，OSP)方式，对该第二金属层的表面进行表面处理。
可选地，该方法还包括：在该至少一个布线层的表面，制作焊接掩膜，并进行表面处理。
例如，在该至少一个布线层的表面，制作焊接/掩膜(Solder/Mask，S/M)，并采用化学镀镍钯浸金(Electroless Nickel Electroless Palladium Immersion Gold，ENEPIG)技术进行表面处理。
下面以图6a至图6f为例，详细描述基于本申请实施例的一种可能的封装方式。其中，前述的第一表面为图6a至图6f中所示的基板401的上表面，第二表面为基板401的下表面。如图6a至图6f所示，该封装过程包括：
在图6a中，在基板401上制作开孔。
在图6b中，将芯片402嵌埋至基板401的开孔内。
在图6c中，在基板401的下表面制作布线层403。
图6c中的布线层403包括金属层M1、金属层M2和金属层M3。其中，金属层M1、金属层M2和金属层M3彼此之间为填充材料404。其中，在基板401的下表面进行金属层M1的生长，其次依次进行通孔和金属层M2、金属层M3的生长。芯片402的焊盘可以与金属层M1电连接。
在图6d中，在基板401的上表面制作BSM层405。
其中，该BSM层405覆盖芯片402和基板401的上表面，用于对芯片 402进行散热。
BSM层405的具体制作方式可以参考图3和图4所示的方式。
在图6e中，进行S/M以及表面处理，形成S/M层406和表面处理层407。
本申请实施例中，在芯片封装过程中，对各个叠层的制作顺序不做任何限定。例如，在图6a至图6e中，可以依次制作金属层M1至金属层M3后，再制作BSM层。
或者，该至少一个布线层中的部分布线层可以在制作BSM层之前形成，而另一部分布线层在制作BSM层之后形成。例如，依次制作金属层M1、金属层M2、BSM层405和金属层M3。这样，在封装过程中，基板两侧的应力交替变化，可以减轻应力对封装过程的影响。
图6a至图6e中仅以一个芯片为例描述具体的封装过程。在实际封装时，通常同时对多个芯片进行封装，之后再对封装后的多个芯片进行切割，形成独立的芯片封装组件。
例如图6f所示，对封装后的多个芯片进行切割后，可以得到单个芯片。在芯片切割之前，还可以在芯片上打上各自的编码和其他标记等。
本申请实施例还提供一种芯片封装组件，该芯片封装组件可以是基于上述任一实施例中的封装方法对芯片进行封装后形成的。如图7所示，所述芯片封装组件700包括：
基板710；
芯片720，嵌埋在基板710的开孔内；
金属层730，制作于基板710的第一表面，用于对所述芯片720进行散热，其中，所述金属层730包括第一金属层730和第二金属层730，第一金属层730和第二金属层730之间设置有间隔层，所述间隔层中设置有至少一个通孔，第二金属层730覆盖所述间隔层且填充所述至少一个通孔；
至少一个布线层740，制作于基板710的第二表面。
可选地，所述至少一个通孔设置于所述间隔层中位于所述芯片720上方的部分。
可选地，第一金属层730和第二金属层730覆盖基板710和所述芯片720 的表面。
可选地，第一金属层730和/或第二金属层730的材料为铜。
可选地，所述间隔层为ABF层。
本申请实施例对芯片类型不做限定。例如，封装后的所述芯片可以为算力芯片，具有相同结构的多个所述算力芯片设置于同一电路板上。
应理解，对于传统计算机而言，一片印刷电路板(Printed Circuit Board， PCB)上仅放置一个计算处理器芯片，例如中央处理器(Central Processing Unit，CPU)或者图形处理单元(Graphic Processing Unit，GPU)等。而对于采用算力芯片的产品来说，一片PCB(称为算力板)上往往会密集地放置多个结构相同的计算处理器芯片(称为算力芯片)。并且，在这些算力芯片中，至少两个算力芯片会通过串联的方式连接在一起。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

1.一种芯片封装的方法，其特征在于，所述方法包括：
在基板上制作开孔；
将所述芯片嵌埋至所述开孔内；
在所述基板的第一表面上，制作用于对所述芯片进行散热的第一金属层和第二金属层，其中，所述第一金属层和所述第二金属层之间设置有间隔层，所述间隔层中设置有至少一个通孔，所述第二金属层覆盖所述间隔层且填充所述至少一个通孔；
在所述基板的第二表面上，制作至少一个布线层。
2.根据权利要求1所述的方法，其特征在于，所述在所述基板的第一表面上，制作第一金属层和第二金属层，包括：
在所述基板的第一表面上溅射所述第一金属层；
在所述第一金属层上覆盖所述间隔层；
在所述间隔层上刻蚀出所述至少一个通孔；
在具有所述至少一个通孔的所述间隔层上溅射所述第二金属层。
3.根据权利要求1或2所述的方法，其特征在于，所述至少一个通孔设置于所述间隔层中位于所述芯片上方的部分。
4.根据权利要求1或2所述的方法，其特征在于，所述第一金属层和所述第二金属层覆盖所述基板和所述芯片的表面。
5.根据权利要求1或2所述的方法，其特征在于，所述第一金属层和/或所述第二金属层的材料为铜。
6.根据权利要求1或2所述的方法，其特征在于，所述间隔层为味之素复合膜ABF层。
7.根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
对所述第二金属层的表面，进行表面处理。
8.根据权利要求7所述的方法，其特征在于，所述对所述第二金属层的表面，进行表面处理，包括：
采用有机可焊性抗氧化处理OSP方式，对所述第二金属层的表面进行表面处理。
9.根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
在所述至少一个布线层的表面，制作焊接掩膜，并进行表面处理。
10.根据权利要求9所述的方法，其特征在于，所述在所述至少一个布线层的表面，制作焊接掩膜，并进行表面处理，包括：
在所述至少一个布线层的表面，制作焊接掩膜，并采用化学镀镍钯浸金技术ENEPIG进行表面处理。
11.一种芯片，其特征在于，所述芯片基于上述权利要求1至10中任一项所述的方法进行封装。
12.根据权利要求11所述的芯片，其特征在于，封装后的所述芯片为算力芯片，具有相同结构的多个所述算力芯片设置于同一电路板上。
13.一种芯片封装组件，其特征在于，包括：
基板；
芯片，嵌埋在所述基板的开孔内；
金属层，制作于所述基板的第一表面，用于对所述芯片进行散热，其中，所述金属层包括第一金属层和第二金属层，所述第一金属层和所述第二金属层之间设置有间隔层，所述间隔层中设置有至少一个通孔，所述第二金属层覆盖所述间隔层且填充所述至少一个通孔；以及，
至少一个布线层，制作于所述基板的第二表面。
14.根据权利要求13所述的芯片封装组件，其特征在于，所述至少一个通孔设置于所述间隔层中位于所述芯片上方的部分。
15.根据权利要求13或14所述的芯片封装组件，其特征在于，所述第一金属层和所述第二金属层覆盖所述基板和所述芯片的表面。
16.根据权利要求13或14所述的芯片封装组件，其特征在于，所述第一金属层和/或所述第二金属层的材料为铜。
17.根据权利要求13或14所述的芯片封装组件，其特征在于，所述间隔层为味之素复合膜ABF层。
18.根据权利要求13或14所述的芯片封装组件，其特征在于，所述芯片封装组件为算力芯片，具有相同结构的多个所述算力芯片设置于同一电路板上。
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