CN110098162A - 包括导热层的半导体封装件 - Google Patents

包括导热层的半导体封装件 Download PDF

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Publication number
CN110098162A
CN110098162A CN201811580748.8A CN201811580748A CN110098162A CN 110098162 A CN110098162 A CN 110098162A CN 201811580748 A CN201811580748 A CN 201811580748A CN 110098162 A CN110098162 A CN 110098162A
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China
Prior art keywords
layer
heat
semiconductor chip
package part
semiconductor package
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CN201811580748.8A
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English (en)
Inventor
金载春
朴佑炫
张彦铢
赵暎相
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110098162A publication Critical patent/CN110098162A/zh
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Abstract

提供了一种包括导热层的半导体封装件。所述半导体封装件包括：半导体芯片，具有作为有效表面的第一表面和与第一表面相对的第二表面；第一再分布部，设置在第一表面上，第一再分布部包括电连接到半导体芯片的下布线层；导热层，设置在半导体芯片的第二表面上；密封层，围绕半导体芯片的侧表面和导热层的侧表面；以及第二再分布部，设置在密封层上，第二再分布部包括连接到导热层的第一上布线层，第二再分布部包括电连接到半导体芯片的第二上布线层。

Description

包括导热层的半导体封装件
本申请要求于2018年1月29日在韩国知识产权局提交的第10-2018-0010699号韩国专利申请的优先权，该韩国专利申请的公开内容通过引用而全部包含于此。
技术领域
本发明构思涉及一种半导体封装件和制造该半导体封装件的方法。
背景技术
随着电子工业的发展，对电子组件的高性能、高速以及小型化的需求不断增长。根据这种趋势，对电子组件中使用的半导体芯片的小型化以及多功能化的需求也在增长。因此，具有精细间距连接端子的半导体芯片是有益的，并且正在开发具有用于再分布到半导体芯片外部的各种结构的扇出半导体封装件。
发明内容
本发明构思的一方面提供了一种具有改善的可靠性的半导体封装件。
根据本发明构思的一方面，半导体封装件包括：半导体芯片，具有作为有效表面的第一表面和与第一表面相对的第二表面；第一再分布部，设置在第一表面上，第一再分布部包括电连接到半导体芯片的下布线层；导热层，设置在半导体芯片的第二表面上；密封层，围绕半导体芯片的侧表面和导热层的侧表面；以及第二再分布部，设置在密封层上，第二再分布部包括连接到导热层的第一上布线层，第二再分布部包括电连接到半导体芯片的第二上布线层。
根据本发明构思的一方面，半导体封装件包括：核心层，具有贯穿孔；半导体芯片，具有作为有效表面的第一表面和与第一表面相对的第二表面，半导体芯片安装在核心层的贯穿孔中；第一再分布部，设置在第一表面上，第一再分布部包括电连接到半导体芯片的下布线层；导热层，设置在半导体芯片的第二表面上；密封层，围绕半导体芯片的侧表面和导热层的侧表面；以及第二再分布部，设置在密封层上，第二再分布部包括连接到导热层的第一上布线层，第二再分布部包括通过核心层电连接到第一再分布部的第二上布线层。
根据本发明构思的一方面，半导体封装件包括：半导体芯片；第一再分布部，设置在半导体芯片的下表面上，第一再分布部包括电连接到半导体芯片的下布线层；导热层，设置在半导体芯片的上表面上，导热层在平面图中具有与半导体芯片的面积相同的面积；以及第二再分布部，设置在导热层上，第二再分布部包括连接到导热层的上布线层。
附图说明
图1和图2分别是根据本发明构思的示例实施例的半导体封装件的示意性平面图和剖视图；
图3是示出图2的半导体封装件的一部分的分解透视图；
图4至图6是根据本发明构思的示例实施例的半导体封装件的示意性剖视图；
图7和图8是根据本发明构思的示例实施例的半导体封装件的示意性剖视图；
图9是根据本发明构思的示例实施例的半导体封装件的示意性剖视图；
图10是用于解释根据本发明构思的示例实施例的半导体封装件的散热特性的曲线图；
图11A至图11H是示出根据本发明构思的示例实施例的制造半导体封装件的方法的步骤的示意图；以及
图12是根据本发明构思的示例实施例的半导体封装件的示意性剖视图。
具体实施方式
在下文中，将参照附图描述本发明构思的优选实施例。
图1和图2分别是根据示例实施例的半导体封装件的示意性平面图和剖视图。在图1中省略了设置在第一上过孔164a的上部和第二上过孔164b的上部上的组件。
图3是示出图2的半导体封装件的一部分的分解透视图。
参照图1至图3，半导体封装件100可以包括：半导体芯片120；第一再分布部110(也被描述为第一再分布层)，设置在半导体芯片120的下部上；导热层130，设置在半导体芯片120的上部上；密封层150，围绕半导体芯片120的侧表面和导热层130的侧表面；以及第二再分布部160，设置在密封层150上并连接到导热层130。半导体封装件100还可以包括：核心层140，具有贯穿孔CA以使半导体芯片120安装在贯穿孔CA中；第一钝化层170，设置在第二再分布部160的上部上；第二钝化层180，设置在第一再分布部110的下部上；垫(pad，也可以称为焊盘)金属层190；以及连接端子195。半导体封装件100可以是其中半导体芯片120的连接垫122在外部再分布的扇出型半导体封装件。
核心层140可以包括穿透核心层140的上表面和下表面的贯穿孔CA，以使半导体芯片120安装在贯穿孔CA中。如图1中所示，贯穿孔CA可以形成在核心层140的中心处，但贯穿孔CA的数量和布置不限于附图中示出的那些。例如，可以在核心层140中形成两个或更多个贯穿孔CA，以安装各个半导体芯片120(例如，相同或不同的芯片)。在一些实施例中，贯穿孔CA可以不完全穿透核心层140的下表面，并且可以具有腔形状。例如，核心层140可以具有含有封闭的底部以及敞开的顶部的凹部，并且半导体芯片120可以安装在该凹部中。
核心层140可以包括核心绝缘层141、核心布线层142和核心过孔144。核心布线层142和核心过孔144可以被布置为使核心层140的上表面和下表面(例如，形在上表面和下表面上的导体图案)电连接。核心布线层142可以设置在核心绝缘层141内部，但不局限于此。例如，核心布线层142中的一些可以形成在核心层140的上表面和/或下表面上。例如，核心布线层142中的一些可以从核心层140的上表面和/或下表面暴露。在核心布线层142之中通过核心层140的下表面暴露的核心布线层142可以嵌入在核心绝缘层141中，并且可以根据制造工艺形成具有这样的结构。
核心绝缘层141可以包括绝缘材料，例如，诸如环氧树脂的热固性树脂或诸如聚酰亚胺的热塑性树脂，并且还可以包括无机填充剂。可选地，核心绝缘层141可以包括浸渍有诸如玻璃纤维、玻璃布或玻璃织物等的核心材料和例如预浸料、ABF(Ajinomoto Build-upFilm)、FR-4或BT(双马来酰亚胺三嗪)等的无机填充剂的树脂。
半导体芯片120可以安装在核心层140的贯穿孔CA中，并且可以被设置为与贯穿孔CA的内壁分开。例如，半导体芯片120可以被设置为与核心层140的贯穿孔CA的全部内壁分开。半导体芯片120可以包括逻辑半导体芯片和/或存储器半导体芯片。逻辑半导体芯片可以是微处理器，例如，中央处理单元(CPU)、控制器或专用集成电路(ASIC)等。存储器半导体芯片可以是易失性存储器(诸如动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM)等)或者非易失性存储器(诸如闪存等)。
半导体芯片120可以包括连接垫122和设置在半导体芯片120的下表面上的覆盖层123。例如，覆盖层123可以是覆盖各个连接垫122的部分和半导体芯片120的下表面的绝缘层。在本示例实施例中，半导体芯片120的下表面可以是有效表面(active surface，也可以称为有源表面)，并且连接垫122可以设置在该有效表面上。与半导体芯片120的下表面相对的上表面可以是无效表面，而有效表面的布置位置可以根据示例实施例而变化。连接垫122可以被设置为使半导体芯片120电连接到其它组件。例如，再分布层或凸块等可以设置在半导体芯片120的下表面上，并且可以连接到连接垫122。例如，再分布层可以是形成第一再分布部110(例如，下布线层112)的层或形成下过孔114的层。连接垫122可以由导电材料(例如，铝(Al))制成。覆盖层123可以被设置为使位于半导体芯片120的下表面上的连接垫122暴露。覆盖层123可以包括氧化硅膜和/或氮化硅膜。例如，覆盖层123可以使连接垫122中的每一个部分地暴露。
第一再分布部110可以将连接垫122从半导体芯片120的下部再分布到半导体芯片120的外围区域。例如，第一再分布部110可以使连接垫122电连接到形成在第一再分布部110的相对侧上的导体图案，从而传输电信号。第一再分布部110可以包括多个下绝缘层111、多个下布线层112和多个下过孔114。构成第一再分布部110的下绝缘层111、下布线层112和下过孔114的数量和布置不限于附图中示出的那些，并且可以根据示例实施例而变化。
下绝缘层111可以由绝缘材料(例如，感光介电(PID)树脂)制成。在这种情况下，下绝缘层111还可以包括无机填充剂。不同的下绝缘层111可以由彼此相同的材料或彼此不同的材料制成。下布线层112和下过孔114可以用于使连接垫122再分布。例如，通过利用下布线层112和下过孔114使连接垫122与连接端子195电连接，可以利用连接端子195来使连接垫122的布置再分布。下过孔114可以具有利用导电材料完全填充各个孔的结构，但不限于此，例如，下过孔114可以具有沿各个孔的壁形成的导电材料的形状，或者可以具有诸如圆柱形形状或锥形形状等的各种形状。下布线层112和下过孔114可以包括诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、铅(Pb)、钛(Ti)或它们的合金的导电材料。
导热层130可以设置在半导体芯片120的上表面上。导热层130可以与半导体芯片120的上表面接触(即，触摸半导体芯片120的上表面)，或者可以经由粘合层等堆叠。导热层130的下表面可以接触(即，触摸)半导体芯片120，或者可以被设置为靠近于半导体芯片120且薄粘合层置于半导体芯片120与导热层130之间，导热层130的上表面可以与第一上过孔164a和密封层150接触。导热层130可以设置在核心层140的贯穿孔CA中。从第一再分布部110的上表面距导热层130的上表面的第二高度D2可以等于或近似于从第一再分布部110的上表面距核心层140的上表面的第一高度D1。例如，即使在第二高度D2大于第一高度D1时，第二高度D2也可以等于或低于从第一再分布部110的上表面距第二上布线层162b的上表面的高度。
导热层130可以由具有比半导体芯片120的热导率高的热导率的材料制成，从而向上散发由半导体芯片120产生的热量。例如，半导体芯片120的热导率可以在大约100W/mK至130W/mK的范围内，并且导热层130的热导率可以在大约360W/mK至410W/mK的范围内，但不局限于此。导热层130可以由例如诸如铜(Cu)的金属制成。在示例实施例中，导热层130可以由与第二再分布部160的上布线层162a和162b的材料相同的材料制成。
如图3中所示，导热层130可以在平面图中具有与半导体芯片120的尺寸相同的尺寸，并且导热层130的侧表面可以与半导体芯片120的侧表面共面。在某些实施例中，导热层130的四个侧表面可以与半导体芯片120的相应的侧表面共面。导热层130的厚度T2可以小于半导体芯片120的厚度T1，并且例如可以在半导体芯片120的厚度T1的10％至40％的范围内，但不限于此。当导热层130的厚度T2相对大时，导热层130会不设置在贯穿孔CA中，从而会增加半导体封装件100的厚度。当导热层130的厚度T2相对小时，会降低导热层130的散热功能。
密封层150可以占据核心层140的贯穿孔CA中的空间以密封贯穿孔CA，并且可以延伸到核心层140的上表面和导热层130的上表面。密封层150可以占据半导体芯片120与贯穿孔CA的内壁之间的空间以及半导体芯片120的覆盖层123与第一再分布部110之间的空间的至少一部分。例如，密封层150可以填充贯穿孔CA的侧壁与半导体芯片120和/或贯穿孔CA的侧壁与导热层130之间的间隙。因此，密封层150也可以用作例如上面提及的层之间的粘合层。密封层150可以由绝缘材料(例如，环氧树脂或聚酰亚胺等)制成。
第二再分布部160(也被描述为再分布图案)可以设置在半导体芯片120的上部上(例如，在半导体芯片120上/上方)，并且通过核心层140的核心布线层142和第一再分布部110电连接到半导体芯片120。因此，第二再分布部160也可以用于再分布连接垫122。例如，第二再分布部160可以电连接到连接垫122。第二再分布部160可以包括第一上布线层162a和第二上布线层162b以及第一上过孔164a和第二上过孔164b。第一上布线层162a和第二上布线层162b可以设置在相同高度水平处，例如所述高度水平相对于包括半导体芯片120的其上形成有连接垫122的下表面的第一平面。例如，所述高度水平可以是第一上布线层162a和第二上布线层162b距第一平面的垂直距离。第一上布线层162a和第一上过孔164a可以设置在半导体芯片120的上部上(例如，在半导体芯片120上/上方)，并且可以连接到导热层130。第二上布线层162b和第二上过孔164b可以设置在核心层140的上部上以电连接到半导体芯片120。例如，第二上布线层162b和第二上过孔164b可以形在核心绝缘层141和/或核心布线层142上/上方。
如图3中所示，第一上布线层162a可以具有与半导体芯片120和导热层130的尺寸和形状相同的尺寸和形状，例如，正方形形状，但不限于此。在示例实施例中，第一上布线层162a的在至少一个方向上的长度L1可以等于或大于导热层130的在所述一个方向上的长度L2。例如，第一上布线层162a可以具有比导热层130的尺寸大的尺寸。在某些实施例中，第一上布线层162a可以由布置在相同高度处的多个线图案形成，例如，所述高度相对于第一平面。
第一上布线层162a可以通过第一上过孔164a连接到导热层130。第一上过孔164a可以通过穿透密封层150而连接到导热层130。在一些示例实施例中，第二再分布部160可以包括设置在密封层150的上部上(例如，在密封层150的位于第一上布线层162a与密封层150之间的顶部上)的绝缘层，在这种情况下，第一上过孔164a可以被设置为例如在竖直方向上穿透该绝缘层和密封层150。如图1和图3中所示，第一上过孔164a可以以行和列布置。如图1中所示，第一上过孔164a可以被布置为具有比第二上过孔164b的间距小的间距，但不局限于此。因此，第一上布线层162a可以设置在导热层130的上部上，并且通过第一上过孔164a连接到导热层130，从而可以通过将执行散热功能的区域从导热层130扩展到第一上布线层162a来进一步改善半导体封装件100的散热功能。
如图2中所示，第一上布线层162a可以在至少一个区域中物理地连接到第二上布线层162b。因此，第一上布线层162a和第一上过孔164a可以电连接到第二上布线层162b和第二上过孔164b。在这种情况下，例如，可以向第一上布线层162a施加电信号(诸如接地电压)。在这种情况下，由于导热层130与半导体芯片120的无效表面接触，所以电信号可以不传输到半导体芯片120(例如，半导体芯片120的布线)。可选地，电压可以由于半导体芯片120与导热层130之间的粘合层而不传输到半导体芯片120。
第二再分布部160可以包括诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、钛(Ti)或它们的合金的导电材料。第一上过孔164a和第二上过孔164b可以具有利用导电材料完全填充各个孔的结构，但不限于此，例如，第一上过孔164a和第二上过孔164b可以具有其中沿各个孔的壁形成导电材料的形状，并且可以具有诸如圆柱形形状或锥形形状等的各种形状。
第一钝化层170和第二钝化层180可以分别设置在第二再分布部160的上表面和第一再分布部110的下表面上，并且可以分别用于保护第二再分布部160和第一再分布部110。第一钝化层170和第二钝化层180可以由例如树脂的绝缘材料形成，但不局限于此。
垫金属层190可以被设置为连接到(例如，接触)通过第二钝化层180的开口暴露的下布线层112，以使第一再分布部110和连接端子195电连接。垫金属层190可以由例如金属的导电材料制成。
连接端子195可以将半导体封装件100连接到电子装置的其上安装有半导体封装件100的主板等。连接端子195可以包括导电材料中的至少一种，例如，焊料、锡(Sn)、银(Ag)、铜(Cu)和/或铝(Al)。连接端子195的形状可以是球形状或诸如平台(land)、凸块、柱或销等的其它形状。
图4至图6是根据示例实施例的半导体封装件的示意性剖视图。
参照图4，在半导体封装件100a中，第二再分布部160a中的第一上布线层162a和第二上布线层162b可以以与图1至图3的示例实施例的方式不同的方式彼此物理地和电气地分离/绝缘。第二再分布部160a(也被描述为再分布图案)可以包括均可以被描述为再分布图案的再分布部(例如，162b和164b)和虚设再分布部(例如，162a和164a)。例如，第一上布线层162a和第一上过孔164a可以分别是虚设布线层和虚设过孔。例如，再分布部(例如，162b和164b)可以传输电信号并且可以具有使电信号线的布置再分布的效果。例如，虚设再分布部(例如，162a和164a)可以不传输电信号。
如这里所使用的，术语“虚设”用于指具有与其它组件的结构和形状相同或相似的结构和形状但在装置中仅以图案存在而没有实质功能的构造。第一上布线层162a和第一上过孔164a不电连接到半导体封装件100a中的半导体芯片120和包括第二上布线层162b的布线结构，但可以作为图案存在而不接收电信号(例如，当半导体芯片120工作时)。第二再分布部160a的第一上布线层162a和第一上过孔164a与导热层130一起可以用于在外部散发由半导体芯片120产生的热量，并且用于防止半导体封装件100的翘曲。在某些实施例中，可以向第一上布线层162a和第一上过孔164a施加接地信号。
参照图5，半导体封装件100b还可以以与图1至图3的示例实施例的方式不同的方式包括设置在半导体芯片120与导热层130之间的阻挡层125。
阻挡层125可以是插置在导热层130与半导体芯片120之间的扩散阻挡层，使得导热层130的材料不扩散到半导体芯片120中，或者可以是用于在导热层130与半导体芯片120之间的界面处保护半导体芯片120的保护层。阻挡层125的材料可以根据导热层130的材料来选择，并且可以由导热材料制成。阻挡层125可以包括例如钛(Ti)、钽(Ta)、镍(Ni)、钨(W)和/或它们的合金中的一种或多种合金。阻挡层125可以包括单层或多层。
参照图6，在半导体封装件100c中，形成核心层140a的核心绝缘层141a和141b以及核心布线层142的数量可以与图1至图3的示例实施例的核心绝缘层以及核心布线层的数量不同，并且核心过孔144a和144b的数量和形状等可以以不同于图1至图3的示例实施例的方式呈现。
核心层140a可以通过形成穿过第一核心绝缘层141a的上表面和下表面的第一核心过孔144a，通过形成设置在该上表面和该下表面上的核心布线层142，然后通过形成位于第一核心绝缘层141a的上表面和下表面上以覆盖第一核心绝缘层141a的相应的上表面和下表面的第二核心绝缘层141b而形成。接下来，核心布线层142可以分别形成在第二核心绝缘层141b的上表面和下表面上。例如，核心布线层142的一部分可以形成在形成于第一核心绝缘层141a的上表面上的第二核心绝缘层141b的上表面上，并且核心布线层142的另一部分可以形成在形成于第一核心绝缘层141a的下表面上的第二核心绝缘层141b的下表面上。第二核心绝缘层141b可以使第一核心过孔144a的一部分暴露。在某些实施例中，如图6中所示，一些第一核心过孔144a可以被第二核心绝缘层141b完全覆盖。第二核心过孔144b可以被形成为穿过第二核心绝缘层141b。例如，核心层140a可以具有以核心形式制造的结构。例如，第一核心绝缘层141a可以封闭在第二核心绝缘层141b内。
因此，核心层140a可以具有其中核心布线层142设置在核心层140a的顶部和底部处而不使核心布线层142嵌入在第一核心绝缘层141a中的结构。在示例实施例中，可以不同地改变核心绝缘层141a和141b以及在第一核心绝缘层141a周围上下堆叠的核心布线层142的数量。例如，可以在第一核心绝缘层141a的每一侧面上堆叠两个或更多个第二核心绝缘层141b以及两个或更多个核心布线层142。
图7和图8是根据示例实施例的半导体封装件的示意性剖视图。
参照图7，半导体封装件100d可以以不同于图1至图3的示例实施例的方式包括多个半导体芯片120a和120b以及多个导热层130。
半导体芯片120a和120b可以平行地布置在核心层140的贯穿孔CA中。例如，在平面图中，导热层130可以以与半导体芯片120a和120b的尺寸基本相同的尺寸布置在相应的半导体芯片120a和120b的上表面上。例如，导热层130可以在平面图中具有与相应的半导体芯片120a和120b的面积相同的面积。
第一上布线层162a和第一上过孔164a可以布置在导热层130的相应的上部上，并且连接到导热层130。例如，第一上过孔164a可以分别与对应的导热层130接触。在至少一个区域中，第一上布线层162a可以电连接到与半导体芯片120a和120b电连接的第二上布线层162b。图7示出了第一上布线层162a在半导体芯片120a和120b之间彼此不连接，但不局限于此。根据示例实施例，第一上布线层162a可以被布置为在半导体芯片120a和120b之间彼此连接。例如，半导体芯片120a和120b可以例如通过第一上布线层162a彼此电连接。
参照图8，半导体封装件100e可以以不同于图7的示例实施例的方式/形式包括多个半导体芯片120a和120b以及导热层130a。
例如，在平面图中，导热层130a可以在半导体芯片120a和120b的上表面上设置为单个层，从而在半导体芯片120a和120b之间延伸。导热层130a可以由例如铜箔制成，但不局限于此。因此，例如，在平面图中，导热层130a可以延伸并设置在半导体芯片120a和120b之间，从而可以进一步改善散热功能。例如，导热层130a可以在半导体芯片120a和120b之上延伸并可以与半导体芯片120a和120b的上表面接触。例如，导热层130a可以在平面图中完全覆盖半导体芯片120a和120b。
第一上布线层162a和第一上过孔164a可以布置在导热层130a上，并且可以布置在半导体芯片120a和120b之间的区域上。例如，形成在半导体芯片120a之上的第一上布线层162a可以在半导体芯片120b之上延伸，从而形成第一上布线层162a的连续图案。
图9是根据示例实施例的半导体封装件的示意性剖视图。
参照图9，不同于图1至图3的示例实施例，半导体封装件100f可以不包括核心层140和密封层150。半导体封装件100f可以包括用于封装半导体芯片120和导热层130的封装层155。
封装层155可以被设置为覆盖第一再分布部110的上表面，并且围绕半导体芯片120和导热层130的侧表面。例如，封装层155可以设置在第一再分布部110与第二再分布部160之间。封装层155的上表面可以与导热层130的上表面共面，但不局限于此。封装层155可以由例如硅树脂类材料、热固性材料、热塑性材料或UV处理材料等制成。封装层155可以由树脂材料制成，并且可以由例如环氧树脂模塑料(EMC)形成。
设置在封装层155的下部上的第一再分布部110和设置在封装层155的上部上的第二再分布部160通过穿透封装层155的通孔145和设置在封装层155的下部上的布线层142而彼此电连接。在示例实施例中，可以省略布线层142，并且通孔145可以使第一再分布部110的下布线层112和第二再分布部160的第二上布线层162b直接连接。因此，半导体封装件100f可以是不包括核心层140的扇出型晶圆级半导体封装件。
图10是用于解释根据示例实施例的半导体封装件的散热特性的曲线图。
参照图10，该曲线表示依据根据对比示例的半导体芯片的厚度的热阻的测量结果以及当前公开的示例实施例的半导体芯片结构的热阻的测量结果。对比示例具有仅由硅基半导体芯片制成的结构，而示例实施例具有其中在硅基半导体芯片上形成有铜的导热层的结构。在示例实施例中，半导体芯片的厚度为160μm，导热层的厚度为40μm。
如图10中所示，在对比示例中，随着半导体芯片的厚度增加，热阻倾向于降低。在发明示例的情况下，示出了尽管半导体芯片结构的总厚度是200μm，但是热阻值在曲线图的曲线中与其中对比示例的半导体芯片的厚度是大约260μm的情况对应。根据这样的结果，可以看出，即使发明示例的半导体芯片结构的总厚度从厚度为160μm的半导体芯片增加40μm，其热阻仍与其中对比示例的半导体芯片的厚度增加100μm的情况相同，其中后一种情况的厚度增加是前一种情况的厚度增加的2.5倍。例如，示例实施例具有通过使用导热层来减小半导体封装件的总厚度的效果。
这种耐热特性可能是由于半导体芯片120和导热层130的热导率的性能，如下：由于硅基半导体芯片的热导率为大约117W/mK，而由铜制成的导热层的热导率为大约385W/mK，这是半导体芯片的热导率的三倍或更多倍。在另一方面，从半导体芯片的中心部分散发的热量可以在半导体芯片的上部处沿导热层在水平方向上有效地消散，从而可以进一步提高散热效率。例如，导热层130可以通过其高热导率的优点而将局部产生的热量有效地扩散到导热层130的整个区域，从而使热量朝向半导体封装件的外部有效地消散。
图11A至图11H是示出根据示例实施例的制造半导体封装件的方法的各步骤的示意图。
参照图11A，可以制备核心层140。
可以通过在载体基底等上形成多个绝缘层(形成核心绝缘层141)，通过顺序地形成穿透绝缘层的核心过孔144以及位于绝缘层上的核心布线层142，并从中移除载体基底来制造核心层140。在某些实施例中，可以通过重复上述步骤以形成多层布线层142、多层过孔144和/或多层核心绝缘层141来形成核心层140。在示例实施例中，根据半导体封装件的功能或核心层140的制造工艺等，可以将核心层140的结构改变为包括图6的示例实施例的各种结构。
参照图11B，可以在核心层140中形成穿透核心层140的上表面和下表面的贯穿孔CA。
可以在核心层140的中心处形成贯穿孔CA。例如，贯穿孔CA可以在平面图中被核心层140围绕。贯穿孔CA的尺寸和形状可以根据要安装的半导体芯片120的尺寸、形状或数量等而改变。例如，贯穿孔CA的平面面积可以小于半导体芯片120的平面面积(或者在多个半导体芯片设置在贯穿孔CA上的情况下，半导体芯片的所有平面面积的总和)的120％。可以通过对核心层140进行机械钻孔和/或激光钻孔来形成贯穿孔CA。可选地，可以通过使用磨粒的喷砂方法或使用等离子体的干蚀刻方法等来形成贯穿孔CA。
参照图11C，可以将粘合层210附着到核心层140的下表面，并且可以在贯穿孔CA中(例如，在粘合层210上)设置半导体芯片120。可以在半导体芯片120的下表面与粘合层210之间设置覆盖层123。
可以设置粘合层210以固定核心层140，并且可以使用例如热固性或紫外线可固化的胶带。半导体芯片120可以在贯穿孔CA中附着到粘合层210。可以以面朝下的形式设置半导体芯片120，使得连接垫122附着到粘合层210。
参照图11D，可以形成密封层150，并且可以在密封层150的上部上形成第一支撑层220。
可以形成密封层150以使核心层140和半导体芯片120的上表面和侧表面密封，并且填充贯穿孔CA中的空间。可以通过使用层压方法或涂覆方法等将形成密封层150的材料放置在半导体芯片120上，然后固化该材料来形成密封层150。涂覆方法可以是例如丝网印刷方法或喷印方法。
可以在密封层150上形成第一支撑层220，并且可以将第一支撑层220形成为在后续工艺期间支撑包括半导体芯片120、核心层140和密封层150的结构。第一支撑层220可以包括可以在后续工艺中容易地移除的各种材料。例如，第一支撑层220可以包括诸如环氧树脂的热固性树脂或者诸如聚酰亚胺的热塑性树脂，但不局限于此。
参照图11E，可以从半导体芯片120的下部去除粘合层210以形成第一再分布部110和第二钝化层180。例如，在从半导体芯片120的下部去除粘合层210之后，可以在半导体芯片120的下部上顺序地形成第一再分布部110和第二钝化层180。
可以通过顺序地形成下绝缘层111、下过孔114和下布线层112来形成第一再分布部110。在形成下绝缘层111之后，在半导体芯片120的下表面上和核心层140的下表面上，可以形成下布线层112和下过孔114以制备第一再分布部110。例如，如图11E中所示，第一再分布部110可以包括交替堆叠的多层下布线层112、多层下过孔114和多层下绝缘层111。
第二钝化层180可以被形成为覆盖第一再分布部110的下表面。可以使用层压方法或涂覆方法等通过放置形成第二钝化层180的材料，然后固化该材料来形成第二钝化层180。可选地，也可以通过气相沉积方法来形成第二钝化层180。
参照图11F，可以从半导体芯片120的上部去除第一支撑层220，并在半导体芯片120上形成导热层130。
首先，可以在第二钝化层180的下部上形成第二支撑层230，以支撑上部结构。在某些示例实施例中，可以省略第二支撑层230。接下来，可以去除第一支撑层220的位于半导体芯片120上的部分，并且可以在密封层150上形成由第一支撑层220形成的图案化的掩模层240。例如，图案化的掩模层240可以使密封层150的与半导体芯片120叠置的部分暴露。在某些实施例中，图案化的掩模层240的边缘线可以在平面图中与半导体芯片120的边缘线相同。
可以使用掩模层240去除形成在半导体芯片120的上表面上的密封层150，以形成导热层130。可以通过蚀刻工艺去除位于半导体芯片120上的密封层150，并且可以通过气相沉积方法或电镀方法在如此暴露的半导体芯片120的上表面上形成导热层130。例如，密封层150的在所移除部分处的边缘线在平面图中可以与半导体芯片120的边缘线相同，从而导热层130的边缘线在平面图中与半导体芯片120的边缘线相同。在根据图5的示例实施例的半导体封装件100b的情况下，可以在该步骤中在形成导热层130之前形成阻挡层125。根据形成导热层130的方法，也会在掩模层240上形成形成导热层130的材料，并且可以在去除掩模层240的同时去除该材料。
虽然在本示例实施例中已经作为示例描述了在形成第二再分布部160之前形成导热层130的方法，但导热层130的形成顺序不局限于此。例如，可以通过层压铜箔来形成导热层130，并且在这种情况下，通过在参照图11C的上述工艺期间预先将导热层130附着到半导体芯片120，可以在核心层140的贯穿孔CA中设置半导体芯片120和导热层130在之后形成密封层150。
参照图11G，还可以在半导体芯片120上形成密封层150的第二部分150b，以与核心层140上的第一部分150a一起形成密封层150，并且可以在密封层150中形成导通孔VH。由于密封层150的第一部分150a和第二部分150b通过彼此不同的步骤形成，所以在某些实施例中，第一部分150a和第二部分150b可以被描述为不同的层，例如，第一密封层和第二密封层。
在本示例实施例的情况下，当在安装半导体芯片120之后并且在从半导体芯片120的上部去除密封层150之后形成导热层130时，在形成导热层130之后形成密封层150的第二部分150b。虽然在一些示例实施例中，第一部分150a和第二部分150b可以由相同的材料形成，但在某些实施例中，密封层150的两个部分150a和150b可以由不同的材料制成。例如，如上所述，在其中形成密封层150之前将导热层130附着到半导体芯片120并且一起设置在贯穿孔CA中的示例实施例中，密封层150可以形成为单层，例如，在整个单层中包括同一种材料。
可以使用光刻或者通过使用机械钻孔或激光钻孔通过使密封层150图案化来形成导通孔VH。可以形成导通孔VH以使在随后形成有第一上过孔164a和第二上过孔164b的位置中的导热层130和核心布线层142暴露。
参照图11H，可以形成第一上过孔164a和第二上过孔164b以及第一上布线层162a和第二上布线层162b以形成第二再分布部160。
可以形成第一上过孔164a和第二上过孔164b以填充导通孔VH，并且可以通过电镀工艺来形成第一上过孔164a和第二上过孔164b。可以通过电镀工艺与第一上过孔164a和第二上过孔164b一起形成第一上布线层162a和第二上布线层162b，但不局限于此。例如，可以通过层压铜箔，然后使铜箔图案化来形成第一上布线层162a和第二上布线层162b。
在本示例实施例中，示例了在形成导热层130之后形成第二再分布部160的方法。根据示例实施例，可以利用形成第二再分布部160的工艺的一部分来执行关于导热层130的工艺。在本示例实施例中，可以首先形成第一再分布部110，然后可以形成第二再分布部160。第一再分布部110和第二再分布部160的形成顺序不限于上面提及的顺序。在某些示例实施例中，在参照图11D形成上面描述的密封层150之后，可以执行上面参照图11G至图11H描述的形成导热层130和第二再分布部160的工艺。然后，可以执行上面参照图11E描述的形成第一再分布部110的工艺。
接下来，一起参照图2，可以在第二再分布部160上形成具有开口的第一钝化层170。然后，可以在第二钝化层180的下部上形成用于使下布线层112的一部分暴露的开口，可以在该开口上形成垫金属层190和连接端子195。
可以通过气相沉积或电镀工艺来形成垫金属层190和连接端子195，并且可以通过进一步使用回流工艺来形成连接端子195。
可以对晶圆级或面板级执行上面的工艺，然后可以通过锯切工艺使每个半导体封装件分离来制造图2的半导体封装件100。
图12是根据示例实施例的半导体封装件的示意性剖视图。
参照图12，半导体封装件1000还可以包括以与图2的示例实施例的方式不同的方式设置在第一半导体封装件100上的第二半导体封装件300。例如，半导体封装件1000可以是第二半导体封装件300堆叠在第一半导体封装件100上的层叠封装(POP)型。
第一半导体封装件100可以具有与上面参照图2描述的半导体封装件100的结构相同的结构，但不局限于此。在示例实施例中，第一半导体封装件100可以采用上面参照图4至图9描述的半导体封装件100a、100b、100c、100d、100e和100f中的任何一个。
第二半导体封装件300可以包括基底310、上半导体芯片320、连接部330、上封装部340和上连接端子380。
基底310可以包括主体部311、通过主体部311的上表面暴露的上垫312以及通过主体部311的下表面暴露的下垫314。基底310可以包括例如硅(Si)、玻璃、陶瓷或塑料。基底310可以是单层，或者可以具有包括位于其中的布线图案的多层结构。
上半导体芯片320可以包括逻辑半导体芯片和/或存储器半导体芯片。上半导体芯片320的上表面可以是有效表面，但在示例实施例中有效表面的布置位置可以变化。
连接部330可以使上半导体芯片320电连接到基底310的上垫312。连接部330可以包括布线，但不局限于此，并且可以包括各种类型的信号传输介质。粘合层325可以用于使上半导体芯片320附着到基底310。
上封装部340可以被设置为封装上半导体芯片320，并且可以用于保护上半导体芯片320。上封装部340可以由例如硅树脂类材料、热固性材料、热塑性材料、或UV处理材料等制成。
上连接端子380可以设置在基底310的下表面上。上连接端子380可以使第二半导体封装件300连接到设置在第二半导体封装件300下的第一半导体封装件100，使得第一半导体封装件100和第二半导体封装件300彼此电连接。上连接端子380可以包括至少一种导电材料，诸如焊料、锡(Sn)、银(Ag)、铜(Cu)或铝(Al)。
上面描述的第二半导体封装件300的结构可以是示例性的，并且具有各种结构的半导体封装件可以堆叠在第一半导体封装件100上。在某些示例实施例中，还可以在第一半导体封装件100与第二半导体封装件300之间设置插入基底。
通过包括导热层以及与其连接的上布线层，可以改善半导体封装件的可靠性。
本发明不限于上述实施例和附图，而是仅由权利要求限制。因此，其意图在于，在不脱离如由权利要求限定的本发明的范围的情况下，可以进行替换、修改和变化。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，具有作为有效表面的第一表面和与所述第一表面相对的第二表面；
第一再分布部，设置在所述第一表面上，所述第一再分布部包括电连接到所述第一半导体芯片的下布线层；
导热层，设置在所述第一半导体芯片的所述第二表面上；
密封层，围绕所述第一半导体芯片的侧表面和所述导热层的侧表面；以及
第二再分布部，设置在密封层上，所述第二再分布部包括连接到所述导热层的第一上布线层，所述第二再分布部包括电连接到所述第一半导体芯片的第二上布线层。
2.根据权利要求1所述的半导体封装件，其中，所述导热层的所述侧表面与所述第一半导体芯片的所述侧表面共面。
3.根据权利要求1所述的半导体封装件，其中，所述第二再分布部还包括设置在所述第一上布线层与所述导热层之间的上过孔，所述上过孔使所述第一上布线层和所述导热层连接。
4.根据权利要求3所述的半导体封装件，其中，所述导热层的上表面与所述上过孔和所述密封层接触。
5.根据权利要求1所述的半导体封装件，其中，所述导热层的厚度小于所述第一半导体芯片的厚度。
6.根据权利要求1所述的半导体封装件，所述半导体封装件还包括包含所述第一上布线层的一部分的虚设再分布部，所述部分是未施加电信号的虚设布线层。
7.根据权利要求1所述的半导体封装件，其中，接地信号被施加到所述第一上布线层。
8.根据权利要求1所述的半导体封装件，其中，所述第一上布线层电连接到所述第二上布线层。
9.根据权利要求1所述的半导体封装件，其中，相对于包括所述第一半导体芯片的所述第一表面的平面，所述第一上布线层和所述第二上布线层设置在相同高度水平处。
10.根据权利要求1所述的半导体封装件，所述半导体封装件还包括设置在所述第一半导体芯片与所述导热层之间的阻挡层，所述阻挡层包括金属。
11.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：具有贯穿孔的核心层，所述第一半导体芯片安装在所述贯穿孔内，
其中，所述密封层填充在所述第一半导体芯片与所述贯穿孔的侧壁之间。
12.根据权利要求11所述的半导体封装件，其中，所述导热层设置在所述贯穿孔中。
13.根据权利要求11所述的半导体封装件，其中，所述核心层包括穿透所述核心层的至少一部分的核心过孔并使所述第一再分布部和所述第二再分布部电连接。
14.根据权利要求13所述的半导体封装件，其中，所述核心层还包括电连接到所述核心过孔的核心布线层。
15.根据权利要求1所述的半导体封装件，所述半导体封装件还包括在平面图中与所述第一半导体芯片平行设置的第二半导体芯片，所述导热层在所述第一半导体芯片和所述第二半导体芯片上设置为单个层。
16.一种半导体封装件，所述半导体封装件包括：
核心层，具有贯穿孔；
半导体芯片，具有作为有效表面的第一表面和与所述第一表面相对的第二表面，所述半导体芯片安装在所述核心层的所述贯穿孔中；
第一再分布部，设置在所述第一表面上，所述第一再分布部包括电连接到所述半导体芯片的下布线层；
导热层，设置在所述半导体芯片的所述第二表面上；
密封层，围绕所述半导体芯片的侧表面和所述导热层的侧表面；以及
第二再分布部，设置在所述密封层上，所述第二再分布部包括连接到所述导热层的第一上布线层以及通过所述核心层电连接到所述第一再分布部的第二上布线层。
17.根据权利要求16所述的半导体封装件，其中，所述密封层覆盖所述导热层的上表面的一部分、所述半导体芯片的所述侧表面和所述导热层的所述侧表面。
18.根据权利要求16所述的半导体封装件，其中，所述核心层包括核心布线层和电连接到所述第二上布线层的核心过孔中的至少一者。
19.一种半导体封装件，所述半导体封装件包括：
半导体芯片；
第一再分布部，设置在所述半导体芯片的下表面上，所述第一再分布部包括电连接到所述半导体芯片的下布线层；
导热层，设置在所述半导体芯片的上表面上，所述导热层在平面图中具有与所述半导体芯片的面积相同的面积；以及
第二再分布部，设置在所述导热层上，所述第二再分布部包括连接到所述导热层的上布线层。
20.根据权利要求19所述的半导体封装件，其中，所述第二再分布部还包括使所述上布线层和所述导热层在竖直方向上连接的上过孔。
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