KR102546223B1 - 다수의 다이들을 포함하는 pop(package-on-package) 구조 - Google Patents

다수의 다이들을 포함하는 pop(package-on-package) 구조 Download PDF

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Publication number
KR102546223B1
KR102546223B1 KR1020187002486A KR20187002486A KR102546223B1 KR 102546223 B1 KR102546223 B1 KR 102546223B1 KR 1020187002486 A KR1020187002486 A KR 1020187002486A KR 20187002486 A KR20187002486 A KR 20187002486A KR 102546223 B1 KR102546223 B1 KR 102546223B1
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die
conductive path
layer
pid
pop structure
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Korean (ko)
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KR20180035806A (ko
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홍복 위
재식 이
동욱 김
시쿤 구
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퀄컴 인코포레이티드
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
  • Packages (AREA)
  • Medical Preparation Storing Or Oral Administration Devices (AREA)
  • Die Bonding (AREA)
  • Packaging Frangible Articles (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Hybrid Cells (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Optical Measuring Cells (AREA)
  • Measurement Of Radiation (AREA)
KR1020187002486A 2015-07-29 2016-07-28 다수의 다이들을 포함하는 pop(package-on-package) 구조 Active KR102546223B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/812,476 2015-07-29
US14/812,476 US9401350B1 (en) 2015-07-29 2015-07-29 Package-on-package (POP) structure including multiple dies
PCT/US2016/044487 WO2017019866A1 (en) 2015-07-29 2016-07-28 Package-on-package (pop) structure including multiple dies

Publications (2)

Publication Number Publication Date
KR20180035806A KR20180035806A (ko) 2018-04-06
KR102546223B1 true KR102546223B1 (ko) 2023-06-20

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Country Link
US (1) US9401350B1 (enExample)
EP (2) EP3329512A1 (enExample)
JP (1) JP6914245B2 (enExample)
KR (1) KR102546223B1 (enExample)
CN (1) CN107851588B (enExample)
BR (1) BR112018001783B8 (enExample)
CA (1) CA2990470A1 (enExample)
WO (1) WO2017019866A1 (enExample)

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WO2017209761A1 (en) * 2016-06-03 2017-12-07 Intel IP Corporation Wireless module with antenna package and cap package
US9837341B1 (en) * 2016-09-15 2017-12-05 Intel Corporation Tin-zinc microbump structures
WO2018182610A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Package architecture utilizing photoimageable dielectric (pid) for reduced bump pitch
EP3602642A4 (en) * 2017-03-31 2020-12-23 3M Innovative Properties Company ELECTRONIC DEVICES INCLUDING SOLID SEMICONDUCTOR CHIPS
ES2936243T3 (es) 2018-07-23 2023-03-15 Borealis Ag Película de polipropileno multicapa
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
WO2020103147A1 (zh) 2018-11-23 2020-05-28 北京比特大陆科技有限公司 芯片散热结构、芯片结构、电路板和超算设备
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
CN113924211B (zh) 2019-06-05 2023-09-22 北欧化工公司 多层聚丙烯膜
KR102764370B1 (ko) 2019-12-26 2025-02-07 삼성전자주식회사 반도체 패키지
CN112867243A (zh) * 2021-01-06 2021-05-28 英韧科技(上海)有限公司 多层电路板
US20240222142A1 (en) * 2022-12-28 2024-07-04 Applied Materials, Inc. Efficient autocatalytic metallization of polymeric surfaces

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US20130234322A1 (en) 2012-03-08 2013-09-12 Stats Chippac, Ltd. Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration
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BR112018001783B1 (pt) 2023-01-31
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US9401350B1 (en) 2016-07-26
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