BR112018001783B8 - Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas - Google Patents

Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas

Info

Publication number
BR112018001783B8
BR112018001783B8 BR112018001783A BR112018001783A BR112018001783B8 BR 112018001783 B8 BR112018001783 B8 BR 112018001783B8 BR 112018001783 A BR112018001783 A BR 112018001783A BR 112018001783 A BR112018001783 A BR 112018001783A BR 112018001783 B8 BR112018001783 B8 BR 112018001783B8
Authority
BR
Brazil
Prior art keywords
matrix
pop
package
structure including
pid
Prior art date
Application number
BR112018001783A
Other languages
English (en)
Portuguese (pt)
Other versions
BR112018001783B1 (pt
BR112018001783A2 (pt
Inventor
Bok We Hong
Sik Lee Jae
Wook Kim Dong
Gu Shiqun
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018001783A2 publication Critical patent/BR112018001783A2/pt
Publication of BR112018001783B1 publication Critical patent/BR112018001783B1/pt
Publication of BR112018001783B8 publication Critical patent/BR112018001783B8/pt

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Die Bonding (AREA)
  • Packaging Frangible Articles (AREA)
  • Packages (AREA)
  • Medical Preparation Storing Or Oral Administration Devices (AREA)
  • Optical Measuring Cells (AREA)
  • Measurement Of Radiation (AREA)
  • Geometry (AREA)
  • Hybrid Cells (AREA)
BR112018001783A 2015-07-29 2016-07-28 Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas BR112018001783B8 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/812,476 US9401350B1 (en) 2015-07-29 2015-07-29 Package-on-package (POP) structure including multiple dies
US14/812,476 2015-07-29
PCT/US2016/044487 WO2017019866A1 (en) 2015-07-29 2016-07-28 Package-on-package (pop) structure including multiple dies

Publications (3)

Publication Number Publication Date
BR112018001783A2 BR112018001783A2 (pt) 2018-09-11
BR112018001783B1 BR112018001783B1 (pt) 2023-01-31
BR112018001783B8 true BR112018001783B8 (pt) 2023-02-14

Family

ID=56411293

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018001783A BR112018001783B8 (pt) 2015-07-29 2016-07-28 Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas

Country Status (8)

Country Link
US (1) US9401350B1 (enExample)
EP (2) EP3329512A1 (enExample)
JP (1) JP6914245B2 (enExample)
KR (1) KR102546223B1 (enExample)
CN (1) CN107851588B (enExample)
BR (1) BR112018001783B8 (enExample)
CA (1) CA2990470A1 (enExample)
WO (1) WO2017019866A1 (enExample)

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US11574874B2 (en) * 2017-03-30 2023-02-07 Intel Corporation Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch
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US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
WO2020103147A1 (zh) 2018-11-23 2020-05-28 北京比特大陆科技有限公司 芯片散热结构、芯片结构、电路板和超算设备
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
US11752743B2 (en) 2019-06-05 2023-09-12 Borealis Ag Multilayer polypropylene film
KR102764370B1 (ko) 2019-12-26 2025-02-07 삼성전자주식회사 반도체 패키지
CN112867243A (zh) * 2021-01-06 2021-05-28 英韧科技(上海)有限公司 多层电路板
US20240222142A1 (en) * 2022-12-28 2024-07-04 Applied Materials, Inc. Efficient autocatalytic metallization of polymeric surfaces

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BR112018001783B1 (pt) 2023-01-31
JP6914245B2 (ja) 2021-08-04
BR112018001783A2 (pt) 2018-09-11
EP3329512A1 (en) 2018-06-06
WO2017019866A1 (en) 2017-02-02
EP4439634A3 (en) 2025-01-15
KR102546223B1 (ko) 2023-06-20
CA2990470A1 (en) 2017-02-02
JP2018523919A (ja) 2018-08-23
KR20180035806A (ko) 2018-04-06
EP4439634A2 (en) 2024-10-02
US9401350B1 (en) 2016-07-26
CN107851588A (zh) 2018-03-27

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