BR112016011552A2 - Redes de partições hierárquicas e paralelas - Google Patents

Redes de partições hierárquicas e paralelas

Info

Publication number
BR112016011552A2
BR112016011552A2 BR112016011552A BR112016011552A BR112016011552A2 BR 112016011552 A2 BR112016011552 A2 BR 112016011552A2 BR 112016011552 A BR112016011552 A BR 112016011552A BR 112016011552 A BR112016011552 A BR 112016011552A BR 112016011552 A2 BR112016011552 A2 BR 112016011552A2
Authority
BR
Brazil
Prior art keywords
parallel partition
hierarchical
networks
unit
unit level
Prior art date
Application number
BR112016011552A
Other languages
English (en)
Inventor
K Mishra Asit
S David Howard
S Dunning David
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112016011552A2 publication Critical patent/BR112016011552A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17362—Indirect interconnection networks hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

REDES DE PARTIÇÕES HIERÁRQUICAS E PARALELAS. A presente invenção refere-se a redes de partições paralelas e hierárquicas que incluem uma pluralidade de redes de pacotes de partições paralelas para interligar os componentes em uma ou mais matrizes de circuito integrado. Em uma modalidade, cada rede de pacotes de partições paralelas é independente das outras redes de pacotes de partições paralelas e possui um comutador de nível de unidade a um nível hierárquico de unidade. Em outro aspecto, cada rede de pacotes de partições paralelas possui um comutador de nível de unidade-a-unidade em um nível hierárquico de unidade-a-unidade. Outros aspectos são aqui descritos.
BR112016011552A 2013-12-20 2014-12-16 Redes de partições hierárquicas e paralelas BR112016011552A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/137,108 US20150178092A1 (en) 2013-12-20 2013-12-20 Hierarchical and parallel partition networks
PCT/US2014/070686 WO2015095243A1 (en) 2013-12-20 2014-12-16 Hierarchical and parallel partition networks

Publications (1)

Publication Number Publication Date
BR112016011552A2 true BR112016011552A2 (pt) 2017-08-08

Family

ID=53400119

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016011552A BR112016011552A2 (pt) 2013-12-20 2014-12-16 Redes de partições hierárquicas e paralelas

Country Status (7)

Country Link
US (1) US20150178092A1 (pt)
EP (1) EP3084629B1 (pt)
JP (1) JP6245360B2 (pt)
KR (1) KR101940636B1 (pt)
CN (1) CN105723356B (pt)
BR (1) BR112016011552A2 (pt)
WO (1) WO2015095243A1 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10108253B2 (en) * 2014-01-30 2018-10-23 Hewlett Packard Enterprise Development Lp Multiple compute nodes
US10447328B2 (en) 2016-06-28 2019-10-15 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for die-to-die communication
GB202100742D0 (en) * 2021-01-20 2021-03-03 Graphcore Ltd Exchange between stacked die

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1184015B (it) * 1985-12-13 1987-10-22 Elsag Sistema multiprocessore a piu livelli gerarchici
US5161156A (en) * 1990-02-02 1992-11-03 International Business Machines Corporation Multiprocessing packet switching connection system having provision for error correction and recovery
US5471580A (en) * 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
JPH07230435A (ja) * 1994-02-18 1995-08-29 Hitachi Ltd 可変構造別系統ネットワークを有する並列計算機
JP3272200B2 (ja) * 1994-07-15 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション カスタマイザブル集積回路デバイス
US5574692A (en) * 1995-06-07 1996-11-12 Lsi Logic Corporation Memory testing apparatus for microelectronic integrated circuit
US20020116595A1 (en) * 1996-01-11 2002-08-22 Morton Steven G. Digital signal processor integrated circuit
US5805839A (en) * 1996-07-02 1998-09-08 Advanced Micro Devices, Inc. Efficient technique for implementing broadcasts on a system of hierarchical buses
US6823511B1 (en) * 2000-01-10 2004-11-23 International Business Machines Corporation Reader-writer lock for multiprocessor systems
JP2004199579A (ja) * 2002-12-20 2004-07-15 Hitachi Ltd マルチプロセッサシステム
US20040236891A1 (en) * 2003-04-28 2004-11-25 International Business Machines Corporation Processor book for building large scalable processor systems
JP2006215816A (ja) * 2005-02-03 2006-08-17 Fujitsu Ltd 情報処理システムおよび情報処理システムの制御方法
US7409609B2 (en) * 2005-03-14 2008-08-05 Infineon Technologies Flash Gmbh & Co. Kg Integrated circuit with a control input that can be disabled
JP4806362B2 (ja) * 2007-02-14 2011-11-02 富士通株式会社 並列処理制御プログラム、並列処理制御システムおよび並列処理制御方法
US8014387B2 (en) * 2007-08-27 2011-09-06 International Business Machines Corporation Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture
US20100100703A1 (en) * 2008-10-17 2010-04-22 Computational Research Laboratories Ltd. System For Parallel Computing
US8244986B2 (en) * 2009-12-30 2012-08-14 Empire Technology Development, Llc Data storage and access in multi-core processor architectures
RU2011117765A (ru) * 2011-05-05 2012-11-10 ЭлЭсАй Корпорейшн (US) Устройство (варианты) и способ реализации двухпроходного планировщика задач линейной сложности
JP5821624B2 (ja) * 2011-12-27 2015-11-24 富士通株式会社 通信制御装置、並列計算機システム及び通信制御方法

Also Published As

Publication number Publication date
KR20160068901A (ko) 2016-06-15
JP6245360B2 (ja) 2017-12-13
EP3084629A1 (en) 2016-10-26
CN105723356A (zh) 2016-06-29
CN105723356B (zh) 2019-05-17
EP3084629A4 (en) 2017-08-09
JP2017503230A (ja) 2017-01-26
EP3084629B1 (en) 2023-01-04
KR101940636B1 (ko) 2019-01-22
WO2015095243A1 (en) 2015-06-25
US20150178092A1 (en) 2015-06-25

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements