JP6466305B2 - 電子パッケージ用の電気インターコネクト - Google Patents
電子パッケージ用の電気インターコネクト Download PDFInfo
- Publication number
- JP6466305B2 JP6466305B2 JP2015208684A JP2015208684A JP6466305B2 JP 6466305 B2 JP6466305 B2 JP 6466305B2 JP 2015208684 A JP2015208684 A JP 2015208684A JP 2015208684 A JP2015208684 A JP 2015208684A JP 6466305 B2 JP6466305 B2 JP 6466305B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- signal conductor
- trench
- electrical interconnect
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004020 conductor Substances 0.000 claims description 163
- 238000000034 method Methods 0.000 claims description 48
- 238000009713 electroplating Methods 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000013461 design Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
Claims (8)
- 片面と反対面とを含む誘電体層であり、前記反対面はトレンチを含む、誘電体層と、
前記誘電体層の前記片面上の第1及び第2の信号導体と、
前記誘電体層の前記反対面上に取り付けられた導電性の基準層であり、当該導電性の基準層は、前記誘電体層の前記反対面と係合し、且つ前記トレンチを充填する突出部を含み、電流が前記第1及び第2の信号導体の各々を通り抜けるときに前記第1及び第2の信号導体の各々が当該導電性の基準層に電磁結合される、導電性の基準層と、
を有し、
前記トレンチを充填する前記導電性の基準層の前記突出部は、前記第1の信号導体及び前記第2の信号導体に沿って延在し、且つ前記第1の信号導体及び前記第2の信号導体から等距離に位置する、
電子パッケージ用の電気インターコネクト。 - 前記誘電体層の前記反対面は複数のトレンチを含み、当該電気インターコネクトは更に、前記誘電体層の前記片面上に複数の更なる信号導体を有し、前記導電性の基準層は、前記複数のトレンチを充填する複数の突出部を含み、前記信号導体は各々、電流が該信号導体を通り抜けるときに前記複数の突出部のうちの少なくとも1つに電磁結合される、請求項1に記載の電気インターコネクト。
- 前記複数の突出部は各々、2つの異なる信号導体から等距離に位置する、請求項2に記載の電気インターコネクト。
- 前記誘電体層は第1の誘電体層であり、当該電気インターコネクトは更に、
前記第1の誘電体層の前記片面に取り付けられた第2の誘電体層であり、それぞれ前記第1及び第2の信号導体を露出させる第1及び第2の開口を含む第2の誘電体層と、
前記第2の誘電体層の前記第1及び第2の開口内でそれぞれ前記第1及び第2の信号導体に電気接続された第1及び第2のはんだバンプと
を有する、請求項1に記載の電気インターコネクト。 - 誘電体層の片面上に第1及び第2の信号導体を形成し、
前記誘電体層の反対面に、第1及び第2の信号導体に沿って延在するトレンチを形成し、且つ
前記誘電体層の前記反対面上に導電性の基準層を形成し、該導電性の基準層は、前記トレンチを充填する突出部を含み、該突出部は、電流が前記第1及び第2の信号導体の各々を通り抜けるときに前記第1及び第2の信号導体の各々に電磁結合されることになる、
ことを有し、
前記トレンチを充填する前記導電性の基準層の前記突出部は、前記第1の信号導体及び前記第2の信号導体から等距離に位置する、
方法。 - 前記誘電体層の前記反対面上及び前記トレンチ内に前記導電性の基準層を形成することは、前記誘電体層の前記反対面上及び前記トレンチ内に前記導電性の基準層を電解めっきすることを含む、請求項5に記載の方法。
- 当該方法は更に、
前記誘電体層の前記片面上に複数の信号導体を形成し、且つ
前記誘電体層の前記反対面に複数のトレンチを形成する
ことを有し、
前記導電性の基準層は、前記複数のトレンチを充填する複数の突出部を含み、該複数の突出部は各々、電流がそれぞれの信号導体を通り抜けるときに対応する信号導体に電磁結合されることになる、
請求項5又は6に記載の方法。 - 前記誘電体層の前記反対面に前記複数のトレンチを形成することは、前記複数の突出部の各々が2つの異なる信号導体から等距離に位置するように、前記誘電体層の前記反対面に前記複数のトレンチを形成することを含む、請求項7に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/555,124 US9552995B2 (en) | 2014-11-26 | 2014-11-26 | Electrical interconnect for an electronic package |
US14/555,124 | 2014-11-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016100600A JP2016100600A (ja) | 2016-05-30 |
JP6466305B2 true JP6466305B2 (ja) | 2019-02-06 |
Family
ID=56010951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015208684A Active JP6466305B2 (ja) | 2014-11-26 | 2015-10-23 | 電子パッケージ用の電気インターコネクト |
Country Status (4)
Country | Link |
---|---|
US (1) | US9552995B2 (ja) |
JP (1) | JP6466305B2 (ja) |
MY (1) | MY175102A (ja) |
TW (1) | TWI614867B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11955436B2 (en) * | 2019-04-24 | 2024-04-09 | Intel Corporation | Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission |
CN110913570A (zh) * | 2019-12-16 | 2020-03-24 | 西安子国微科技有限公司 | 一种高性能信息处理及接口方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH065593A (ja) * | 1992-04-20 | 1994-01-14 | Sumitomo Electric Ind Ltd | 多層配線基板及びその製造方法 |
JP2001053507A (ja) * | 1999-08-13 | 2001-02-23 | Nec Corp | 配線基板とその製造方法 |
CN101232776B (zh) * | 1999-09-02 | 2011-04-20 | 揖斐电株式会社 | 印刷布线板 |
JP2001203300A (ja) * | 2000-01-18 | 2001-07-27 | Matsushita Electric Ind Co Ltd | 配線用基板と半導体装置および配線用基板の製造方法 |
US6541711B1 (en) * | 2000-05-22 | 2003-04-01 | Cisco Technology, Inc. | Isolated ground circuit board apparatus |
US6914334B2 (en) * | 2002-06-12 | 2005-07-05 | Intel Corporation | Circuit board with trace configuration for high-speed digital differential signaling |
JP4511294B2 (ja) * | 2004-09-22 | 2010-07-28 | 京セラ株式会社 | 配線基板 |
US7646097B2 (en) * | 2005-10-11 | 2010-01-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pads and methods for fabricating the same |
JP2007193999A (ja) * | 2006-01-17 | 2007-08-02 | Sony Chemical & Information Device Corp | 伝送ケーブル |
JP2007288180A (ja) * | 2006-03-24 | 2007-11-01 | Kyocera Corp | 配線構造、多層配線基板および電子装置 |
TWI312560B (en) * | 2006-10-20 | 2009-07-21 | Phoenix Prec Technology Corporatio | Package substrate and method thereof |
JP5103088B2 (ja) * | 2007-08-02 | 2012-12-19 | 信越ポリマー株式会社 | 伝導ノイズ抑制構造体および配線回路基板 |
CN102239753B (zh) * | 2008-12-05 | 2013-11-06 | 揖斐电株式会社 | 多层印刷线路板和多层印刷线路板的制造方法 |
US8563336B2 (en) * | 2008-12-23 | 2013-10-22 | International Business Machines Corporation | Method for forming thin film resistor and terminal bond pad simultaneously |
US8343810B2 (en) * | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
JP2012124452A (ja) * | 2010-12-06 | 2012-06-28 | Samsung Electro-Mechanics Co Ltd | プリント基板およびその製造方法 |
JP2012227211A (ja) * | 2011-04-15 | 2012-11-15 | Olympus Corp | 差動信号用配線基板 |
JP2013051367A (ja) * | 2011-08-31 | 2013-03-14 | Fujikura Ltd | 多層配線板の製造方法 |
US8716852B2 (en) * | 2012-02-17 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-electro mechanical systems (MEMS) having outgasing prevention structures and methods of forming the same |
US8987851B2 (en) * | 2012-09-07 | 2015-03-24 | Mediatek Inc. | Radio-frequency device package and method for fabricating the same |
US8962349B1 (en) * | 2013-11-25 | 2015-02-24 | Avalanche Technology, Inc. | Method of manufacturing magnetic tunnel junction memory element |
-
2014
- 2014-11-26 US US14/555,124 patent/US9552995B2/en active Active
-
2015
- 2015-10-16 TW TW104134050A patent/TWI614867B/zh active
- 2015-10-16 MY MYPI2015703725A patent/MY175102A/en unknown
- 2015-10-23 JP JP2015208684A patent/JP6466305B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2016100600A (ja) | 2016-05-30 |
TWI614867B (zh) | 2018-02-11 |
MY175102A (en) | 2020-06-06 |
US20160148866A1 (en) | 2016-05-26 |
US9552995B2 (en) | 2017-01-24 |
TW201631727A (zh) | 2016-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6067802B2 (ja) | 相互接続ルーティング構成及び関連技術 | |
KR101242881B1 (ko) | 입/출력 패키지 아키텍처, 입/출력 패키지 아키텍처 패키지, 방법 및 컴퓨팅 시스템 | |
US9159670B2 (en) | Ultra fine pitch and spacing interconnects for substrate | |
US8772951B1 (en) | Ultra fine pitch and spacing interconnects for substrate | |
US9105635B2 (en) | Stubby pads for channel cross-talk reduction | |
EP2854488A1 (en) | Reducing far end crosstalk in single ended interconnects and buses | |
AU2017321176B2 (en) | Circuits and methods providing mutual capacitance in vertical electrical connections | |
US11482481B2 (en) | Semiconductor device and system | |
KR20210074993A (ko) | 집적 회로 패키지용 복합 브리지 다이 대 다이 상호접속부 | |
JP6466305B2 (ja) | 電子パッケージ用の電気インターコネクト | |
US10354957B2 (en) | Electrical interconnect for a flexible electronic package | |
US11114394B2 (en) | Signal routing carrier | |
CN111863736A (zh) | 用于实现高速低损耗信号传递并减轻制造风险和成本的封装设计方案 | |
US11153968B2 (en) | Device, system and method to promote the integrity of signal communications | |
US10303225B2 (en) | Methods of forming hybrid socket structures for package interconnect applications and structures formed thereby | |
TWI727996B (zh) | 具有暴露在側壁上之導電佈線的中介件 | |
US10840196B1 (en) | Trace modulations in connectors for integrated-circuit packages | |
US20200170113A1 (en) | High density flexible interconnect design for multi-mode signaling | |
Huang et al. | Design and electrical performance analysis on coreless flip chip BGA substrate | |
US10062981B2 (en) | Ground routing device and method | |
US20170318669A1 (en) | Electronic package and method forming an electrical package | |
WO2013006496A2 (en) | Multiple socket concept |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170207 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170912 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20171208 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180207 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20180612 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181009 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20181018 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20181211 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190109 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6466305 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |