JP2017506430A5 - - Google Patents

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Publication number
JP2017506430A5
JP2017506430A5 JP2016549575A JP2016549575A JP2017506430A5 JP 2017506430 A5 JP2017506430 A5 JP 2017506430A5 JP 2016549575 A JP2016549575 A JP 2016549575A JP 2016549575 A JP2016549575 A JP 2016549575A JP 2017506430 A5 JP2017506430 A5 JP 2017506430A5
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JP
Japan
Prior art keywords
contact
active
gate
dummy gate
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016549575A
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English (en)
Japanese (ja)
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JP2017506430A (ja
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Publication date
Priority claimed from US14/274,184 external-priority patent/US9379058B2/en
Application filed filed Critical
Publication of JP2017506430A publication Critical patent/JP2017506430A/ja
Publication of JP2017506430A5 publication Critical patent/JP2017506430A5/ja
Pending legal-status Critical Current

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JP2016549575A 2014-02-14 2015-01-08 スケーリングされたレイアウト設計におけるダミーゲートのアース Pending JP2017506430A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461940011P 2014-02-14 2014-02-14
US61/940,011 2014-02-14
US14/274,184 2014-05-09
US14/274,184 US9379058B2 (en) 2014-02-14 2014-05-09 Grounding dummy gate in scaled layout design
PCT/US2015/010667 WO2015122974A1 (en) 2014-02-14 2015-01-08 Grounding dummy gate in scaled layout design

Publications (2)

Publication Number Publication Date
JP2017506430A JP2017506430A (ja) 2017-03-02
JP2017506430A5 true JP2017506430A5 (enExample) 2018-02-01

Family

ID=53798758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016549575A Pending JP2017506430A (ja) 2014-02-14 2015-01-08 スケーリングされたレイアウト設計におけるダミーゲートのアース

Country Status (5)

Country Link
US (1) US9379058B2 (enExample)
EP (1) EP3105782B1 (enExample)
JP (1) JP2017506430A (enExample)
CN (1) CN105981157B (enExample)
WO (1) WO2015122974A1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224842B2 (en) * 2014-04-22 2015-12-29 Globalfoundries Inc. Patterning multiple, dense features in a semiconductor device using a memorization layer
US10998228B2 (en) * 2014-06-12 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnect with protection layer
US20160005822A1 (en) * 2014-07-01 2016-01-07 Qualcomm Incorporated Self-aligned via for gate contact of semiconductor devices
US10361195B2 (en) * 2014-09-04 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor device with an isolation gate and method of forming
US9496394B2 (en) 2014-10-24 2016-11-15 Globalfoundries Inc. Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
US9570573B1 (en) * 2015-08-10 2017-02-14 Globalfoundries Inc. Self-aligned gate tie-down contacts with selective etch stop liner
US9935100B2 (en) * 2015-11-09 2018-04-03 Qualcomm Incorporated Power rail inbound middle of line (MOL) routing
US10153351B2 (en) 2016-01-29 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
DE102016125299B4 (de) 2016-01-29 2024-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US9548366B1 (en) * 2016-04-04 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self aligned contact scheme
US10141256B2 (en) 2016-04-21 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and layout design thereof
CN107452680B (zh) 2016-06-01 2020-05-05 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9837351B1 (en) * 2016-06-07 2017-12-05 International Business Machines Corporation Avoiding gate metal via shorting to source or drain contacts
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
KR102308779B1 (ko) * 2017-04-10 2021-10-05 삼성전자주식회사 이종 컨택들을 구비하는 집적 회로 및 이를 포함하는 반도체 장치
US10269636B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US10651284B2 (en) * 2017-10-24 2020-05-12 Globalfoundries Inc. Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
US10600866B2 (en) 2018-02-01 2020-03-24 Qualcomm Incorporated Standard cell architecture for gate tie-off
KR102516878B1 (ko) 2018-07-26 2023-03-31 삼성전자주식회사 집적회로 소자
US10832963B2 (en) 2018-08-27 2020-11-10 International Business Machines Corporation Forming gate contact over active free of metal recess
US10950732B2 (en) * 2018-09-21 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US11335596B2 (en) * 2018-10-30 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Selective deposition for integrated circuit interconnect structures
US11056537B2 (en) * 2019-03-27 2021-07-06 International Business Machines Corporation Self-aligned gate contact integration with metal resistor
US11164782B2 (en) 2020-01-07 2021-11-02 International Business Machines Corporation Self-aligned gate contact compatible cross couple contact formation
US12199161B2 (en) 2020-12-16 2025-01-14 Intel Corporation Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication
US12237388B2 (en) * 2020-12-16 2025-02-25 Intel Corporation Transistor arrangements with stacked trench contacts and gate straps
US11723194B2 (en) * 2021-03-05 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit read only memory (ROM) structure
US11929314B2 (en) * 2021-03-12 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures including a fin structure and a metal cap
US11862625B2 (en) 2021-07-01 2024-01-02 Nxp Usa, Inc. Area-efficient ESD protection inside standard cells
US12230684B2 (en) 2021-07-26 2025-02-18 Samsung Electronics Co., Ltd. Integrated circuit with continuous active region and raised source/drain region
US12165920B2 (en) * 2021-08-30 2024-12-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for forming the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5700706A (en) 1995-12-15 1997-12-23 Micron Technology, Inc. Self-aligned isolated polysilicon plugged contacts
JPH09289251A (ja) * 1996-04-23 1997-11-04 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造およびその検証方法
US6242302B1 (en) 1998-09-03 2001-06-05 Micron Technology, Inc. Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry
JP3506025B2 (ja) * 1998-11-30 2004-03-15 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
JP2002208643A (ja) * 2001-01-10 2002-07-26 Mitsubishi Electric Corp 半導体装置の構造およびその製造方法
US7074717B2 (en) 2003-03-04 2006-07-11 Micron Technology, Inc. Damascene processes for forming conductive structures
JP3897730B2 (ja) 2003-04-23 2007-03-28 松下電器産業株式会社 半導体記憶装置および半導体集積回路
KR100665850B1 (ko) 2005-07-22 2007-01-09 삼성전자주식회사 고집적 반도체 메모리 소자용 모오스 트랜지스터들의배치구조 및 그에 따른 배치방법
US7663237B2 (en) * 2005-12-27 2010-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Butted contact structure
US8426310B2 (en) * 2010-05-25 2013-04-23 Freescale Semiconductor, Inc. Method of forming a shared contact in a semiconductor device
US8604531B2 (en) 2010-10-15 2013-12-10 Taiwan Semiconductor Manufacturing Company Method and apparatus for improving capacitor capacitance and compatibility
US8633520B2 (en) * 2010-10-21 2014-01-21 Samsung Electronics Co., Ltd. Semiconductor device
CN102468226B (zh) * 2010-11-18 2014-08-20 中国科学院微电子研究所 一种半导体结构及其制造方法
US8299544B2 (en) 2011-01-04 2012-10-30 International Business Machines Corporation Field effect transistor having ohmic body contact(s), an integrated circuit structure incorporating stacked field effect transistors with such ohmic body contacts and associated methods
DE102011004323B4 (de) 2011-02-17 2016-02-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit selbstjustierten Kontaktelementen und Verfahren zu seiner Herstellung
CN103050525B (zh) 2011-10-12 2015-06-17 中国科学院微电子研究所 Mosfet及其制造方法
US8716124B2 (en) 2011-11-14 2014-05-06 Advanced Micro Devices Trench silicide and gate open with local interconnect with replacement gate process
KR101923120B1 (ko) 2012-03-21 2018-11-28 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
KR102003959B1 (ko) 2012-07-31 2019-07-25 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법

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