JP2015159233A - 被処理体を処理する方法 - Google Patents
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- JP2015159233A JP2015159233A JP2014034050A JP2014034050A JP2015159233A JP 2015159233 A JP2015159233 A JP 2015159233A JP 2014034050 A JP2014034050 A JP 2014034050A JP 2014034050 A JP2014034050 A JP 2014034050A JP 2015159233 A JP2015159233 A JP 2015159233A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Abstract
【解決手段】被処理体を処理する方法は、プラズマ処理装置の静電チャックに被処理体を静電吸着する工程ST1であり、被処理体が基板上に有機ポリマー層及びレジストマスクを有する工程ST1と、第1のガスのプラズマによってレジストマスクを介して有機ポリマー層をエッチングする工程ST2と、第2のガスのプラズマを生成しつつ静電チャックから被処理体を脱着する工程ST3と、レジストマスクを剥離する工程ST4と、を含む。第2のガスは、酸素ガス又はアルゴンガスよりも原子量の小さい希ガスと酸素ガスとの混合ガスである。
【選択図】図1
Description
Claims (2)
- 被処理体を処理する方法であって、
プラズマ処理装置の処理容器内に設けられた静電チャックに対して被処理体を静電吸着する第1工程であり、該被処理体は、シリコンを含有する基板、該基板上に設けられた有機ポリマー層、及び、該有機ポリマー層上にレジストマスクを有する、該第1工程と、
前記レジストマスクを介して前記有機ポリマー層をエッチングするよう、前記処理容器内において発生させた第1のガスのプラズマに前記被処理体を晒す第2工程と、
前記第2工程の後、前記処理容器内において第2のガスのプラズマを生成しつつ前記静電チャックから前記被処理体を脱着する第3工程と、
前記第3工程の後、前記レジストマスクを剥離する第4工程と、
前記第4工程の後、前記被処理体上に、第1のポリマー及び第2のポリマーを含み自己組織化可能なブロック・コポリマー層を形成する第5工程と、
前記ブロック・コポリマー層に前記第1のポリマーを含む第1の領域及び前記第2のポリマーを含む第2の領域を形成するよう前記被処理体を処理する第6工程と、
前記第6工程の後、前記プラズマ処理装置を用いて前記第2の領域をエッチングする第7工程と、
を含み、
前記第2のガスは、酸素ガス、又は、アルゴンガスよりも原子量の小さい希ガスと酸素ガスとの混合ガスである、
方法。 - 前記有機ポリマー層は、ポリスチレン、又はポリスチレンとポリメチルメタクリレートとのランダム共重合体を含む、
請求項1に記載の方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014034050A JP6234271B2 (ja) | 2014-02-25 | 2014-02-25 | 被処理体を処理する方法 |
KR1020167019960A KR102330411B1 (ko) | 2014-02-25 | 2015-01-16 | 피처리체를 처리하는 방법 |
SG11201606375QA SG11201606375QA (en) | 2014-02-25 | 2015-01-16 | Method for processing article |
PCT/JP2015/051029 WO2015129322A1 (ja) | 2014-02-25 | 2015-01-16 | 被処理体を処理する方法 |
US15/117,052 US9911621B2 (en) | 2014-02-25 | 2015-01-16 | Method for processing target object |
TW104105529A TWI628711B (zh) | 2014-02-25 | 2015-02-17 | 被處理體之處理方法 |
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JP2014034050A JP6234271B2 (ja) | 2014-02-25 | 2014-02-25 | 被処理体を処理する方法 |
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JP2015159233A true JP2015159233A (ja) | 2015-09-03 |
JP6234271B2 JP6234271B2 (ja) | 2017-11-22 |
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US (1) | US9911621B2 (ja) |
JP (1) | JP6234271B2 (ja) |
KR (1) | KR102330411B1 (ja) |
SG (1) | SG11201606375QA (ja) |
TW (1) | TWI628711B (ja) |
WO (1) | WO2015129322A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170029389A (ko) * | 2015-09-07 | 2017-03-15 | 아이엠이씨 브이제트더블유 | 트렌치 보조 케모에피탁시(trac) dsa 흐름 |
JP2017055047A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | パターン形成方法 |
JP6458174B1 (ja) * | 2018-01-12 | 2019-01-23 | デクセリアルズ株式会社 | パターン形成方法及び偏光板の製造方法 |
JP7389845B2 (ja) | 2022-04-18 | 2023-11-30 | セメス カンパニー,リミテッド | 基板処理装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10192743B2 (en) * | 2016-08-29 | 2019-01-29 | Tokyo Electron Limited | Method of anisotropic extraction of silicon nitride mandrel for fabrication of self-aligned block structures |
JP6822561B2 (ja) | 2016-11-30 | 2021-01-27 | エルジー・ケム・リミテッド | 積層体 |
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JPH08279487A (ja) * | 1993-05-20 | 1996-10-22 | Hitachi Ltd | プラズマ処理方法 |
JP2004014868A (ja) * | 2002-06-07 | 2004-01-15 | Tokyo Electron Ltd | 静電チャック及び処理装置 |
JP2007027816A (ja) * | 2005-07-12 | 2007-02-01 | Ricoh Co Ltd | 符号化処理装置および方法、並びにプログラムおよび記録媒体 |
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- 2015-01-16 WO PCT/JP2015/051029 patent/WO2015129322A1/ja active Application Filing
- 2015-01-16 US US15/117,052 patent/US9911621B2/en active Active
- 2015-01-16 KR KR1020167019960A patent/KR102330411B1/ko active IP Right Grant
- 2015-02-17 TW TW104105529A patent/TWI628711B/zh active
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JP7389845B2 (ja) | 2022-04-18 | 2023-11-30 | セメス カンパニー,リミテッド | 基板処理装置 |
Also Published As
Publication number | Publication date |
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US20170148641A1 (en) | 2017-05-25 |
KR102330411B1 (ko) | 2021-11-23 |
KR20160125950A (ko) | 2016-11-01 |
SG11201606375QA (en) | 2016-09-29 |
WO2015129322A1 (ja) | 2015-09-03 |
TWI628711B (zh) | 2018-07-01 |
TW201539572A (zh) | 2015-10-16 |
JP6234271B2 (ja) | 2017-11-22 |
US9911621B2 (en) | 2018-03-06 |
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