SG11201606375QA - Method for processing article - Google Patents

Method for processing article

Info

Publication number
SG11201606375QA
SG11201606375QA SG11201606375QA SG11201606375QA SG11201606375QA SG 11201606375Q A SG11201606375Q A SG 11201606375QA SG 11201606375Q A SG11201606375Q A SG 11201606375QA SG 11201606375Q A SG11201606375Q A SG 11201606375QA SG 11201606375Q A SG11201606375Q A SG 11201606375QA
Authority
SG
Singapore
Prior art keywords
processing article
article
processing
Prior art date
Application number
SG11201606375QA
Inventor
Toshikatsu Tobana
Gen You
Soichiro Okada
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of SG11201606375QA publication Critical patent/SG11201606375QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
SG11201606375QA 2014-02-25 2015-01-16 Method for processing article SG11201606375QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014034050A JP6234271B2 (en) 2014-02-25 2014-02-25 Method for processing an object
PCT/JP2015/051029 WO2015129322A1 (en) 2014-02-25 2015-01-16 Method for processing article

Publications (1)

Publication Number Publication Date
SG11201606375QA true SG11201606375QA (en) 2016-09-29

Family

ID=54008651

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201606375QA SG11201606375QA (en) 2014-02-25 2015-01-16 Method for processing article

Country Status (6)

Country Link
US (1) US9911621B2 (en)
JP (1) JP6234271B2 (en)
KR (1) KR102330411B1 (en)
SG (1) SG11201606375QA (en)
TW (1) TWI628711B (en)
WO (1) WO2015129322A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102651697B1 (en) * 2015-09-07 2024-03-27 아이엠이씨 브이제트더블유 Trench assisted chemoepitaxy (trac) dsa flow
JP6346132B2 (en) * 2015-09-11 2018-06-20 株式会社東芝 Pattern formation method
WO2018044727A1 (en) * 2016-08-29 2018-03-08 Tokyo Electron Limited Method of anisotropic extraction of silicon nitride mandrel for fabrication of self-aligned block structures
KR102261687B1 (en) 2016-11-30 2021-06-08 주식회사 엘지화학 Laminate
JP6458174B1 (en) * 2018-01-12 2019-01-23 デクセリアルズ株式会社 Pattern forming method and manufacturing method of polarizing plate
JP7389845B2 (en) 2022-04-18 2023-11-30 セメス カンパニー，リミテッド Substrate processing equipment

Family Cites Families (21)

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JPH08279487A (en) * 1993-05-20 1996-10-22 Hitachi Ltd Plasma processing method
JP3360404B2 (en) 1994-04-01 2002-12-24 ソニー株式会社 Plasma etching method
US5869401A (en) * 1996-12-20 1999-02-09 Lam Research Corporation Plasma-enhanced flash process
US6872322B1 (en) * 1997-11-12 2005-03-29 Applied Materials, Inc. Multiple stage process for cleaning process chambers
TW527646B (en) * 2001-07-24 2003-04-11 United Microelectronics Corp Method for pre-cleaning residual polymer
JP2004014868A (en) * 2002-06-07 2004-01-15 Tokyo Electron Ltd Electrostatic chuck and processing apparatus
US20030236004A1 (en) * 2002-06-24 2003-12-25 Applied Materials, Inc. Dechucking with N2/O2 plasma
US20050066994A1 (en) * 2003-09-30 2005-03-31 Biles Peter John Methods for cleaning processing chambers
JP2007027816A (en) * 2005-07-12 2007-02-01 Ricoh Co Ltd Coding processing device and method therefor, program, and recording medium
EP2034296B1 (en) * 2007-09-07 2012-09-26 Imec Quantification of hydrophobic and hydrophilic properties of materials
JP2010040822A (en) * 2008-08-06 2010-02-18 Tokyo Electron Ltd Destaticization method for electrostatic absorption device, substrate treatment device and storage medium
US8525139B2 (en) * 2009-10-27 2013-09-03 Lam Research Corporation Method and apparatus of halogen removal
JP5284300B2 (en) 2010-03-10 2013-09-11 株式会社東芝 Semiconductor light emitting element, lighting device using the same, and method for manufacturing semiconductor light emitting element
US10538859B2 (en) * 2010-12-23 2020-01-21 Asml Netherlands B.V. Methods for providing patterned orientation templates for self-assemblable polymers for use in device lithography
US8832916B2 (en) * 2011-07-12 2014-09-16 Lam Research Corporation Methods of dechucking and system thereof
US8691925B2 (en) * 2011-09-23 2014-04-08 Az Electronic Materials (Luxembourg) S.A.R.L. Compositions of neutral layer for directed self assembly block copolymers and processes thereof
JP2013201356A (en) * 2012-03-26 2013-10-03 Toshiba Corp Exposure method and pattern formation method
JP5973763B2 (en) 2012-03-28 2016-08-23 東京エレクトロン株式会社 Method and apparatus for forming periodic patterns using self-organizable block copolymers
JP2014027228A (en) * 2012-07-30 2014-02-06 Tokyo Electron Ltd Substrate processing method, program, computer storage medium, and substrate processing system
US8975009B2 (en) * 2013-03-14 2015-03-10 Tokyo Electron Limited Track processing to remove organic films in directed self-assembly chemo-epitaxy applications
US9147574B2 (en) * 2013-03-14 2015-09-29 Tokyo Electron Limited Topography minimization of neutral layer overcoats in directed self-assembly applications

Also Published As

Publication number Publication date
US9911621B2 (en) 2018-03-06
TW201539572A (en) 2015-10-16
JP2015159233A (en) 2015-09-03
JP6234271B2 (en) 2017-11-22
KR102330411B1 (en) 2021-11-23
TWI628711B (en) 2018-07-01
WO2015129322A1 (en) 2015-09-03
US20170148641A1 (en) 2017-05-25
KR20160125950A (en) 2016-11-01

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