JP2014530504A - ナノワイヤサイズ光電構造及びそれを製造する方法 - Google Patents
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Abstract
Description
図6aは、図4aに類似する構造を示す。先に図4aに関して説明したように、2つの厚さを有するフォトレジスト層又はフォトレジストパターン10bは、非活性領域13のナノワイヤを完全に被覆する一方、LED領域14のナノワイヤを部分的に取り囲むので、ナノワイヤの最上部は露出したまま残される。nパッド領域11及びpパッド領域15は開放されており、フォトレジストパターン10bにより被覆されない。
Claims (28)
- 光電構造であって、
支持層の上に並列配置された複数のナノ素子であって、各ナノ素子が、少なくとも第1の導電型の半導体ナノサイズコアを有しており、前記コアと第2の導電型の半導体とがpn接合又はpin接合を形成している複数のナノ素子と、
前記複数のナノ素子の上に配され、前記第2の導電型の半導体の少なくとも一部と電気的に接触する第1の電極層と、
前記構造の第2の導電型の半導体の側に設けられたミラーと、を備える
ことを特徴とする構造。 - 前記ミラーは、前記第1の電極層の上に反射材料層として設けられている
ことを特徴とする請求項1に記載の構造。 - 前記ナノサイズコアに電気的に接続された第2の電極層を更に備える
ことを特徴とする請求項2に記載の構造。 - 前記支持層は、基板上にn型半導体バッファ層を有しており、
前記バッファ層はnコンタクトとして機能し、且つ、
前記第2の電極層は前記バッファ層と接触している
ことを特徴とする請求項3に記載の構造。 - 前記第1の電極層は反射性であり且つ前記ミラーを含んでいる
ことを特徴とする請求項1に記載の構造。 - 前記第1の電極層は透明である
ことを特徴とする請求項2に記載の構造。 - 前記第1の電極層の厚さは150nm〜900nmである
ことを特徴とする請求項2に記載の構造。 - 前記ミラーの上に拡散障壁層を更に備える
ことを特徴とする請求項3に記載の構造。 - 前記拡散障壁層の上に共融接合層又はめっき接合層を更に備える
ことを特徴とする請求項8に記載の構造。 - 前記第1の電極の上に透明絶縁層を更に備えており、
前記透明絶縁層は前記ミラーに対して平坦な面を形成し、且つ、
前記ミラーは、前記透明絶縁層の開口部を通して前記第1の電極層と電気的に接触している
ことを特徴とする請求項9に記載の構造。 - 前記構造は、前記共融接合層又は前記めっき接合層を用いて担持体上のコンタクト電極に接合されたフリップチップであり、
前記担持体の第1の部分は、前記共融接合層又は前記めっき接合層と、前記拡散障壁層と、前記ミラーとによって前記第1の電極層に電気的に接続されており、且つ、
前記担持体の第2の部分は、ワイヤによって前記第2の電極層に接続されている
ことを特徴とする請求項10に記載の構造。 - 前記第2の導電型の半導体は、前記ナノ素子の一部である半導体シェルを有しており、
各ナノ素子は、前記コアと、前記シェルと、前記コアと前記シェルとの間の活性領域とを含むナノ構造を有している
ことを特徴とする請求項2に記載の構造。 - 前記第2の導電型の半導体は、前記ナノ素子の一部ではないバルク半導体素子を有しており、
前記コアは、前記第1の導電型の半導体ナノワイヤ、又は、前記第1の導電型の前記半導体ナノワイヤ及び前記第1の導電型の少なくとも1つの半導体シェルを有しており、
各ナノ素子は、前記コアと、前記コアと前記バルク半導体素子との間の活性領域とを含むナノ構造を有している
ことを特徴とする請求項2に記載の構造。 - 光電構造を製造する方法であって、
支持層を準備する工程と、
前記支持層の上に並列配置された複数のナノ素子を準備する工程であって、各ナノ素子が、少なくとも第1の導電型の半導体ナノサイズコアを有し、前記コアと第2の導電型の半導体とがpn接合又はpin接合を形成する工程と、
前記複数のナノ素子の上に配され、前記第2の導電型の半導体の少なくとも一部と電気的に接触する第1の電極層を形成する工程と、
前記構造の第2の導電型の半導体側にミラーを配置する工程と、を有する
ことを特徴とする方法。 - 前記第1の導電型はn型であり、
前記第2の導電型はp型であり、且つ、
前記第1の電極層はp電極層である
ことを特徴とする請求項14に記載の方法。 - 前記n型コアに電気的に接続する第2のn電極層を成膜する工程を更に有する
ことを特徴とする請求項15に記載の方法。 - 前記支持層は基板上にn型半導体バッファ層を有し、
前記バッファ層はnコンタクトとして作用し、且つ、
前記n電極層は前記バッファ層と接触する
ことを特徴とする請求項16に記載の方法。 - 前記第2の導電型の半導体は、前記ナノ素子の一部である半導体シェルを有しており、
各ナノ素子は、前記コアと、前記シェルと、前記コアと前記シェルとの間の活性領域とを含むナノ構造を有している
ことを特徴とする請求項16に記載の方法。 - 前記第2の導電型の半導体は、前記ナノ素子の一部ではないバルク半導体素子を有しており、
前記コアは、前記第1の導電型の半導体ナノワイヤ、又は、前記第1の導電型の前記半導体ナノワイヤ及び前記第1の導電型の少なくとも1つの半導体シェルを有しており、
各ナノ素子は、前記コアと、前記コアと前記バルク半導体素子との間の活性領域とを含むナノ構造を有している
ことを特徴とする請求項16に記載の方法。 - 前記第1の電極層は反射性であり且つ前記ミラーを含み、前記第1の電極を形成する工程と前記ミラーを配置する工程とは同一の工程である
ことを特徴とする請求項16に記載の方法。 - 前記第1の電極層は反射性であり、
前記ミラーは、前記第1の電極層と電気的に接触するように成膜された反射導電層を含む
ことを特徴とする請求項16に記載の方法。 - 前記第1の電極層の上に透明絶縁層を成膜する工程と、前記透明絶縁層を平坦化することと、前記透明絶縁層に開口部を形成する工程と、を更に有しており、
前記反射導電層は、前記第1の電極層と電気的に接触するように前記透明絶縁層の前記開口部の中に成膜される
ことを特徴とする請求項21に記載の方法。 - 前記透明絶縁層はスピンオングラスを含む
ことを特徴とする請求項22に記載の方法。 - 前記ミラーの上に拡散障壁層を成膜する工程と、前記拡散障壁層の上に共融接合層又はめっき接合層を成膜する工程と、を更に有する
ことを特徴とする請求項22に記載の方法。 - 前記共融接合層又は前記めっき接合層を用いて共融接合又は溶融接合を行うことにより前記構造を担持体上のコンタクト電極にフリップチップ接合する工程を更に有する
ことを特徴とする請求項24に記載の方法。 - 前記担持体の第1の部分は、前記共融接合層又は前記めっき接合層と、前記拡散障壁層と、前記ミラーとによって前記第1の電極層に電気的に接続され、
前記担持体の第2の部分は、ワイヤによって前記第2の電極層に接続される
ことを特徴とする請求項25に記載の方法。 - 前記基板は、エッチング、研削又は研磨により除去される
ことを特徴とする請求項17に記載の方法。 - 前記バッファ層は、光の抽出が大きくなるように、粗面化され、又は、エッチングされる
ことを特徴とする請求項27に記載の方法。
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US13/251,555 US8350251B1 (en) | 2011-09-26 | 2011-10-03 | Nanowire sized opto-electronic structure and method for manufacturing the same |
US13/251,555 | 2011-10-03 | ||
PCT/US2012/057029 WO2013049008A2 (en) | 2011-09-26 | 2012-09-25 | Nanowire sized opto-electronic structure and method for manufacturing the same |
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US8350251B1 (en) | 2013-01-08 |
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CN104321887B (zh) | 2017-05-31 |
EP2761678A2 (en) | 2014-08-06 |
WO2013049008A2 (en) | 2013-04-04 |
US20150207037A1 (en) | 2015-07-23 |
KR20140067076A (ko) | 2014-06-03 |
KR101944327B1 (ko) | 2019-01-31 |
WO2013049008A3 (en) | 2013-05-23 |
SG11201400882QA (en) | 2014-04-28 |
JP6077549B2 (ja) | 2017-02-08 |
US8937295B2 (en) | 2015-01-20 |
CN104321887A (zh) | 2015-01-28 |
EP2761678A4 (en) | 2015-06-17 |
US20130092900A1 (en) | 2013-04-18 |
TW201322490A (zh) | 2013-06-01 |
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