JP6219506B2 - ナノワイヤデバイスの活性領域の平坦化および規定のための絶縁層 - Google Patents
ナノワイヤデバイスの活性領域の平坦化および規定のための絶縁層 Download PDFInfo
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Description
ナノワイヤ発光ダイオード(LED)は、プレーナ型LEDに代わる手段として、ますます多くの関心を集めている。ナノワイヤLEDは、従来型のプレーナ技術で製造されたLEDと比べると、ナノワイヤの3次元性に起因する独特の特性であって、より大きい基板上での処理のための格子整合の制限および機会を低減する材料の組み合わせの柔軟性を向上させる特性を示す。
実施形態は、半導体デバイスの製造方法を含み、該製造方法は、複数のナノワイヤであって各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤを基台上に形成する工程と、絶縁材料の層を、前記絶縁材料の層の少なくとも一部が実質的に平らな上面を与えるように、前記複数のナノワイヤの少なくとも一部の上に形成する工程と、ナノワイヤの活性領域を規定するように前記絶縁材料の層の一部を除去する工程と、前記絶縁材料の層の前記実質的に平らな上面の上に電気接触を形成する工程と、を有する。
Claims (14)
- 複数のナノワイヤであって各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤを基台上に形成する工程と、
絶縁材料の層を、前記絶縁材料の層の少なくとも一部が実質的に平らな上面を与えるように、前記複数のナノワイヤの少なくとも一部の上に形成する工程と、
ナノワイヤの活性領域を規定するように前記絶縁材料の層の一部を除去する工程と、
前記絶縁材料の層の前記実質的に平らな上面の上に電気接触を形成する工程と、
前記絶縁材料の層の少なくとも一部および前記活性領域の前記複数のナノワイヤの上に導電材料の層を形成する工程と、を有し、
前記電気接触は、前記導電材料の層に電気的に接続され、
前記導電材料の層は、前記活性領域の前記ナノワイヤと接触し、前記実質的に平らな上面の上で前記絶縁材料の層と接触し、前記電気接触は、前記導電材料の上に形成される
ことを特徴とする半導体デバイスの製造方法。 - 前記デバイスはナノワイヤLEDを含む
ことを特徴とする請求項1記載の半導体デバイスの製造方法。 - ナノワイヤの前記活性領域の周辺の境界を与えるように前記絶縁材料の一部を維持する工程をさらに有する
ことを特徴とする請求項1記載の半導体デバイスの製造方法。 - 前記絶縁材料の層の一部を除去する工程は、ナノワイヤの前記活性領域を規定するように第1のマスクを介して前記絶縁材料の層をエッチングする工程を含み、
前記製造方法は、
第2のマスクを介してエッチングして、前記基台の一部が露出するようにナノワイヤおよび前記導電材料の層の一部を除去する工程と、
前記デバイスの上に、前記導電材料の層の上および前記絶縁材料の層の前記平らな上面の上の第1の開口と、前記基台の前記露出された一部の上の第2の開口とを有する第3のマスクを形成する工程と、
前記導電材料の層に電気的に接続された前記電気接触を形成するように前記第1の開口に金属材料を堆積する工程と、
前記基台の前記露出された一部の上に第2の電気接触を形成するように前記第2の開口に金属材料を堆積する工程と、
前記第3のマスクを除去する工程と、をさらに有する
ことを特徴とする請求項1記載の半導体デバイスの製造方法。 - 複数のナノワイヤであって各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤを基台上に形成する工程と、
絶縁材料の層を、前記絶縁材料の層の少なくとも一部が実質的に平らな上面を与えるように、前記複数のナノワイヤの少なくとも一部の上に形成する工程と、
ナノワイヤの活性領域を規定するように前記絶縁材料の層の一部を除去する工程と、
前記絶縁材料の層の前記実質的に平らな上面の上に電気接触を形成する工程と、
前記絶縁材料の層の少なくとも一部および前記活性領域の前記複数のナノワイヤの上に導電材料の層を形成する工程と、
ここで、前記電気接触は、前記導電材料の層に電気的に接続され、
前記基台の一部が露出するようにナノワイヤおよび前記導電材料の層の一部を除去する工程と、
前記基台の前記露出された一部の上に第2の電気接触を形成する工程と、を有する
ことを特徴とする半導体デバイスの製造方法。 - 複数のナノワイヤであって各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤを基台上に形成する工程と、
絶縁材料の層を、前記絶縁材料の層の少なくとも一部が実質的に平らな上面を与えるように、前記複数のナノワイヤの少なくとも一部の上に形成する工程と、
ナノワイヤの活性領域を規定するように前記絶縁材料の層の一部を除去する工程と、
前記絶縁材料の層の前記実質的に平らな上面の上に電気接触を形成する工程と、
前記絶縁材料の層の少なくとも一部および前記活性領域の前記複数のナノワイヤの上に導電材料の層を形成する工程と、を有し、
前記電気接触は、前記導電材料の層に電気的に接続され、
前記デバイスはナノワイヤLEDを含み、
前記導電材料の層は、透明な導電性酸化物(TCO)を含む
ことを特徴とする半導体デバイスの製造方法。 - 前記TCOは、インジウムスズ酸化物(ITO)を含む
ことを特徴とする請求項6記載の半導体デバイスの製造方法。 - 複数のナノワイヤであって各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤを基台上に形成する工程と、
絶縁材料の層を、前記絶縁材料の層の少なくとも一部が実質的に平らな上面を与えるように、前記複数のナノワイヤの少なくとも一部の上に形成する工程と、
ナノワイヤの活性領域を規定するように前記絶縁材料の層の一部を除去する工程と、
前記絶縁材料の層の少なくとも一部および前記活性領域の前記複数のナノワイヤの上に導電材料の層を形成する工程と、
前記絶縁材料の層の前記実質的に平らな上面の上に電気接触を形成する工程と、を有し、
前記電気接触は、前記導電材料の層に電気的に接続され、
前記導電材料の層は、前記活性領域における前記ナノワイヤの前記第2導電型の半導体シェルと接触するp型の電極を備える
ことを特徴とする半導体デバイスの製造方法。 - 前記活性領域を規定するように前記絶縁材料の層の一部を除去する工程の後に、該活性領域の上に誘電性の層を形成する工程を更に有する
ことを特徴とする請求項8記載の半導体デバイスの製造方法。 - 前記基台上に位置するn型のバッファ層と接触する導電性のn型のコンタクトを形成する工程を更に有する
ことを特徴とする請求項8記載の半導体デバイスの製造方法。 - 前記導電材料の層は、前記絶縁材料の層の前記実質的に平らな上面の少なくとも一部の上に位置し、
前記電気接触は、前記絶縁材料の層の前記実質的に平らな上面の或る領域において前記導電材料の層の上に位置する
ことを特徴とする請求項8記載の半導体デバイスの製造方法。 - 基台上の複数のナノワイヤであって、各ナノワイヤが第1導電型の半導体コアと該コアの上の第2導電型の半導体シェルとを含む複数のナノワイヤと、
実質的に平らな上面を有し、ナノワイヤの活性領域を規定するように前記複数のナノワイヤの周囲の境界を形成する絶縁材料の層と、
前記絶縁材料の層の前記実質的に平らな上面の少なくとも一部の上に位置し且つ前記活性領域において前記複数のナノワイヤの前記第2導電型の半導体シェルと接触するp型の電極を含む導電材料の層と、
前記絶縁材料の層の前記実質的に平らな上面の或る領域において前記導電材料の層の上に位置する電気接触と、を備える
ことを特徴とする半導体デバイス。 - 前記活性領域の上に位置する誘電性の層を更に備える
ことを特徴とする請求項12記載の半導体デバイス。 - 前記基台上に位置するn型のバッファ層と接触する導電性のn型のコンタクトを更に備える
ことを特徴とする請求項12記載の半導体デバイス。
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JP4058937B2 (ja) | 2001-11-07 | 2008-03-12 | 松下電器産業株式会社 | 半導体発光装置及びその製造方法 |
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2014
- 2014-06-17 WO PCT/US2014/042649 patent/WO2014204906A1/en active Application Filing
- 2014-06-17 JP JP2016521498A patent/JP6219506B2/ja not_active Expired - Fee Related
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- 2014-06-17 US US14/306,563 patent/US9224914B2/en not_active Expired - Fee Related
- 2014-06-17 TW TW103120902A patent/TW201515269A/zh unknown
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Publication number | Publication date |
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WO2014204906A1 (en) | 2014-12-24 |
US9640723B2 (en) | 2017-05-02 |
TW201515269A (zh) | 2015-04-16 |
US9224914B2 (en) | 2015-12-29 |
EP3011607A1 (en) | 2016-04-27 |
US20140367638A1 (en) | 2014-12-18 |
US20160172538A1 (en) | 2016-06-16 |
JP2016526789A (ja) | 2016-09-05 |
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