JP2014099470A - 半導体装置および半導体集積回路装置、電子装置 - Google Patents
半導体装置および半導体集積回路装置、電子装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 135
- 230000017525 heat dissipation Effects 0.000 claims abstract description 81
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 40
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Abstract
【解決手段】半導体装置は、半導体基板と、前記半導体基板上に形成された活性素子と、を含み、前記多層配線構造中には層間絶縁膜が順次積層されており、前記多層配線構造中には、上端が外部配線基板に接続される外部接続パッドを構成する放熱構造が、下端が前記半導体基板の表面に接触して設けられている。
【選択図】図1
Description
図1は第1の実施形態による電子装置10Aの構成を示す断面図である。
図7は、第2の実施形態による電子装置10Bの構成を示す断面図である。ただし図7中、先に説明した部分には同一の参照符号を付し、説明を省略する。
図11(A)〜(C)は、半導体チップ21の表面上に形成された様々な電力増幅器のレイアウトを示す平面図である。
図13は、図7〜図9の実施形態で説明した構成の電子装置により電力増幅器を構成し、かかる電力増幅器を、半導体チップ21よりなる半導体チップ21Chip上に、周辺回路装置とともに集積化した半導体集積回路装置40を示す平面図である。
11 配線基板
11G 接地配線パターン
11S 信号配線パターン
11H 導体パターン
11H/11G 放熱/接地配線パターン
20H,20H1 放熱構造
21 シリコン基板
21A,21A1,21A2 素子領域
21B 放熱領域
21I 素子分離領域
21NW n型ウェル
21PW p型ウェル
21a ソース領域
21b ドレイン領域
22 ゲート絶縁膜
23 ゲート電極
23P ポリシリコンパターン
23SW ゲート側壁絶縁膜
24〜28 層間絶縁膜
24S〜28S ソース配線パターン
24D〜28D ドレイン配線パターン
24H〜28H Cu放熱パッド
24M ドレイン配線パターン
24s〜28s,24d〜28d,24h〜28h Cuビアプラグ
29 パッシベーション膜
29A,29B,29H 開口部
30A,30B,30H ハンダバンプ
40 半導体集積回路装置
40A ベースバンド回路部
40B トランシーバ部
40C 電力増幅部
50 無線装置
50A ベースバンド回路
50B トランシーバ
50C 電力増幅器
50D デュプレクサ
50E アンテナ
AA アンプアレイ
BK1〜BK4 ブロック
Claims (17)
- 半導体基板と、
前記半導体基板上に形成された活性素子と、
前記半導体基板上に形成された多層配線構造と、
を含み、
前記多層配線構造中には、上端が外部配線基板に接続される外部接続パッドを構成する放熱構造が、下端が前記半導体基板の表面に、前記活性素子の素子領域の外でコンタクトして設けられていることを特徴とする半導体装置。 - 前記多層配線構造中には層間絶縁膜が順次積層されており、
前記層間絶縁膜はそれぞれの配線層を含み、
前記配線層の各々は一部にパッドと前記パッドから下方に延在する複数のビアプラグとを含み、
前記放熱構造は、前記層間絶縁膜の各々に形成されたパッドおよびビアプラグより構成されており、
前記放熱構造中、最下層の層間絶縁膜を除いた一の層間絶縁膜中のビアプラグは、その下の層間絶縁膜中のパッドにコンタクトし、
前記放熱構造中、前記最下層の層間絶縁膜中のビアプラグは前記半導体基板の表面に、前記放熱構造の前記下端としてコンタクトすることを特徴とする請求項1記載の半導体装置。 - 前記放熱構造中、前記一の層間絶縁膜中のパッドは、その下の層間絶縁膜中のパッドの直上に形成されることを特徴とする請求項2記載の半導体装置。
- 素子領域が前記半導体基板上に素子分離領域により画成されており、前記放熱構造の下端は前記半導体基板の表面のうち、前記素子領域および素子分離領域よりなる領域の外でコンタクトすることを特徴とする請求項1〜3のうち、いずれか一項記載の半導体装置。
- 前記活性素子は接地ノードとなる拡散領域を有し、前記放熱構造の前記下端は前記拡散領域に電気的に接続されていることを特徴とする請求項1〜4のうち、いずれか一項記載の半導体装置。
- 前記拡散領域は、前記多層配線構造に、前記放熱構造を介して電気的に接続されていることを特徴とする請求項5記載の半導体装置。
- 前記活性素子はMOSトランジスタであり、前記拡散領域は前記MOSトランジスタのソース拡散領域であることを特徴とする請求項5または6記載の半導体装置。
- 前記放熱構造の下端がコンタクトする前記半導体基板の表面には、前記半導体基板の導電型とは逆導電型のウェルが形成されていることを特徴とする請求項5〜7のうち、いずれか一項記載の半導体装置。
- 前記放熱構造の下端がコンタクトする前記半導体基板の表面には、前記半導体基板の導電型とは逆導電型の第1のウェルが形成され、前記第1のウェルの内側には前記半導体基板と同じ導電型の第2のウェルが形成され、前記放熱構造の下端は前記第2のウェルにコンタクトしていることを特徴とする請求項5〜8のうち、いずれか一項記載の半導体装置。
- 前記放熱構造の上端が構成する前記外部接続パッドは、前記外部配線基板上の導体パターンにハンダバンプを介して接合されることを特徴とする請求項1〜9のうち、いずれか一項記載の半導体装置。
- 半導体基板と、
前記半導体基板上に形成された活性素子と、
前記半導体基板上に形成された多層配線構造と、
を含み、
前記活性素子は拡散領域を含み、
前記多層配線構造中の配線層が前記拡散領域の第1の領域においてにビアプラグを介して電気的に接続され、
前記多層配線構造中には、上端が外部配線基板に接続される外部接続パッドを構成する放熱構造が設けられ、
前記放熱構造の下端が前記拡散領域に、前記第1の領域とは別の第2の領域においてコンタクトして設けられていることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板上の第1の素子領域に形成され、第1の周波数で動作する第1の半導体素子を含む第1の機能ブロックと、
前記半導体基板上の第2の素子領域に形成され、前記第1の周波数よりも低い第2の周波数で動作する第2の半導体素子を含む第2の機能ブロックと、
前記半導体基板上に形成された多層配線構造と、
を含み、
前記多層配線構造中には複数の層間絶縁膜が順次積層されており、
前記複数の層間絶縁膜はそれぞれの配線層を含み、
さらに前記多層配線構造中には、前記第1の機能ブロックを囲んで複数の放熱構造が、前記半導体基板の表面に接して形成されており、
前記各々の放熱構造は、前記複数の層間絶縁膜のそれぞれの配線層の一部により構成され最下層の層間絶縁膜から最上層の層間絶縁膜まで順次積層された複数のパッド領域と、前記複数のパッド領域のそれぞれから下方に延在する複数のビアプラグとを含み、
前記複数の層間絶縁膜のうち最下層の層間絶縁膜を除いた一の層間絶縁膜中のビアプラグは、その下の層間絶縁膜中のパッド領域にコンタクトし、
前記最下層の層間絶縁膜中のビアプラグは前記半導体基板の表面に、前記第1の素子領域の外でコンタクトすることを特徴とする半導体集積回路装置。 - 前記少なくとも一つの前記放熱構造は、前記半導体基板上で前記第1の機能ブロックと前記第2の機能ブロックとの間に配設されていることを特徴とする請求項12記載の半導体集積回路装置。
- 前記少なくとも一つの前記放熱構造は、前記第1の半導体素子の接地ノードを構成する拡散領域に前記多層配線構造により電気的に接続されていることを特徴とする請求項12または13記載の半導体集積回路装置。
- 前記第1の機能ブロックにおいて前記第1の半導体素子は高周波増幅器を構成することを特徴とする請求項12〜14のうち、いずれか一項記載の半導体集積回路装置。
- 配線基板と、
前記配線基板にフリップチップ実装された半導体チップと、
を含み、
前記半導体チップは請求項12〜15のいずれか一項に記載の半導体集積回路装置を含み、
前記放熱構造は前記配線基板上の接地パターンに、はんだバンプを介して接続されていることを特徴とする電子装置。 - 前記配線基板上の接地パターンは、前記配線基板上において信号伝送系の一部を構成する接地パターンとは別に設けられていることを特徴とする請求項16記載の電子装置。
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