JP2014011175A - ショットキーバリアダイオード及びそれを用いた装置 - Google Patents
ショットキーバリアダイオード及びそれを用いた装置 Download PDFInfo
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Abstract
【解決手段】 第一の半導体層に接して配置されたLOCOS層と、前記第一の半導体層と第一の電極との接触面に形成されたショットキー接合領域と、前記第一の半導体層と接続された、前記第一の半導体層よりキャリア濃度の高い第二の半導体層と、前記第二の半導体層とオーミック接続された第二の電極とを備え、
前記ショットキー接合領域と前記LOCOS層とが接することを特徴とするショットキーバリアダイオードを提供するものである。
【選択図】 図1
Description
実施形態1に係るショットキーバリアダイオードについて、図1、図2を用いて説明する。図1及び図2に示す様に、本実施形態のショットキーバリアダイオード100は、基板101と、その上に形成された第一の半導体層102と、これよりはキャリア濃度の高い第二の半導体層103、LOCOS層105とを備える。また、ショットキーバリアダイオード100は、第一の半導体層102の一部とショットキー接続された第一の電極(以下、ショットキー電極と言う。)106と、第二の半導体層103とオーミック接続された第二の電極(以下、オーミック電極と言う。)107とを備える。
(A)基板101上の半導体層102の上面に、パッド酸化膜410を介してSi3N4を含むパターン層409を形成する工程(図4(a))
(B)熱酸化法により半導体層102を熱酸化して、パターン層409の周囲にLOCOS層105とパターン層409の下にメサ構造108を形成する工程(図4(b))
(C)パターン層409を除去して半導体層102の表面を露出する工程(図4(c))
(D)LOCOS層105と接し、且つ、LOCOS層105とオーバーラップするように、半導体層102の表面とショットキー接触するショットキー電極106を形成する工程(図4(d))
(E)半導体層102の一部とオーミック接触するオーミック電極107を形成する工程(図4(d))
この製造方法では、半導体層102の露出部分に対して、ショットキー電極106を構成する金属膜をLOCOS層105にオーバーラップするように上から成膜することで、微小面積のショットキー接合領域104を高い精度で形成することが出来る。半導体層102の露出部分の面積は、従来のLOCOSプロセスで知られるようなSi3N4を含むパターン層409の寸法を制御する方法でコントロール可能である。
(F)半導体層412を、LOCOS層105に周囲を囲まれて露出した半導体層102の表面にのみ選択的にエピタキシャル成長する工程(図4(e))。ここで、半導体層412は、半導体層102よりキャリア濃度が低い層を含むことが好ましい。また、LOCOS105層は、選択的なエピタキシャル成長時のマスクとなっている。
(G)LOCOS層105と接し、且つ、LOCOS層105とオーバーラップするように、半導体層412の表面とショットキー接触するショットキー電極106を形成する工程(図4(f))
この製造方法は、LOCOS層105をマスクにして、LOCOS層105に周囲を囲まれて露出した半導体層102の表面にのみ選択的に半導体層412をエピタキシャル成長する技術を用いることが出来る。従って、半導体層412としては、キャリア濃度などの特性を変化させたSiや、SiGe、GaAs、InGaAs、AlAsなどのSi以外の半導体材料を選択することが出来るようになり、高感度化や高周波化が期待される。
実施形態2に係る検出素子500について、図5を用いて説明する。本実施形態は、実施形態1の変形例である。図5(a)に示した本実施形態が、実施形態1と異なるのは、基板101と誘電体520によって半導体層102及び103を島状に分離している点である。つまり、ショットキー電極106及びオーミック電極107と、第一の半導体層102及び第二の半導体層103が、101の半導体基板上に島状に配されている構成である。また、ショットキー電極106とオーミック電極107には、それぞれ、導電層であるアンテナ109、110が接続されている。その他は、実施形態1と同様であり、本発明の特徴であるLOCOS層105は、ショットキー接合領域104の周囲に接して配置されている。
実施形態2に対応するより具体的な検出素子500について、図6を用いて説明する。本実施例は、電磁波を検出するための用途に好適なショットキーバリアダイオードを用いた検出素子の一実施例である。
実施例2に係る検出素子500について、図8を用いて説明する。図8に示す本実施例は、実施例1の変形例である。本実施例は、検出信号をアンプするための用途で使用することができる好適な検出素子の実施例を示すもので、同じSi基板101上に集積したMOSFET830によって検出信号をアンプすることが可能である。
500,500(a〜i) 検出素子
101 基板
102 第一の半導体層
103 第二の半導体層
104 ショットキー接合領域
105 LOCOS層
106 ショットキー電極(第一の電極)
107 オーミック電極(第二の電極)
108 メサ構造
409 パターン層
410 パッド酸化膜
412 半導体層
520,620,720,820 誘電体
109,110 アンテナ
523,723,823 島
724,725 読み出し線
830 MOSFET
831 ゲート電極
832 ゲート絶縁膜
833 ソース電極
834 ドレイン電極
835 イオン注入領域
836 配線
Claims (15)
- ショットキーバリアダイオードであって、
第一の半導体層と、
前記第一の半導体層に接して配置されたLOCOS層と、
前記第一の半導体層と第一の電極との接触面に形成されるショットキー接合領域と、
前記第一の半導体層と接続され、前記第一の半導体層よりキャリア濃度の高い第二の半導体層と、
前記第二の半導体層とオーミック接続される第二の電極とを備え、
前記ショットキー接合領域と前記LOCOS層とが接していることを特徴とするショットキーバリアダイオード。 - 基板の上に、前記第二の半導体層、前記第一の半導体層の順に積層されたことを特徴とする請求項1記載のショットキーバリアダイオード。
- 前記第一の電極又は前記第二の電極は、前記LOCOS層の上部の少なくとも一部にも形成されていることを特徴とする請求項1〜2の何れか1項に記載のショットキーバリアダイオード。
- 前記ショットキー接合領域の周囲が前記LOCOS層に覆われていることを特徴とする請求項1〜3の何れか1項に記載のショットキーバリアダイオード。
- 前記LOCOS層は、前記第一の電極と前記第二の電極との間を絶縁することを特徴とする請求項1〜4の何れか1項に記載のショットキーバリアダイオード。
- 前記第一の半導体層は、エピタキシャル成長させた半導体を含むことを特徴とする請求項1〜5の何れか1項に記載のショットキーバリアダイオード。
- 前記ショットキーバリアダイオードが、半導体基板上に島状に配されたことを特徴とする請求項1〜6の何れか1項に記載のショットキーバリアダイオード。
- 請求項1〜7の何れか1項に記載のショットキーバリアダイオードと、
検出電磁波の電界成分を前記第一の電極と前記第二の電極の間に誘起するためのアンテナと、を備え、
前記第一の電極と前記第二の電極を前記アンテナの出力ポートとすることを特徴とする検出素子。 - 請求項1〜7の何れか1項に記載のショットキーバリアダイオードと、
検出信号を出力するためのトランジスタと、を備え、
前記検出素子と前記トランジスタが同一基板に配置されることを特徴とする検出素子。 - 請求項8又は9に記載の検出素子を複数個アレイ状に配し、
前記複数の検出素子がそれぞれ検出する検出電磁波の電界に基づいて電界分布の画像を形成することを特徴とする画像形成装置。 - 第一の半導体層の上にパターン層を形成する工程と、
熱酸化により前記パターン層の周囲にLOCOS層を形成する工程と、
前記パターン層を除去して前記第一の半導体層の表面を露出する工程と、
前記LOCOS層と接し、且つ、前記LOCOS層の一部を覆うように、前記第一の半導体層の表面とショットキー接合する第一の電極を形成する工程と、
前記第一の半導体層と接続された、前記第一の半導体層よりキャリア濃度の高い第二の半導体層の一部とオーミック接触する第二の電極を形成する工程とを少なくとも含むショットキーバリアダイオードの製造方法。 - 第一の半導体層の上にSi3N4を含むパターン層を形成する工程と、
熱酸化によりパターン層の周囲にLOCOS層を形成する工程と、
前記パターン層を除去して前記第一の半導体層の表面を露出する工程と、
第二の半導体層を、前記第一の半導体層の露出した表面に選択的にエピタキシャル成長する工程と、
前記LOCOS層と接し、且つ、前記LOCOS層の一部を覆うように、前記第二の半導体層の表面とショットキー接合する第一の電極を形成する工程と、
前記第一の半導体層とオーミック接触する第二の電極を形成する工程とを少なくとも含むショットキーバリアダイオードの製造方法。 - 前記パターン層はSi3N4を含むことを特徴とする請求項11又は12記載のショットキーバリアダイオードの製造方法。
- 請求項11〜13のいずれか1項に記載されたショットキーバリアダイオードの製造方法で製造されたショットキーバリアダイオードと、
検出電磁波の電界成分を前記第一の電極と前記第二の電極の間に誘起するためのアンテナ又は、検出信号を出力するためのトランジスタの少なくとも一方を形成する工程とを有する検出素子の製造方法。 - 請求項14に記載された検出素子で製造された検出素子を複数個アレイ状に配置する工程を有する画像形成装置の製造方法。
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US10121926B2 (en) * | 2016-08-22 | 2018-11-06 | Shahid Rajaee Teacher Training University | Graphene-based detector for W-band and terahertz radiations |
US10797137B2 (en) * | 2017-06-30 | 2020-10-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for reducing Schottky barrier height and semiconductor device with reduced Schottky barrier height |
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JPS57115875A (en) * | 1981-01-09 | 1982-07-19 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JPS5877256A (ja) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | 半導体装置の電極構造 |
JPS59155178A (ja) * | 1984-01-18 | 1984-09-04 | Hitachi Ltd | シヨツトキバリアダイオ−ドを有する半導体装置 |
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