US20170148928A1 - Schottky barrier diode and apparatus using the same - Google Patents
Schottky barrier diode and apparatus using the same Download PDFInfo
- Publication number
- US20170148928A1 US20170148928A1 US15/381,842 US201615381842A US2017148928A1 US 20170148928 A1 US20170148928 A1 US 20170148928A1 US 201615381842 A US201615381842 A US 201615381842A US 2017148928 A1 US2017148928 A1 US 2017148928A1
- Authority
- US
- United States
- Prior art keywords
- schottky
- semiconductor
- electrode
- layer
- ohmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 163
- 239000000758 substrate Substances 0.000 claims description 36
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000001514 detection method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 239000002800 charge carrier Substances 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 210000001520 comb Anatomy 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-L Sulfate Chemical compound [O-]S([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-L 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000012620 biological material Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- XKUKSGPZAADMRA-UHFFFAOYSA-N glycyl-glycyl-glycine Natural products NCC(=O)NCC(=O)NCC(O)=O XKUKSGPZAADMRA-UHFFFAOYSA-N 0.000 description 1
- 108010067216 glycyl-glycyl-glycine Proteins 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- MGFYIUFZLHCRTH-UHFFFAOYSA-N nitrilotriacetic acid Chemical compound OC(=O)CN(CC(O)=O)CC(O)=O MGFYIUFZLHCRTH-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000000123 paper Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- -1 pharmaceutical Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011896 sensitive detection Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 229910021653 sulphate ion Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/09—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/108—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the Schottky type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- aspects of the present invention relate to Schottky barrier diodes and particularly relate to a Schottky barrier diode which oscillates or detects an electromagnetic wave in a frequency band within a frequency region from a millimeter-wave band to a terahertz band (equal to or higher than 30 GHz and equal to or lower than 30 THz) (hereinafter, called a terahertz-wave) and an apparatus using the same.
- a terahertz-wave a terahertz-wave
- a frequency region of terahertz-waves has an absorption peak derived from the structure and/or state of a biological material, pharmaceutical, electronic material, and many other organic molecules.
- Terahertz-waves are highly transmissive to materials such as paper, ceramics, resins, cloth.
- imaging technologies and sensing technologies making use of such characteristics of terahertz-waves have been studied and developed. For example, their applications to safe fluoroscopic apparatuses alternative to X-ray apparatuses and in-line nondestructive inspection apparatuses in manufacturing processes are being expected.
- Well known terahertz-wave detecting devices may include thermal detectors and quantum detectors.
- a thermal detector may include a VO x microbolometer, TGS (Triglycine Sulphate) pyroelectric element, and a Golay cell using thermal expansion of gas.
- a thermal detector converts energy of an electromagnetic wave to heat and captures a change in heat electromotive force or resistance of a material due to a change in temperature to detect an electromagnetic wave. These devices may not necessarily be cooled but are slower to respond because of use of heat exchange.
- Examples of such a quantum detector may include an intrinsic semiconductor device (such as an MCT (HgCdTe) and a photoconductor) and a QWIP (Quantum Well Infrared Photodetector).
- a quantum detector captures an electromagnetic wave as a photon to detect a photovoltaic or resistance change in a semiconductor having a small band gap. Such a device is faster to respond but requires cooling because thermal energy at room temperature in the frequency region above is significant.
- a terahertz-wave detecting device using a Schottky barrier diode has been developed which is faster to respond and does not require cooling.
- This detecting device captures an electromagnetic wave as a high frequency electric signal and rectifies with a diode the high frequency electric signal received through an antenna for detection.
- Japanese Patent Laid-Open No. 09-162424 discloses a detecting device using a vertical Schottky barrier diode having two electrodes in a longitudinal direction on a substrate. The detecting device detects an approximately 28 THz electromagnetic wave (having a wavelength of 10.6 ⁇ m) from CO 2 laser.
- 60-18959 discloses a rectifier using a horizontal Schottky barrier diode having tow electrodes on a surface of a substrate.
- the rectifier includes a Schottky electrode having a guard ring at its edge to increase its reverse bias resistance.
- US Patent Application Publication No. 2007/0181909 discloses a Schottky barrier diode which detects a microwave and has a Schottky barrier having a silicon oxide at its edge to increase its reverse bias.
- a vertical Schottky barrier diode as disclosed in Japanese Patent Laid-Open No. 09-162424 uses its substrate as an earth electrode, limited types of antenna may be integrally formed.
- a semiconductor interface exposes to an element structure between two electrodes or in the vicinity of a diode on a semiconductor surface, larger leak current is generated by formation of a parasitic current path and/or larger noise may occur due to a state of the interface.
- noise may occur due to lack of an interface between a semiconductor 900 and a silicon oxide 901 .
- the disclosed device may detect microwaves at partial frequency bands, but its application to highly sensitive detection of terahertz-waves has been difficult.
- a Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer.
- the Schottky junction region and the LOCOS layer are in contact.
- a Schottky barrier diode In a Schottky barrier diode according to an aspect of the present invention, a LOCOS layer and a first semiconductor layer and/or a Schottky junction region are arranged in contact. This may prevent exposure of a semiconductor surface and/or interface and reduce its defect density in the vicinity of the Schottky junction region. Therefore, reduction of noise (such as 1/f noise or RTS noise) involved in carrier capture and/or emission may be expected. For that reason, a Schottky barrier diode according to an aspect of the present invention is more highly sensitive, compared with those in the past.
- FIGS. 1A and 1B illustrate a diode in one embodiment of the present invention.
- FIG. 2 illustrates a correspondence between a configuration of a diode in one embodiment of the present invention and a configuration of an equivalent circuit element.
- FIGS. 3A and 3B illustrate variation examples of a diode.
- FIGS. 4A to 4F illustrate a manufacturing method for a diode in one embodiment of the present invention.
- FIGS. 5A and 5B illustrate a detecting device in one embodiment of the present invention.
- FIGS. 6A and 6B illustrate a detecting device in one embodiment of the present invention.
- FIG. 7 illustrates an image forming apparatus having a detecting device in one embodiment of the present invention.
- FIG. 8 illustrates a detecting device in one embodiment of the present invention.
- FIG. 9 illustrates a diode of a background technology.
- a Schottky barrier diode 100 of this embodiment includes a substrate 101 , a first semiconductor layer 102 formed thereon, a second semiconductor layer 103 having a higher carrier concentration than the first semiconductor layer 102 , and a LOCOS layer 105 .
- the Schottky barrier diode 100 further includes a first electrode 106 (hereinafter, called a Schottky electrode) Schottky-connected to a part of the first semiconductor layer 102 and a second electrode (hereinafter, called an ohmic electrode) 107 which forms an ohmic contact with the second semiconductor layer 103 .
- a first electrode 106 hereinafter, called a Schottky electrode
- a second electrode hereinafter, called an ohmic electrode
- An interface where the first semiconductor layer 102 and the Schottky electrode 106 are in contact has a Schottky junction region 104 .
- the Schottky junction region may sometimes refer to an interface only or may refer to an area having a predetermined thickness from an interface or an area including an interface having a predetermined thickness.
- the first semiconductor layer 102 typically has an area having an order of 10 15 to 10 17 cm ⁇ 3 charge carriers in the vicinity of a contact surface with the Schottky electrode 106 .
- the first semiconductor layer 102 and the second semiconductor layer 103 are in contact with each other and are mechanically and electrically coupled.
- the second semiconductor layer 103 is a structure allowing the first semiconductor layer 102 and the ohmic electrode 107 to be coupled for lower ohmic resistance. According to this embodiment, the second semiconductor layer 103 has a higher carrier concentration achieved by doping impurities to a part of a semiconductor in the first semiconductor layer.
- the LOCOS layer 105 is a silicon oxide film formed by a LOCOS (Local Oxidation of Silicon) method.
- a silicon layer including the first semiconductor layer 102 is locally thermally oxidized with a pattern layer containing Si 3 N 4 having a slightly larger area than the Schottky junction region 104 as a mask to form a mesa structure 108 that is a part of the LOCOS layer 105 and first semiconductor layer 104 .
- the LOCOS layer 105 surrounds the Schottky junction region 104 and mesa structure 108 .
- the LOCOS layer 105 , Schottky junction region 104 , mesa structure 108 and first semiconductor layer 102 are in contact with each other.
- the size of a pattern containing Si 3 N 4 which functions as a mask for a LOCOS process and determines the area of the Schottky junction region 104 may be designed from a general thermal oxidation theory as proposed by Deal-Grove. That is, briefly, a pattern extending to both sides by approximately 0.5 times of the thickness of the LOCOS layer 105 to be formed is used for a desirable pattern dimension. For example, in order to acquire a 0.5 ⁇ m thick LOCOS layer 105 and a 0.5 ⁇ m diameter Schottky junction region 104 , thermal oxidation may be performed with an approximately 1 ⁇ m pattern containing Si 3 N 4 as a mask.
- the rate and/or result of oxidization may slightly change in accordance with a condition for the thermal oxidation and/or a configuration of a surrounding film.
- controlling a film deposition condition properly by setting the conditions several times allows as highly precise as an nm order of design and/or production of the size of Schottky junction region 104 and the structure of the mesa structure 108 .
- the area of the Schottky junction region 104 depends on the type and/or characteristic of a semiconductor used therein, it may be set in a range of 0.1 ⁇ m 2 to 10 ⁇ m 2 to raise the cutoff frequency from millimeter waves to a terahertz band.
- the Schottky electrode 106 is a layer in contact with the first semiconductor layer 102 and contains a metal material which forms the Schottky junction region 104 .
- the Schottky electrode 106 is in contact with the LOCOS layer 105 and is arranged so as to cover at least a part of the LOCOS layer 105 .
- the Schottky electrode 106 is arranged so as to cover the entire surface of the Schottky junction region 104 and a partial surface of the LOCOS layer 105 .
- cover here refers to a structure in which the Schottky electrode 106 arranged on a surface of the Schottky junction region 104 is also partially superposed on the LOCOS layer 105 arranged in contact with a circumference of the Schottky junction region 104 .
- the ohmic electrode 107 is a layer containing a metal material in ohmic-contact with the second semiconductor layer 103 .
- the ohmic electrode 107 is in contact with the LOCOS layer 105 and is arranged so as to cover at least a part of the LOCOS layer 105 .
- the ohmic electrode 107 is arranged so as to cover the entire exposed surface of the second semiconductor layer 103 and a partial surface of the LOCOS layer 105 .
- the term “cover” here refers to a structure in which the ohmic electrode 107 arranged on an exposed surface of the second semiconductor layer 103 is partially superposed on the LOCOS layer 104 arranged in contact with a circumference of an exposed surface of the second semiconductor layer 103 .
- the Schottky barrier diode 100 in which the Schottky electrode 106 , Schottky junction region 104 , first semiconductor layer 102 , second semiconductor layer 103 , and ohmic electrode 107 are electrically coupled in order.
- the Schottky barrier diode 100 has a horizontal configuration including the two electrodes 106 and 107 on one same semiconductor surface (that is, a surface of the substrate 101 including the semiconductor layers 102 and 103 and the LOCOS layer 105 ).
- the LOCOS layer 105 is arranged between two electrodes of the Schottky electrode 106 and ohmic electrode 107 on its surface so that a semiconductor surface between the two electrodes may not be exposed.
- current input to the Schottky electrode 106 is injected to the mesa structure 108 through the Schottky junction region 104 by avoiding the area including the LOCOS layer 105 that is an insulator and the substrate 101 .
- the current passes through the first semiconductor layer 102 region between the LOCOS layer 105 and the substrate 101 , is injected to the second semiconductor layer 103 having a high carrier concentration and is output to the ohmic electrode 107 .
- an outermost surface of a semiconductor has many surface levels due to incomplete bonding because of crystal discontinuity and/or impurities adhered to the surface.
- the surface levels may be formed due to an interface between a semiconductor and air or other materials a defect or impurities formed on a semiconductor surface during a manufacturing process, for example. It has been well known that the surface levels cause noise such as 1/f noise and RTS noise due to a what-is-called carrier capture or emission process. Therefore, configurations in the past have a problem that noise occurs in a diode due to a semiconductor interface exposed between two electrodes on a surface, a semiconductor interface exposed to a side of a mesa structure formed by etching, or a damage layer due to a process, for example.
- the LOCOS layer 105 are arranged in contact with the first semiconductor layer 102 and Schottky junction region 104 . This may eliminate the semiconductor surface exposed between two electrodes, which may reduce noise occurring in the Schottky barrier diode 100 .
- An interface between silicon and silicon thermal oxide has been well known as having a lower defect density than an interface between silicon and a silicon oxide layer formed thereon by a sol-gel method.
- a configuration of the present invention has a low defect density Si/SiO 2 interface formed between the first semiconductor 102 and the LOCOS layer 105 in the vicinity of the Schottky junction region 104 and mesa structure 108 . Therefore, noise due to surface levels and/or defects may be reduced.
- the mesa structure 108 is configured by actively using a local distortion caused by silicon thermal oxide according to the present invention. Thus, the mobility of electrons in a semiconductor may be controlled to adjust its cutoff frequency.
- FIGS. 3A and 3B illustrate variation examples of this embodiment.
- the Schottky barrier diode 100 illustrated in FIG. 3A has on the substrate 101 the second semiconductor layer 103 having a higher carrier concentration and the first semiconductor 102 having a lower carrier concentration in this order.
- the LOCOS layer 105 is formed by local thermal oxidation of a silicon layer including the first semiconductor layer 102 and the second semiconductor layer 103 .
- the LOCOS layer 105 is oxidized to a sufficient thickness to reach at least the second semiconductor layer 105 .
- the first semiconductor layer 102 is doped so as to typically have an order of 10 15 to 10 17 cm ⁇ 3 charge carriers so that the Schottky junction region 104 may be formed on an interface in contact with the Schottky electrode 106 .
- the second semiconductor layer 103 is doped typically to an order of 10 18 cm 3 or more charge carriers so that it may be coupled with the ohmic electrode 107 by ohmic contact.
- the configuration except for the part is the same as the example above. This configuration may lower the resistances (corresponding to Rm and Rb in FIG. 2 ) of the mesa structure 108 and the second semiconductor layer 103 under the LOCOS layer 105 , which is effective for detection of a high frequency of the Schottky barrier diode 100 , particularly, detection of a terahertz-wave.
- the Schottky barrier diode 100 illustrated in FIG. 3B has on the substrate 101 the second semiconductor layer 103 having a higher carrier concentration and the first semiconductor 102 having a lower carrier concentration connected to the second semiconductor layer 103 .
- the LOCOS layer 105 is formed by local thermal oxidation on a semiconductor including the second semiconductor layer 103 .
- the first semiconductor layer 102 includes a semiconductor formed by selective epitaxial growth with a LOCOS layer as a mask on a surface of the exposed second semiconductor layer 103 surrounded by the LOCOS layer 105 .
- a contact surface of the first semiconductor layer 102 and Schottky electrode 106 has the Schottky junction region 104 .
- the first semiconductor layer 102 includes a semiconductor layer doped so as to typically have an order of 10 15 to 10 17 cm ⁇ 3 charge carriers in the vicinity of a contact interface with the Schottky electrode 106 .
- the second semiconductor layer 103 is doped so as to typically have an order to 10 19 cm ⁇ 3 or more charge carriers, like the example in FIG. 3A and is coupled to the ohmic electrode 107 by ohmic contact.
- the configuration except for this part is the same as the one in FIG. 3A .
- This configuration allows arbitrary selection of a semiconductor material having different band gap, lattice constant, mobility, dopant concentration and so on for the first semiconductor layer 102 , as will be described below, which is effective for achieving a high frequency and/or highly sensitive Schottky barrier diode 100 .
- the Schottky barrier diode 100 according to the present invention may be produced by a manufacturing method including at least the following steps (A) to (E) as illustrated in FIG. 4 :
- a metal film forming the Schottky electrode 106 is formed over the LOCOS layer 105 such that the minute Schottky junction region 104 may be formed on the exposed part of the semiconductor layer 102 with high accuracy.
- the area of the exposed part of the semiconductor layer 102 may be controlled by controlling a dimension of the pattern layer 409 containing Si 3 N 4 as known in a LOCOS process in the past.
- the exposed part of the semiconductor layer 102 (or the uppermost surface of the mesa structure 108 ) and the accuracy of alignment with the Schottky electrode 106 do not depend on the area of the Schottky junction region 104 . Therefore, the structure may be formed on the Schottky junction region having a minute area of 1 ⁇ m 2 or smaller with high accuracy and high yield, contributing to lower capacitance due to a reduced area of the Schottky joint region.
- the Schottky electrode 106 and the ohmic electrode 107 are allowed to be integrally formed more closely to the diodes and more closely to each other, which may inhibit parasitic series resistance (corresponding to Rs).
- a Schottky barrier diode produced by the manufacturing method has a reduced RC delay and therefore is expected to operate highly sensitively to terahertz-waves having a higher frequency than those in the past.
- high accuracy of alignment is not necessary, an improvement of productivity due to an improved yield and reduced number of steps may be expected.
- a Schottky barrier diode, like the Schottky barrier diode 100 , of the present invention may be produced by a manufacturing method including a step (F) after the step (C) and including a step (G) instead of the step (D) as follows:
- This manufacturing method may apply a technology of forming the semiconductor layer 412 by selective epitaxial growth only on an exposed surface of the semiconductor layer 102 surrounded by the LOCOS layer 105 with the LOCOS layer 105 as a mask.
- Si having a different characteristic such as a carrier concentration and/or a semiconductor material such as SiGe, GaAs, InGaAs, and AlAs, excluding Si may be selected, from which a highly sensitive and high frequency Schottky diode may be expected.
- carriers may be selected arbitrarily.
- selection of electrons with high mobility may reduce its delay time and increase its cutoff frequency.
- its mobility depends on a material of a semiconductor.
- Si-based material is used as the semiconductor, a common Si process including a LOCOS method is applicable thereto.
- the structure of the present invention may be produced more easily.
- amplifiers such as a MOSFET in CMOS and an HBT in BiCMOS to be integrally formed on one substrate.
- a selective epitaxial growth technology or an ELT (Epitaxial Layer Transfer) technology allows selection of a SiGe-based, GaAs-based, InP-based (containing InGaAs), InAs-based, or InSb-based semiconductor. Selecting a material with carriers having high mobility for the second semiconductor 102 may raise its cutoff frequency.
- a highly sensitive Schottky barrier diode may be provided in which a leak current fed to an exposed semiconductor interface may be inhibited and noise occurring when carriers are trapped by the interface may be reduced.
- a high frequency Schottky barrier diode with an RC delay inhibited may be provided.
- a Schottky barrier diode of the present invention may be used to provide an electromagnetic wave detecting device that is high sensitive to a high frequency region from a millimeter-wave band to a terahertz band (30 GHz or higher and 30 THz or lower) and an apparatus using it.
- a detecting device 500 according to a second embodiment will be described with reference to FIGS. 5A and 5B .
- This embodiment is a variation example of the first embodiment.
- This embodiment illustrated in FIG. 5A is different from the first embodiment in that the semiconductor layers 102 and 103 are separated by the substrate 101 and a dielectric substance 520 in an island-shape.
- the Schottky electrode 106 and ohmic electrode 107 and the first semiconductor layer 102 and second semiconductor layer 103 are arranged to have island shapes on the semiconductor substrate 101 .
- Antennas 109 and 110 that are conductive layers are connected to the Schottky electrode 106 and ohmic electrode 107 , respectively.
- the other configuration is the same as the first embodiment, and the LOCOS layer 105 that is a characteristic of the present invention is in contact with a circumference of the Schottky junction region 104 .
- a detecting device has one diode formed in an island shape.
- an island 523 When such an island 523 is sufficiently smaller than a wavelength of an electromagnetic wave to be detected, it may be approximate as a lumped constant element.
- the island 523 may be produced in approximately several ⁇ m and may function as a detecting device for a range from a millimeter-wave band to a terahertz band.
- the entire region excluding the sufficiently small semiconductor layers 102 and 103 , electrodes 106 and 107 , Schottky junction region 104 , and LOCOS layer 105 is a dielectric substance containing air, and its field (electric field) is easily controllable through the antennas 109 and 110 .
- the antennas 109 and 110 to be integrally formed may be a resonant dipole antenna or a slot antenna or a wide-band log-periodic antenna.
- Many types of balanced antenna are available and may be used as a detecting device.
- a transmission line may be provided in a part of the antennas 109 and 110 .
- an existing microwave technology may be used such as impedance matching between a diode and an antenna.
- the substrate 101 may behave as a dielectric substance at a frequency band to be detected and have a low free carrier absorption and may be a semi-insulating GaAs or InP substrate or an FZ—Si substrate having a higher resistivity.
- a CZ (MCZ)—Si substrate having a resistivity of 20 ⁇ cm or higher may be used.
- the dielectric substance 520 has a low dielectric loss in a frequency band to be detected and may be an oxide film of SiO or a nitride film of SiN.
- a resin of BCB Benzocyclobutene
- FIG. 5B illustrates a variation example of this embodiment.
- the ohmic electrode 107 is used as an earth conductor pattern, instead of use of an earth electrode as a substrate as in Japanese Patent Laid-Open No. 09-162424.
- the substrate 101 may have either high or low resistivity.
- the earth electrode includes the electrode 107 being an earth conductor pattern and the second semiconductor layer 103 .
- the antenna 109 functioning as an upper electrode may be formed on the earth electrode to easily configure an unbalanced antenna.
- a resonant patch antenna may be integrally formed.
- the detecting device 500 has a Schottky barrier diode for an application of detecting an electromagnetic wave.
- the substrate 101 is an Si substrate. Against growth by FZ method, a material of a high resistivity of 1 k ⁇ cm is used. Electrons are used as carriers, an n-type carrier concentration of the first semiconductor layer 102 is 5 ⁇ 10 17 cm ⁇ 3 , and its thickness is 100 nm. An n-type carrier concentration of the second semiconductor layer 103 is 5 ⁇ 10 19 cm ⁇ 3 , and its thickness is 400 nm.
- the LOCOS layer 105 is a silicon oxide film acquired by thermal oxidation of a part of the semiconductor layers 102 and 103 by using a pattern containing Si 3 N 4 as a mask, and its thickness is 500 nm.
- the LOCOS layer 105 surrounds the Schottky junction region 104 and mesa structure 108 .
- the LOCOS layer 105 and the Schottky junction region 104 , mesa structure 108 , first semiconductor layer 102 and second semiconductor layer 103 are in contact with each other.
- the ohmic electrode 107 is arranged immediately above the second semiconductor layer 103 having a higher n-type carrier concentration and is in ohmic contact with the second semiconductor layer 103 .
- a 200-nm thick AlSi material is used as its electrode material.
- the Schottky electrode 106 is in contact with a surface of the first semiconductor layer 102 having a lower carrier concentration, and the interface has a Schottky junction region 104 .
- a 200-nm thick Ti material is used as its electrode material.
- the materials and thicknesses of the Schottky electrode 106 and ohmic electrode 107 are not limited to those described above.
- a metallic material used for a general ohmic electrode and/or a Schottky electrode of a semiconductor to be used may be formed in an arbitrary thickness. Thus, a diode to which the present invention is applicable is configured.
- an island 723 including the semiconductor layers 102 and 103 , electrodes 106 and 107 , Schottky junction region 104 , and LOCOS layer 105 is formed.
- the size of the island may be approximately 50 ⁇ m 2 or smaller for detection of an electromagnetic wave in a frequency band of 0.5 THz or higher to 3 THz or lower. In this example, each side was designed to be approximately 7 ⁇ m long.
- the island 723 is embedded in SiO 2 720 , and the Schottky electrode 106 and ohmic electrode 107 are coupled with the antennas 109 and 110 made of metal such as Ti/Al through contact holes.
- a contact part between the Schottky electrode 106 and the first semiconductor layer 102 that is, the Schottky junction region 104 is designed to have a diameter of 0.6 ⁇ m, and the distance between the Schottky electrode 106 and the ohmic electrode 107 was designed to be 1 ⁇ m such that the cutoff frequency of an RC low pass filter may be approximately 3 THz.
- a log-periodic antenna illustrated in FIG. 6 is used as an example of an integrated antenna having two electrodes in a diode structure as output ports in this example.
- Each of the antennas 109 and 110 was designed such that a radius to an outer edge may be 250 ⁇ m, a radius to the innermost edge may be 10 ⁇ m, the number of combs of the log periodic antenna for a frequency range from 0.7 GHz may be 9, and the angles of the combs may be 45 degrees. Simulating this structure was simulated by using a high frequency entire electromagnetic simulator HFSS v1 2 (manufactured by Ansoft Corporation), it was found that an electromagnetic wave in a wide frequency band of 0.2 to 2.5 THz could be detected.
- HFSS v1 2 manufactured by Ansoft Corporation
- a detecting device including a Schottky barrier diode and antennas for inducing an electric-field component of a detected electromagnetic wave between the Schottky electrode 106 and the ohmic electrode 107 , wherein the Schottky electrode 106 and the ohmic electrode 107 are output ports of the antennas.
- Detection may include, reading of detected current with a current measuring unit, not illustrated, through lines 724 and 725 , for example.
- a voltage applying unit not illustrated, may apply a bias voltage to the read lines 724 and 725 to set an operating point voltage of the diode.
- a diode having a high sensitivity may be acquired by biasing approximately to 0 V in this example.
- An optimum bias voltage in this case depends on an electrode material of the Schottky electrode 106 .
- the bias voltage may be approximately 0 V for an electrode material having a lower work function, such as Ti or may be a forward bias of a range of approximately 0.3 to 0.5 V for an electrode material having a higher work function, such as Pt or Pd.
- the detecting device in this example is produced by a manufacturing method including steps (1) to (8) below.
- the manufacturing method will be described with reference to FIGS. 4A to 4F and FIG. 6 .
- the semiconductor layers 102 and 103 which are epitaxially grown layers are integrated on the Si substrate 101 .
- a CVD method, an MBE method or the like may be applicable to the crystal growth.
- a 30-nm pad oxide film (corresponding to the film 410 in FIG. 4A ) is formed by a thermal oxidation method.
- a Si 3 N 4 layer 100-nm thick is formed on the surface by an LPCVD (Low Pressure Chemical Vapor Deposition) method.
- a resist pattern (not illustrated) is formed on a Si 3 N 4 pattern formed region (corresponding to the pattern layer 409 in FIG. 4A ) through a photolithography process using a stepper.
- the resist pattern is a circular pattern having a diameter of 1.1 ⁇ m arranged at a position having a central axis matched with a central axis of the Schottky junction region 104 such that the diameter of the Schottky junction region 104 may be equal to 0.6 ⁇ m.
- the resist pattern is used as a mask to remove the Si 3 N 4 layer on the substrate by an ICP-RIE (Inductive Coupled Plasma Reactive Ion Etching) method using CF 4 (not illustrated). Then, the resist is removed by using asking and sulfuric acid/hydrogen peroxide mixture (corresponding to FIG. 4A ).
- the Si 3 N 4 layer is used as a mask to form the LOCOS layer 105 of silicon thermal oxide having a thickness of 500 nm by pyrogenic thermal oxidation at 1100° C. with mixed gas of H 2 and O 2 (corresponding to FIG. 4B ).
- the Si 3 N 4 and pad oxide film are etched by an RIE (Reactive Ion Etching) method and immersion to buffered HF solution, for example, whereby a surface of the first semiconductor layer 102 is exposed (corresponding to FIG. 4C ).
- RIE Reactive Ion Etching
- a resist pattern is formed by lithography using a stepper to remove a region for forming the Schottky electrode 106 .
- electron beam evaporation is used to form a 200-nm thick Ti layer.
- the Ti layer excluding the Schottky electrode 106 region is removed by a lift-off method using an organic solvent, and the Schottky electrode 106 is formed.
- a lift-off is used in the electrode forming step in order to avoid occurrence of a defect due to a process damage by resurfacing on the first semiconductor layer 102 on which the Schottky junction region 104 is to be formed.
- a lift-off method by electron beam evaporation is used in this example, an embodiment of the present invention is not limited thereto. For example, sputtering or dry etching may be used for the formation.
- Contact holes for forming the electrode 107 are formed in a part of the LOCOS layer 105 by using lithography using a stepper and RIE. After that, a resist pattern is formed by lithography using a stepper to remove a region on which the ohmic electrode 107 is to be formed. Then, a 200-nm thick AlSi layer is formed by electron beam evaporation. Next, the AlSi layer excluding the region for the ohmic electrode 107 is removed by a lift-off method using an organic solvent to form the ohmic electrode 107 (corresponding to FIG. 4D ). Though a lift-off method using electron beam evaporation is used in this example, an embodiment of the present invention is not limited thereto. For example, sputtering or dry etching may be used for the formation.
- Patterning by lithography using a stepper is performed such that a resist may remain in a region where the island 723 is to be formed. Then, the resist is used as a mask to etch a part of the LOCOS layer 105 by an RIE using mixed gas of CF 4 and O 2 . Then, a silicon layer being the second semiconductor layer 103 is etched by an RIE using halogen-based gas such as SF 6 and Cl 2 . In this case, etching to the substrate 101 is performed for electrical insulation from adjacent devices. The resist mask is removed by asking and immersion to an organic solvent.
- An SiO x layer to be the insulating layer 720 is formed by a plasma CVD (Chemical Vapor Deposition) method.
- a plasma CVD Chemical Vapor Deposition
- the following step may be performed. That is, after an SiO x layer is buried, the SiO x layer may be flattened by a CMP (Chemical Mechanical Polishing) step.
- a resist is patterned to remove the SiO x layer on the electrodes 106 and 107 , and through-hole etching is performed thereon.
- the RIE method using CF 4 above may be used for the etching.
- a 10-nm/200-nm thick Ti/Al film is formed by sputtering.
- a resist is patterned to form the log-periodic antennas 109 and 110 , and an unnecessary part of the Ti/Al film is etched by the RIE method or a combination of an ECR (electron cyclotron resonance) etching method with a high plasma density and halogen-based gas. After that, the resist is removed.
- ECR electron cyclotron resonance
- the detecting device 500 completes.
- the device manufacturing method in this example may be a selective epitaxial growth technology, as illustrated in FIGS. 4E and 4F .
- a step is performed in which a 10-nm Si layer or 10-nm SiGe layer with different doping levels epitaxially grows with the LOCOS layer 105 as a mask, for example, by selectively using an MBE method only for a surface of the first semiconductor layer 102 .
- the other steps of this manufacturing process may be substantially same as (1) to (8) above. Performing the step above allows selection of Si or a semiconductor material excluding Si with different characteristics such as carrier concentrations and band gaps, achieving a further highly sensitive and high frequency detecting device.
- a plurality of arrays of the detecting device may be arranged to configure an image forming apparatus including an image forming unit which forms an image of an electric-field distribution on the basis of electric fields of electromagnetic waves detected by the plurality of detecting devices.
- FIG. 7 discloses an example of an image forming apparatus having 3 ⁇ 3 focal plane arrays of the detecting devices 500 with 600 ⁇ m pitches.
- the image forming apparatus may support different polarized waves.
- the image forming apparatus may support different frequencies.
- FIG. 8 illustrates a variation example of the first example.
- the detecting device may be used for an application for amplifying a detection signal.
- a detection signal may be amplified by a MOSFET 830 integrally formed on the Si substrate 101 .
- the MOSFET 830 in this example includes a gate electrode 831 , a gate insulating layer 832 , a source electrode 833 , a drain electrode 834 , and an ion implanted region 835 .
- the Schottky electrode 106 is connected to a wire 836 such that a detection signal may be input to the gate electrode 831 of the MOSFET 830 .
- a resistance of the Schottky barrier diode or a resistor not illustrated inputs converted rectified voltage to the MOSFET 830 .
- a detecting device may be configured which includes a Schottky barrier diode and a transistor configured to output a detection signal, wherein the Schottky barrier diode and the transistor are arranged on one substrate.
- a detecting device may be produced by performing local oxidation on the LOCOS layer 105 by the steps (1) and (2) according to the first example and then forming a part corresponding to the island 823 by the same steps disclosed in the first example. After that, a standard CMOS process may be used to produce the MOSFET 830 on the Si substrate 101 . Then, an electrode structure may be integrally formed by the steps (3) to (8) according to the first example.
- a configuration having a detecting device and a MOSFET as an amplifier for the detecting device on a same substrate may be produced by a standard CMOS process at low costs. The shorter the wire 836 is, the less noise is mixed into a detection signal. Therefore, integrating them on one substrate is also effective for a lower NF.
- an image forming apparatus including an image forming unit which forms an image of an electric-field distribution on the basis of electric fields of electromagnetic waves detected by a plurality of highly dense detecting devices.
- a Schottky barrier diode of the present invention may be used as a part of a detecting device, but it may be used as a part of an oscillating element on general principles.
- An oscillating element and/or a detecting device including a Schottky barrier diode of the present invention may be applied industrially to a test apparatus which examines quality of a sample of medical supplies, for example.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.
Description
- This application is a Continuation of U.S. application Ser. No. 13/925,071, filed Jun. 24, 2013, which claims the benefit of Japanese Patent Application No. 2012-144320 filed Jun. 27, 2012, which are hereby incorporated by reference herein in their entireties.
- Technical Field
- Aspects of the present invention relate to Schottky barrier diodes and particularly relate to a Schottky barrier diode which oscillates or detects an electromagnetic wave in a frequency band within a frequency region from a millimeter-wave band to a terahertz band (equal to or higher than 30 GHz and equal to or lower than 30 THz) (hereinafter, called a terahertz-wave) and an apparatus using the same.
- Description of the Related Art
- A frequency region of terahertz-waves has an absorption peak derived from the structure and/or state of a biological material, pharmaceutical, electronic material, and many other organic molecules. Terahertz-waves are highly transmissive to materials such as paper, ceramics, resins, cloth. In recent years, imaging technologies and sensing technologies making use of such characteristics of terahertz-waves have been studied and developed. For example, their applications to safe fluoroscopic apparatuses alternative to X-ray apparatuses and in-line nondestructive inspection apparatuses in manufacturing processes are being expected.
- Well known terahertz-wave detecting devices may include thermal detectors and quantum detectors. Examples of such a thermal detector may include a VOx microbolometer, TGS (Triglycine Sulphate) pyroelectric element, and a Golay cell using thermal expansion of gas. A thermal detector converts energy of an electromagnetic wave to heat and captures a change in heat electromotive force or resistance of a material due to a change in temperature to detect an electromagnetic wave. These devices may not necessarily be cooled but are slower to respond because of use of heat exchange. Examples of such a quantum detector may include an intrinsic semiconductor device (such as an MCT (HgCdTe) and a photoconductor) and a QWIP (Quantum Well Infrared Photodetector). A quantum detector captures an electromagnetic wave as a photon to detect a photovoltaic or resistance change in a semiconductor having a small band gap. Such a device is faster to respond but requires cooling because thermal energy at room temperature in the frequency region above is significant.
- A terahertz-wave detecting device using a Schottky barrier diode has been developed which is faster to respond and does not require cooling. This detecting device captures an electromagnetic wave as a high frequency electric signal and rectifies with a diode the high frequency electric signal received through an antenna for detection. For example, Japanese Patent Laid-Open No. 09-162424 discloses a detecting device using a vertical Schottky barrier diode having two electrodes in a longitudinal direction on a substrate. The detecting device detects an approximately 28 THz electromagnetic wave (having a wavelength of 10.6 μm) from CO2 laser. Japanese Patent Laid-Open No. 60-18959 discloses a rectifier using a horizontal Schottky barrier diode having tow electrodes on a surface of a substrate. The rectifier includes a Schottky electrode having a guard ring at its edge to increase its reverse bias resistance. US Patent Application Publication No. 2007/0181909 discloses a Schottky barrier diode which detects a microwave and has a Schottky barrier having a silicon oxide at its edge to increase its reverse bias.
- However, since a vertical Schottky barrier diode as disclosed in Japanese Patent Laid-Open No. 09-162424 uses its substrate as an earth electrode, limited types of antenna may be integrally formed. In such a horizontal device in the past as disclosed in Japanese Patent Laid-Open No. 60-18959, a semiconductor interface exposes to an element structure between two electrodes or in the vicinity of a diode on a semiconductor surface, larger leak current is generated by formation of a parasitic current path and/or larger noise may occur due to a state of the interface.
- In a structure (
FIG. 9 ) disclosed in US Patent Application Publication No. 2007/0181909, noise may occur due to lack of an interface between asemiconductor 900 and asilicon oxide 901. The disclosed device may detect microwaves at partial frequency bands, but its application to highly sensitive detection of terahertz-waves has been difficult. - According to an aspect of the present invention, a Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.
- In a Schottky barrier diode according to an aspect of the present invention, a LOCOS layer and a first semiconductor layer and/or a Schottky junction region are arranged in contact. This may prevent exposure of a semiconductor surface and/or interface and reduce its defect density in the vicinity of the Schottky junction region. Therefore, reduction of noise (such as 1/f noise or RTS noise) involved in carrier capture and/or emission may be expected. For that reason, a Schottky barrier diode according to an aspect of the present invention is more highly sensitive, compared with those in the past.
- Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
-
FIGS. 1A and 1B illustrate a diode in one embodiment of the present invention. -
FIG. 2 illustrates a correspondence between a configuration of a diode in one embodiment of the present invention and a configuration of an equivalent circuit element. -
FIGS. 3A and 3B illustrate variation examples of a diode. -
FIGS. 4A to 4F illustrate a manufacturing method for a diode in one embodiment of the present invention. -
FIGS. 5A and 5B illustrate a detecting device in one embodiment of the present invention. -
FIGS. 6A and 6B illustrate a detecting device in one embodiment of the present invention. -
FIG. 7 illustrates an image forming apparatus having a detecting device in one embodiment of the present invention. -
FIG. 8 illustrates a detecting device in one embodiment of the present invention. -
FIG. 9 illustrates a diode of a background technology. - Embodiments or examples of the present invention will be described below with reference to drawings.
- A Schottky barrier diode according to a first embodiment will be described with reference to
FIGS. 1A and 1B andFIG. 2 . As illustrated inFIGS. 1A and 1B andFIG. 2 , a Schottkybarrier diode 100 of this embodiment includes asubstrate 101, afirst semiconductor layer 102 formed thereon, asecond semiconductor layer 103 having a higher carrier concentration than thefirst semiconductor layer 102, and aLOCOS layer 105. The Schottkybarrier diode 100 further includes a first electrode 106 (hereinafter, called a Schottky electrode) Schottky-connected to a part of thefirst semiconductor layer 102 and a second electrode (hereinafter, called an ohmic electrode) 107 which forms an ohmic contact with thesecond semiconductor layer 103. - An interface where the
first semiconductor layer 102 and the Schottkyelectrode 106 are in contact has a Schottkyjunction region 104. The Schottky junction region may sometimes refer to an interface only or may refer to an area having a predetermined thickness from an interface or an area including an interface having a predetermined thickness. In order to provide the Schottkyjunction region 104 in an interface in contact with the Schottkyelectrode 106, thefirst semiconductor layer 102 typically has an area having an order of 1015 to 1017 cm−3 charge carriers in the vicinity of a contact surface with theSchottky electrode 106. Thefirst semiconductor layer 102 and thesecond semiconductor layer 103 are in contact with each other and are mechanically and electrically coupled. Thesecond semiconductor layer 103 is a structure allowing thefirst semiconductor layer 102 and theohmic electrode 107 to be coupled for lower ohmic resistance. According to this embodiment, thesecond semiconductor layer 103 has a higher carrier concentration achieved by doping impurities to a part of a semiconductor in the first semiconductor layer. - The
LOCOS layer 105 is a silicon oxide film formed by a LOCOS (Local Oxidation of Silicon) method. According to this embodiment, a silicon layer including thefirst semiconductor layer 102 is locally thermally oxidized with a pattern layer containing Si3N4 having a slightly larger area than theSchottky junction region 104 as a mask to form amesa structure 108 that is a part of theLOCOS layer 105 andfirst semiconductor layer 104. TheLOCOS layer 105 surrounds theSchottky junction region 104 andmesa structure 108. TheLOCOS layer 105,Schottky junction region 104,mesa structure 108 andfirst semiconductor layer 102 are in contact with each other. - Here, the size of a pattern containing Si3N4 which functions as a mask for a LOCOS process and determines the area of the
Schottky junction region 104 may be designed from a general thermal oxidation theory as proposed by Deal-Grove. That is, briefly, a pattern extending to both sides by approximately 0.5 times of the thickness of theLOCOS layer 105 to be formed is used for a desirable pattern dimension. For example, in order to acquire a 0.5 μmthick LOCOS layer 105 and a 0.5 μm diameterSchottky junction region 104, thermal oxidation may be performed with an approximately 1 μm pattern containing Si3N4 as a mask. In reality, the rate and/or result of oxidization may slightly change in accordance with a condition for the thermal oxidation and/or a configuration of a surrounding film. However, controlling a film deposition condition properly by setting the conditions several times allows as highly precise as an nm order of design and/or production of the size ofSchottky junction region 104 and the structure of themesa structure 108. Here, though the area of theSchottky junction region 104 depends on the type and/or characteristic of a semiconductor used therein, it may be set in a range of 0.1 μm2 to 10 μm2 to raise the cutoff frequency from millimeter waves to a terahertz band. - The
Schottky electrode 106 is a layer in contact with thefirst semiconductor layer 102 and contains a metal material which forms theSchottky junction region 104. TheSchottky electrode 106 is in contact with theLOCOS layer 105 and is arranged so as to cover at least a part of theLOCOS layer 105. According to this embodiment, theSchottky electrode 106 is arranged so as to cover the entire surface of theSchottky junction region 104 and a partial surface of theLOCOS layer 105. The term “cover” here refers to a structure in which theSchottky electrode 106 arranged on a surface of theSchottky junction region 104 is also partially superposed on theLOCOS layer 105 arranged in contact with a circumference of theSchottky junction region 104. - The
ohmic electrode 107 is a layer containing a metal material in ohmic-contact with thesecond semiconductor layer 103. Theohmic electrode 107 is in contact with theLOCOS layer 105 and is arranged so as to cover at least a part of theLOCOS layer 105. According to this embodiment, theohmic electrode 107 is arranged so as to cover the entire exposed surface of thesecond semiconductor layer 103 and a partial surface of theLOCOS layer 105. The term “cover” here refers to a structure in which theohmic electrode 107 arranged on an exposed surface of thesecond semiconductor layer 103 is partially superposed on theLOCOS layer 104 arranged in contact with a circumference of an exposed surface of thesecond semiconductor layer 103. - Configuring as described above provides the
Schottky barrier diode 100 in which theSchottky electrode 106,Schottky junction region 104,first semiconductor layer 102,second semiconductor layer 103, andohmic electrode 107 are electrically coupled in order. TheSchottky barrier diode 100 has a horizontal configuration including the twoelectrodes substrate 101 including the semiconductor layers 102 and 103 and the LOCOS layer 105). - In the horizontal
Schottky barrier diode 100 disclosed in the present invention, theLOCOS layer 105 is arranged between two electrodes of theSchottky electrode 106 andohmic electrode 107 on its surface so that a semiconductor surface between the two electrodes may not be exposed. Thus, current input to theSchottky electrode 106 is injected to themesa structure 108 through theSchottky junction region 104 by avoiding the area including theLOCOS layer 105 that is an insulator and thesubstrate 101. After that, the current passes through thefirst semiconductor layer 102 region between theLOCOS layer 105 and thesubstrate 101, is injected to thesecond semiconductor layer 103 having a high carrier concentration and is output to theohmic electrode 107. In this manner, current form theSchottky electrode 106 dominantly flows through an electric circuit including the Schottky diode (SBD), a resistance (Rm) of themesa structure 108, a resistance (Rb) of thefirst semiconductor layer 102 under theLOCOS layer 105, as illustrated inFIG. 2 . As a result, this configuration of the present invention allows parasitic leak current flowing through a semiconductor interface exposed between two electrodes in a horizontal Schottky barrier diode, which has been a problem in the past, to bypass the interface, and the leak current may significantly be inhibited. - Generally, an outermost surface of a semiconductor has many surface levels due to incomplete bonding because of crystal discontinuity and/or impurities adhered to the surface. The surface levels may be formed due to an interface between a semiconductor and air or other materials a defect or impurities formed on a semiconductor surface during a manufacturing process, for example. It has been well known that the surface levels cause noise such as 1/f noise and RTS noise due to a what-is-called carrier capture or emission process. Therefore, configurations in the past have a problem that noise occurs in a diode due to a semiconductor interface exposed between two electrodes on a surface, a semiconductor interface exposed to a side of a mesa structure formed by etching, or a damage layer due to a process, for example.
- In the
Schottky barrier diode 100 of the present invention, theLOCOS layer 105 are arranged in contact with thefirst semiconductor layer 102 andSchottky junction region 104. This may eliminate the semiconductor surface exposed between two electrodes, which may reduce noise occurring in theSchottky barrier diode 100. An interface between silicon and silicon thermal oxide has been well known as having a lower defect density than an interface between silicon and a silicon oxide layer formed thereon by a sol-gel method. Thus, a configuration of the present invention has a low defect density Si/SiO2 interface formed between thefirst semiconductor 102 and theLOCOS layer 105 in the vicinity of theSchottky junction region 104 andmesa structure 108. Therefore, noise due to surface levels and/or defects may be reduced. Themesa structure 108 is configured by actively using a local distortion caused by silicon thermal oxide according to the present invention. Thus, the mobility of electrons in a semiconductor may be controlled to adjust its cutoff frequency. -
FIGS. 3A and 3B illustrate variation examples of this embodiment. TheSchottky barrier diode 100 illustrated inFIG. 3A has on thesubstrate 101 thesecond semiconductor layer 103 having a higher carrier concentration and thefirst semiconductor 102 having a lower carrier concentration in this order. TheLOCOS layer 105 is formed by local thermal oxidation of a silicon layer including thefirst semiconductor layer 102 and thesecond semiconductor layer 103. TheLOCOS layer 105 is oxidized to a sufficient thickness to reach at least thesecond semiconductor layer 105. Thefirst semiconductor layer 102 is doped so as to typically have an order of 1015 to 1017 cm−3 charge carriers so that theSchottky junction region 104 may be formed on an interface in contact with theSchottky electrode 106. Thesecond semiconductor layer 103 is doped typically to an order of 1018 cm3 or more charge carriers so that it may be coupled with theohmic electrode 107 by ohmic contact. The configuration except for the part is the same as the example above. This configuration may lower the resistances (corresponding to Rm and Rb inFIG. 2 ) of themesa structure 108 and thesecond semiconductor layer 103 under theLOCOS layer 105, which is effective for detection of a high frequency of theSchottky barrier diode 100, particularly, detection of a terahertz-wave. - The
Schottky barrier diode 100 illustrated inFIG. 3B has on thesubstrate 101 thesecond semiconductor layer 103 having a higher carrier concentration and thefirst semiconductor 102 having a lower carrier concentration connected to thesecond semiconductor layer 103. TheLOCOS layer 105 is formed by local thermal oxidation on a semiconductor including thesecond semiconductor layer 103. Thefirst semiconductor layer 102 includes a semiconductor formed by selective epitaxial growth with a LOCOS layer as a mask on a surface of the exposedsecond semiconductor layer 103 surrounded by theLOCOS layer 105. A contact surface of thefirst semiconductor layer 102 andSchottky electrode 106 has theSchottky junction region 104. Thefirst semiconductor layer 102 includes a semiconductor layer doped so as to typically have an order of 1015 to 1017 cm−3 charge carriers in the vicinity of a contact interface with theSchottky electrode 106. Thesecond semiconductor layer 103 is doped so as to typically have an order to 1019 cm−3 or more charge carriers, like the example inFIG. 3A and is coupled to theohmic electrode 107 by ohmic contact. The configuration except for this part is the same as the one inFIG. 3A . This configuration allows arbitrary selection of a semiconductor material having different band gap, lattice constant, mobility, dopant concentration and so on for thefirst semiconductor layer 102, as will be described below, which is effective for achieving a high frequency and/or highly sensitiveSchottky barrier diode 100. - The
Schottky barrier diode 100 according to the present invention may be produced by a manufacturing method including at least the following steps (A) to (E) as illustrated inFIG. 4 : - (A) forming a
pattern layer 409 containing Si3N4 through apad oxide film 410 on a top surface of thesemiconductor layer 102 on the substrate 101 (FIG. 4A ); - (B) thermally oxidizing the
semiconductor layer 102 by a thermal oxidation method and forming themesa structure 108 around thepattern layer 409 and under theLOCOS layer 105 and the pattern layer 409 (FIG. 4B ); - (C) removing the
pattern layer 409 to expose a surface of the semiconductor layer 102 (FIG. 4C ); - (D) forming the
Schottky electrode 106 in Schottky contact with thesemiconductor layer 102 such that theSchottky electrode 106 may be in contact with theLOCOS layer 105 and overlaps with the LOCOS layer 105 (FIG. 4D ); and - (E) forming the
ohmic electrode 107 in ohmic contact with a part of the semiconductor layer 102 (FIG. 4D ). According to this manufacturing method, a metal film forming theSchottky electrode 106 is formed over theLOCOS layer 105 such that the minuteSchottky junction region 104 may be formed on the exposed part of thesemiconductor layer 102 with high accuracy. The area of the exposed part of thesemiconductor layer 102 may be controlled by controlling a dimension of thepattern layer 409 containing Si3N4 as known in a LOCOS process in the past. - Through those steps above, the exposed part of the semiconductor layer 102 (or the uppermost surface of the mesa structure 108) and the accuracy of alignment with the
Schottky electrode 106 do not depend on the area of theSchottky junction region 104. Therefore, the structure may be formed on the Schottky junction region having a minute area of 1 μm2 or smaller with high accuracy and high yield, contributing to lower capacitance due to a reduced area of the Schottky joint region. TheSchottky electrode 106 and theohmic electrode 107 are allowed to be integrally formed more closely to the diodes and more closely to each other, which may inhibit parasitic series resistance (corresponding to Rs). Thus, a Schottky barrier diode produced by the manufacturing method has a reduced RC delay and therefore is expected to operate highly sensitively to terahertz-waves having a higher frequency than those in the past. In addition, because high accuracy of alignment is not necessary, an improvement of productivity due to an improved yield and reduced number of steps may be expected. - A Schottky barrier diode, like the
Schottky barrier diode 100, of the present invention may be produced by a manufacturing method including a step (F) after the step (C) and including a step (G) instead of the step (D) as follows: - (F) forming the
semiconductor layer 412 by selective epitaxial growth on the exposed surface of thesemiconductor layer 102 surrounded by the LOCOS layer 105 (FIG. 4E ), where thesemiconductor layer 412 may contain a layer having a lower carrier concentration than thesemiconductor layer 102, and theLOCOS layer 105 functions as a mask for the selective epitaxial growth; and - (G) forming the
Schottky electrode 106 in Schottky contact with a surface of thesemiconductor layer 412 such that it may be in contact with theLOCOS layer 105 and overlap with the LOCOS layer 105 (FIG. 4F ). - This manufacturing method may apply a technology of forming the
semiconductor layer 412 by selective epitaxial growth only on an exposed surface of thesemiconductor layer 102 surrounded by theLOCOS layer 105 with theLOCOS layer 105 as a mask. Thus, for thesemiconductor layer 412, Si having a different characteristic such as a carrier concentration and/or a semiconductor material such as SiGe, GaAs, InGaAs, and AlAs, excluding Si may be selected, from which a highly sensitive and high frequency Schottky diode may be expected. - According to this embodiment, carriers may be selected arbitrarily. However, selection of electrons with high mobility may reduce its delay time and increase its cutoff frequency. Furthermore, its mobility depends on a material of a semiconductor. For example, when an Si-based material is used as the semiconductor, a common Si process including a LOCOS method is applicable thereto. Thus, the structure of the present invention may be produced more easily. In addition, it allows amplifiers such as a MOSFET in CMOS and an HBT in BiCMOS to be integrally formed on one substrate. On the other hand, use of a selective epitaxial growth technology or an ELT (Epitaxial Layer Transfer) technology allows selection of a SiGe-based, GaAs-based, InP-based (containing InGaAs), InAs-based, or InSb-based semiconductor. Selecting a material with carriers having high mobility for the
second semiconductor 102 may raise its cutoff frequency. - According to the present invention, a highly sensitive Schottky barrier diode may be provided in which a leak current fed to an exposed semiconductor interface may be inhibited and noise occurring when carriers are trapped by the interface may be reduced. Furthermore, according to the present invention, a high frequency Schottky barrier diode with an RC delay inhibited may be provided. Still further, a Schottky barrier diode of the present invention may be used to provide an electromagnetic wave detecting device that is high sensitive to a high frequency region from a millimeter-wave band to a terahertz band (30 GHz or higher and 30 THz or lower) and an apparatus using it.
- A detecting
device 500 according to a second embodiment will be described with reference toFIGS. 5A and 5B . This embodiment is a variation example of the first embodiment. This embodiment illustrated inFIG. 5A is different from the first embodiment in that the semiconductor layers 102 and 103 are separated by thesubstrate 101 and adielectric substance 520 in an island-shape. In other words, theSchottky electrode 106 andohmic electrode 107 and thefirst semiconductor layer 102 andsecond semiconductor layer 103 are arranged to have island shapes on thesemiconductor substrate 101.Antennas Schottky electrode 106 andohmic electrode 107, respectively. The other configuration is the same as the first embodiment, and theLOCOS layer 105 that is a characteristic of the present invention is in contact with a circumference of theSchottky junction region 104. - According to this embodiment, a detecting device has one diode formed in an island shape. When such an
island 523 is sufficiently smaller than a wavelength of an electromagnetic wave to be detected, it may be approximate as a lumped constant element. Theisland 523 may be produced in approximately several μm and may function as a detecting device for a range from a millimeter-wave band to a terahertz band. Thus, the entire region excluding the sufficientlysmall semiconductor layers electrodes Schottky junction region 104, andLOCOS layer 105 is a dielectric substance containing air, and its field (electric field) is easily controllable through theantennas antennas antennas - The
substrate 101 may behave as a dielectric substance at a frequency band to be detected and have a low free carrier absorption and may be a semi-insulating GaAs or InP substrate or an FZ—Si substrate having a higher resistivity. For a 1 THz or higher frequency region, a CZ (MCZ)—Si substrate having a resistivity of 20 Ωcm or higher may be used. Thedielectric substance 520 has a low dielectric loss in a frequency band to be detected and may be an oxide film of SiO or a nitride film of SiN. For a terahertz band, a resin of BCB (Benzocyclobutene) may be used. - Apparently, an unbalanced antenna may be integrally formed thereto.
FIG. 5B illustrates a variation example of this embodiment. Theohmic electrode 107 is used as an earth conductor pattern, instead of use of an earth electrode as a substrate as in Japanese Patent Laid-Open No. 09-162424. In this case, thesubstrate 101 may have either high or low resistivity. In either case, the earth electrode includes theelectrode 107 being an earth conductor pattern and thesecond semiconductor layer 103. Theantenna 109 functioning as an upper electrode may be formed on the earth electrode to easily configure an unbalanced antenna. For example, a resonant patch antenna may be integrally formed. - More specific diodes and detecting devices will be described with reference to examples.
- A specific detecting
device 500 according to the second embodiment will be described withFIG. 6 . According to this example, the detecting device has a Schottky barrier diode for an application of detecting an electromagnetic wave. - In this example, the
substrate 101 is an Si substrate. Against growth by FZ method, a material of a high resistivity of 1 kΩcm is used. Electrons are used as carriers, an n-type carrier concentration of thefirst semiconductor layer 102 is 5×1017 cm−3, and its thickness is 100 nm. An n-type carrier concentration of thesecond semiconductor layer 103 is 5×1019 cm−3, and its thickness is 400 nm. TheLOCOS layer 105 is a silicon oxide film acquired by thermal oxidation of a part of the semiconductor layers 102 and 103 by using a pattern containing Si3N4 as a mask, and its thickness is 500 nm. TheLOCOS layer 105 surrounds theSchottky junction region 104 andmesa structure 108. TheLOCOS layer 105 and theSchottky junction region 104,mesa structure 108,first semiconductor layer 102 andsecond semiconductor layer 103 are in contact with each other. - The
ohmic electrode 107 is arranged immediately above thesecond semiconductor layer 103 having a higher n-type carrier concentration and is in ohmic contact with thesecond semiconductor layer 103. In this example, a 200-nm thick AlSi material is used as its electrode material. TheSchottky electrode 106 is in contact with a surface of thefirst semiconductor layer 102 having a lower carrier concentration, and the interface has aSchottky junction region 104. In this example, a 200-nm thick Ti material is used as its electrode material. The materials and thicknesses of theSchottky electrode 106 andohmic electrode 107 are not limited to those described above. A metallic material used for a general ohmic electrode and/or a Schottky electrode of a semiconductor to be used may be formed in an arbitrary thickness. Thus, a diode to which the present invention is applicable is configured. - In order to configure the detecting
device 500 to which the present invention is applicable, anisland 723 including the semiconductor layers 102 and 103,electrodes Schottky junction region 104, andLOCOS layer 105 is formed. The size of the island may be approximately 50 μm2 or smaller for detection of an electromagnetic wave in a frequency band of 0.5 THz or higher to 3 THz or lower. In this example, each side was designed to be approximately 7 μm long. Theisland 723 is embedded inSiO 2 720, and theSchottky electrode 106 andohmic electrode 107 are coupled with theantennas Schottky electrode 106 and thefirst semiconductor layer 102, that is, theSchottky junction region 104 is designed to have a diameter of 0.6 μm, and the distance between theSchottky electrode 106 and theohmic electrode 107 was designed to be 1 μm such that the cutoff frequency of an RC low pass filter may be approximately 3 THz. - A log-periodic antenna illustrated in
FIG. 6 is used as an example of an integrated antenna having two electrodes in a diode structure as output ports in this example. Each of theantennas Schottky electrode 106 and theohmic electrode 107, wherein theSchottky electrode 106 and theohmic electrode 107 are output ports of the antennas. - Detection may include, reading of detected current with a current measuring unit, not illustrated, through
lines lines Schottky electrode 106. For a structure in this example, the bias voltage may be approximately 0 V for an electrode material having a lower work function, such as Ti or may be a forward bias of a range of approximately 0.3 to 0.5 V for an electrode material having a higher work function, such as Pt or Pd. - The detecting device in this example is produced by a manufacturing method including steps (1) to (8) below. The manufacturing method will be described with reference to
FIGS. 4A to 4F andFIG. 6 . - (1) The semiconductor layers 102 and 103 which are epitaxially grown layers are integrated on the
Si substrate 101. A CVD method, an MBE method or the like may be applicable to the crystal growth. After that, in order to protect the silicon surface, a 30-nm pad oxide film (corresponding to thefilm 410 inFIG. 4A ) is formed by a thermal oxidation method. Then, a Si3N4 layer 100-nm thick is formed on the surface by an LPCVD (Low Pressure Chemical Vapor Deposition) method. Then, a resist pattern (not illustrated) is formed on a Si3N4 pattern formed region (corresponding to thepattern layer 409 inFIG. 4A ) through a photolithography process using a stepper. The resist pattern is a circular pattern having a diameter of 1.1 μm arranged at a position having a central axis matched with a central axis of theSchottky junction region 104 such that the diameter of theSchottky junction region 104 may be equal to 0.6 μm. Next, the resist pattern is used as a mask to remove the Si3N4 layer on the substrate by an ICP-RIE (Inductive Coupled Plasma Reactive Ion Etching) method using CF4 (not illustrated). Then, the resist is removed by using asking and sulfuric acid/hydrogen peroxide mixture (corresponding toFIG. 4A ). - (2) The Si3N4 layer is used as a mask to form the
LOCOS layer 105 of silicon thermal oxide having a thickness of 500 nm by pyrogenic thermal oxidation at 1100° C. with mixed gas of H2 and O2 (corresponding toFIG. 4B ). - (3) The Si3N4 and pad oxide film are etched by an RIE (Reactive Ion Etching) method and immersion to buffered HF solution, for example, whereby a surface of the
first semiconductor layer 102 is exposed (corresponding toFIG. 4C ). - (4) A resist pattern is formed by lithography using a stepper to remove a region for forming the
Schottky electrode 106. After that, electron beam evaporation is used to form a 200-nm thick Ti layer. Next, the Ti layer excluding theSchottky electrode 106 region is removed by a lift-off method using an organic solvent, and theSchottky electrode 106 is formed. Here, a lift-off is used in the electrode forming step in order to avoid occurrence of a defect due to a process damage by resurfacing on thefirst semiconductor layer 102 on which theSchottky junction region 104 is to be formed. Though a lift-off method by electron beam evaporation is used in this example, an embodiment of the present invention is not limited thereto. For example, sputtering or dry etching may be used for the formation. - (5) Contact holes for forming the
electrode 107 are formed in a part of theLOCOS layer 105 by using lithography using a stepper and RIE. After that, a resist pattern is formed by lithography using a stepper to remove a region on which theohmic electrode 107 is to be formed. Then, a 200-nm thick AlSi layer is formed by electron beam evaporation. Next, the AlSi layer excluding the region for theohmic electrode 107 is removed by a lift-off method using an organic solvent to form the ohmic electrode 107 (corresponding toFIG. 4D ). Though a lift-off method using electron beam evaporation is used in this example, an embodiment of the present invention is not limited thereto. For example, sputtering or dry etching may be used for the formation. - (6) Patterning by lithography using a stepper is performed such that a resist may remain in a region where the
island 723 is to be formed. Then, the resist is used as a mask to etch a part of theLOCOS layer 105 by an RIE using mixed gas of CF4 and O2. Then, a silicon layer being thesecond semiconductor layer 103 is etched by an RIE using halogen-based gas such as SF6 and Cl2. In this case, etching to thesubstrate 101 is performed for electrical insulation from adjacent devices. The resist mask is removed by asking and immersion to an organic solvent. - (7) An SiOx layer to be the insulating
layer 720 is formed by a plasma CVD (Chemical Vapor Deposition) method. Here, when theisland 723 of the substrate and concaves and convexes of theelectrodes - (8) A resist is patterned to remove the SiOx layer on the
electrodes periodic antennas - By performing the steps above, the detecting
device 500 completes. - The device manufacturing method in this example may be a selective epitaxial growth technology, as illustrated in
FIGS. 4E and 4F . In this case, after the step (3) (state inFIG. 4C ), a step is performed in which a 10-nm Si layer or 10-nm SiGe layer with different doping levels epitaxially grows with theLOCOS layer 105 as a mask, for example, by selectively using an MBE method only for a surface of thefirst semiconductor layer 102. The other steps of this manufacturing process may be substantially same as (1) to (8) above. Performing the step above allows selection of Si or a semiconductor material excluding Si with different characteristics such as carrier concentrations and band gaps, achieving a further highly sensitive and high frequency detecting device. - A plurality of arrays of the detecting device according to this example may be arranged to configure an image forming apparatus including an image forming unit which forms an image of an electric-field distribution on the basis of electric fields of electromagnetic waves detected by the plurality of detecting devices. For example,
FIG. 7 discloses an example of an image forming apparatus having 3×3 focal plane arrays of the detectingdevices 500 with 600 μm pitches. In this case, when the detecting devices are arranged with antennas in different directions, the image forming apparatus may support different polarized waves. When the detecting devices are arranged with resonant antennas for different frequencies, the image forming apparatus may support different frequencies. - A detecting
device 500 according to a second example will be described with reference toFIG. 8 .FIG. 8 illustrates a variation example of the first example. In this example, the detecting device may be used for an application for amplifying a detection signal. A detection signal may be amplified by aMOSFET 830 integrally formed on theSi substrate 101. - The
MOSFET 830 in this example includes agate electrode 831, agate insulating layer 832, asource electrode 833, adrain electrode 834, and an ion implantedregion 835. In order to amplify a detection signal, theSchottky electrode 106 is connected to awire 836 such that a detection signal may be input to thegate electrode 831 of theMOSFET 830. A resistance of the Schottky barrier diode or a resistor not illustrated inputs converted rectified voltage to theMOSFET 830. In this case, either well-known source connection of theohmic electrode 107 to thesource electrode 833 or well-known source follower by connecting theohmic electrode 107 to thedrain electrode 834 may be selected in accordance with the purpose. A detection signal amplified from the MOSFET is output from an electrode that is connected to neitherSchottky electrode 106 norohmic electrode 107. In this manner, a detecting device may be configured which includes a Schottky barrier diode and a transistor configured to output a detection signal, wherein the Schottky barrier diode and the transistor are arranged on one substrate. - A detecting device according to this example may be produced by performing local oxidation on the
LOCOS layer 105 by the steps (1) and (2) according to the first example and then forming a part corresponding to theisland 823 by the same steps disclosed in the first example. After that, a standard CMOS process may be used to produce theMOSFET 830 on theSi substrate 101. Then, an electrode structure may be integrally formed by the steps (3) to (8) according to the first example. A configuration having a detecting device and a MOSFET as an amplifier for the detecting device on a same substrate may be produced by a standard CMOS process at low costs. The shorter thewire 836 is, the less noise is mixed into a detection signal. Therefore, integrating them on one substrate is also effective for a lower NF. - Also in this case, connecting a detecting device of this example to matrix wiring to use a MOSFET as a switching element for an active matrix results in the following apparatus. That is, there may be provided an image forming apparatus including an image forming unit which forms an image of an electric-field distribution on the basis of electric fields of electromagnetic waves detected by a plurality of highly dense detecting devices.
- A Schottky barrier diode of the present invention may be used as a part of a detecting device, but it may be used as a part of an oscillating element on general principles. An oscillating element and/or a detecting device including a Schottky barrier diode of the present invention may be applied industrially to a test apparatus which examines quality of a sample of medical supplies, for example.
- While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
Claims (17)
1. A Schottky barrier diode comprising:
a semiconductor;
a Schottky electrode which is Schottky-contacted with the semiconductor;
an ohmic electrode which is ohmic-contacted with the semiconductor; and
a LOCOS layer which is arranged in contact with the semiconductor, between a Schottky junction region where the Schottky electrode is Schottky-contacted with the semiconductor and an ohmic junction region where the ohmic electrode is ohmic-contacted with the semiconductor,
wherein the Schottky junction region and the ohmic junction region are arranged at different positions in a direction in which the semiconductor is in line with the LOCOS layer.
2. The Schottky barrier diode according to claim 1 , wherein the Schottky junction region is arranged at a position higher than the ohmic junction region.
3. The Schottky barrier diode according to claim 1 , wherein the LOCOS layer is arranged so as to surround the Schottky junction region.
4. The Schottky barrier diode according to claim 1 , wherein the LOCOS layer is in contact with a circumference of the Schottky junction region.
5. The Schottky barrier diode according to claim 1 , wherein a part of the Schottky electrode is arranged on an upper part of the LOCOS layer.
6. The Schottky barrier diode according to claim 1 , wherein a part of the ohmic electrode is arranged on an upper part of the LOCOS layer.
7. The Schottky barrier diode according to claim 1 , wherein the semiconductor comprises a first semiconductor which is Schottky-connected with the first electrode and a second semiconductor which is ohmic-connected with the second electrode.
8. A Schottky barrier diode comprising:
a substrate;
a semiconductor arranged on the substrate;
a Schottky electrode arranged on the semiconductor and Schottky-connected to the semiconductor;
an ohmic electrode arranged on the semiconductor and ohmic-connected to the semiconductor; and
a LOCOS layer arranged in contact with the semiconductor, between a Schottky junction region and an ohmic junction region of the semiconductor,
wherein the Schottky junction region and the ohmic junction region are arranged at different positions in a direction perpendicular to a substrate face of the substrate.
9. The Schottky barrier diode according to claim 8 , wherein the Schottky junction region is arranged at a position apart from the substrate face than the ohmic junction region in the direction perpendicular to the substrate face of the semiconductor.
10. A detecting device comprising:
the Schottky barrier diode according to claim 1 ; and
an antenna.
11. A detecting device comprising:
the Schottky barrier diode according to claim 1 ; and
a transistor.
12. A Schottky barrier diode manufacturing method, comprising:
forming a pattern layer on a semiconductor;
forming a LOCOS layer around the pattern layer by thermal oxidation;
removing the pattern layer to expose a surface of the semiconductor;
forming a first electrode to form a Schottky junction with the surface of the semiconductor, the first electrode being in contact with the LOCOS layer and covering a part of the LOCOS layer; and
forming a second electrode to form an ohmic junction with the surface of the semiconductor,
wherein in the forming the second electrode, the second electrode is formed in such a manner that the surface of the semiconductor and the second electrode are ohmic-contacted at a position different from a region where the Schottky junction, in a direction in which the semiconductor is in line with the LOCOS layer.
13. The Schottky barrier diode manufacturing method according to claim 12 , wherein in the forming the second electrode, the second electrode is formed in such a manner that the surface of the semiconductor and the second electrode are ohmic-connected at a position lower than the region where the Schottky junction is formed with the first electrode, in the direction in which the semiconductor is in line with the LOCOS layer.
14. A Schottky barrier diode comprising:
a semiconductor;
a Schottky electrode which is Schottky-connected to the semiconductor;
an ohmic electrode which is ohmic-connected to the semiconductor; and
an insulating layer which is arranged in contact with the semiconductor, between a Schottky junction region where the Schottky electrode is Schottky-contacted with the semiconductor and an ohmic junction region where the ohmic electrode is ohmic-contacted with the semiconductor,
wherein the Schottky junction region and the ohmic junction region are arranged at different positions in a direction in which the semiconductor is in line with the LOCOS layer.
15. The Schottky barrier diode according to claim 13 , wherein the Schottky junction region is arranged at a position higher than the ohmic junction region in the direction in which the semiconductor is in line with the LOCOS layer.
16. The Schottky barrier diode according to claim 13 , wherein the insulating layer is arranged to surround the Schottky junction region.
17. The Schottky barrier diode according to claim 13 , wherein the insulating layer is in contact with a circumference of the Schottky junction region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/381,842 US20170148928A1 (en) | 2012-06-27 | 2016-12-16 | Schottky barrier diode and apparatus using the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012144320A JP6095284B2 (en) | 2012-06-27 | 2012-06-27 | Schottky barrier diode and device using the same |
JP2012-144320 | 2012-06-27 | ||
US13/925,071 US9553211B2 (en) | 2012-06-27 | 2013-06-24 | Schottky barrier diode and apparatus using the same |
US15/381,842 US20170148928A1 (en) | 2012-06-27 | 2016-12-16 | Schottky barrier diode and apparatus using the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/925,071 Continuation US9553211B2 (en) | 2012-06-27 | 2013-06-24 | Schottky barrier diode and apparatus using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170148928A1 true US20170148928A1 (en) | 2017-05-25 |
Family
ID=49777117
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/925,071 Active 2033-11-15 US9553211B2 (en) | 2012-06-27 | 2013-06-24 | Schottky barrier diode and apparatus using the same |
US15/381,842 Abandoned US20170148928A1 (en) | 2012-06-27 | 2016-12-16 | Schottky barrier diode and apparatus using the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/925,071 Active 2033-11-15 US9553211B2 (en) | 2012-06-27 | 2013-06-24 | Schottky barrier diode and apparatus using the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US9553211B2 (en) |
JP (1) | JP6095284B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180053871A1 (en) * | 2016-08-22 | 2018-02-22 | Mina Amirmazlaghani | Graphene-based detector for w-band and terahertz radiations |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104241401B (en) * | 2014-09-09 | 2016-06-01 | 华中科技大学 | Based on Schottky type Terahertz multispectrum signal detector and the preparation method of Meta Materials |
US10297704B2 (en) * | 2016-03-15 | 2019-05-21 | Teledyne Scientific & Imaging, Llc | Low noise detectors for astronomy |
US10797137B2 (en) * | 2017-06-30 | 2020-10-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for reducing Schottky barrier height and semiconductor device with reduced Schottky barrier height |
KR20200096805A (en) | 2017-12-04 | 2020-08-13 | 그린 어라이즈 엘티디 | Converter for converting electromagnetic waves into direct current |
CN109616513B (en) * | 2019-01-23 | 2023-06-27 | 山东科技大学 | Terahertz Schottky diode for improving current crowding effect based on multi-split anode |
CN113594291A (en) * | 2021-07-22 | 2021-11-02 | 山东大学 | Method for realizing infrared photoelectric detection by regulating metal/semiconductor Schottky junction through pyroelectric effect of polar semiconductor |
CN113745815B (en) * | 2021-08-27 | 2022-05-20 | 西安交通大学 | Cooperative combined antenna working in terahertz wave band |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57115875A (en) * | 1981-01-09 | 1982-07-19 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JPS5877256A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Electrode structure of semiconductor device |
JPS6018959A (en) | 1983-07-13 | 1985-01-31 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS59155178A (en) * | 1984-01-18 | 1984-09-04 | Hitachi Ltd | Semiconductor device with schottky barrier diode |
JPS60201666A (en) * | 1984-03-27 | 1985-10-12 | Nec Corp | Semiconductor device |
JP3251758B2 (en) | 1994-02-15 | 2002-01-28 | 株式会社東芝 | Method for manufacturing semiconductor integrated circuit device |
JP2002057350A (en) | 1994-08-30 | 2002-02-22 | Seiko Instruments Inc | Semiconductor device |
JPH09162424A (en) | 1995-12-04 | 1997-06-20 | Yokogawa Electric Corp | Antenna-coupled electric field detection photo detecting element, and its manufacture |
JP3484354B2 (en) * | 1998-09-14 | 2004-01-06 | 三菱電機株式会社 | Thermal infrared detector array and method of manufacturing the same |
JP4277496B2 (en) | 2001-11-21 | 2009-06-10 | 富士電機デバイステクノロジー株式会社 | Semiconductor device |
US7417265B2 (en) * | 2006-02-03 | 2008-08-26 | Semiconductor Components Industries, L.L.C. | Schottky diode structure with enhanced breakdown voltage and method of manufacture |
JP5506258B2 (en) * | 2008-08-06 | 2014-05-28 | キヤノン株式会社 | Rectifier element |
-
2012
- 2012-06-27 JP JP2012144320A patent/JP6095284B2/en active Active
-
2013
- 2013-06-24 US US13/925,071 patent/US9553211B2/en active Active
-
2016
- 2016-12-16 US US15/381,842 patent/US20170148928A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180053871A1 (en) * | 2016-08-22 | 2018-02-22 | Mina Amirmazlaghani | Graphene-based detector for w-band and terahertz radiations |
US10121926B2 (en) * | 2016-08-22 | 2018-11-06 | Shahid Rajaee Teacher Training University | Graphene-based detector for W-band and terahertz radiations |
Also Published As
Publication number | Publication date |
---|---|
US20140001363A1 (en) | 2014-01-02 |
JP6095284B2 (en) | 2017-03-15 |
US9553211B2 (en) | 2017-01-24 |
JP2014011175A (en) | 2014-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9553211B2 (en) | Schottky barrier diode and apparatus using the same | |
JP5506258B2 (en) | Rectifier element | |
JP5563356B2 (en) | Electromagnetic wave detection element | |
JP6214201B2 (en) | Image acquisition device | |
US8067754B2 (en) | Photoconductive device | |
JP6642769B1 (en) | Manufacturing method of electronic device using graphene | |
US10121926B2 (en) | Graphene-based detector for W-band and terahertz radiations | |
US8338200B2 (en) | Frontside-illuminated inverted quantum well infrared photodetector devices and methods of fabricating the same | |
US9349881B2 (en) | Diode element and detecting device | |
JP6141027B2 (en) | Detection element, detector, and imaging apparatus using the same | |
US8053734B2 (en) | Nano-antenna for wideband coherent conformal IR detector arrays | |
US20140145280A1 (en) | Semiconductor device and production method therefor | |
US10886323B2 (en) | Infrared detector, infrared detection device, and method of manufacturing infrared detector | |
Kazemi et al. | First THz and IR characterization of nanometer-scaled antenna-coupled InGaAs/InP Schottky-diode detectors for room temperature infrared imaging | |
Rahman et al. | Terahertz focal plane arrays employing heterostructure backward diodes integrated with folded dipole antennas | |
JP2017085184A (en) | Schottky barrier diode and device using the same | |
US9356170B2 (en) | THz distributed detectors and arrays | |
Rahman et al. | Development of terahertz focal plane array elements using Sb-based heterostructure backward diodes | |
JP2012119490A (en) | Semiconductor light-receiving element and light-receiving device having the same | |
KR102505015B1 (en) | Terahertz wave detector based on monolithic field-effect transistor-antenna device with independent performance parameters | |
Yang et al. | Embedded actives for terahertz circuit applications: Imaging array | |
JP2023160647A (en) | Antenna device and detection system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |