JP2002057350A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which four Schottky barrier diodes are combined in a bridge on a silicon substrate, with low voltage and small power consumption at a low cost, while the voltage rise in forward direction of the Schottky barrier diodes is small in the voltage-current characteristics. SOLUTION: Each Schottky barrier diode is formed in mesa, and a high resistance polysilicon, an oxide film 10 Å or less, and an intermediate transient level are formed at the Schottky junction of each Schottky barrier diode. Instead of the Schottky barrier diodes, MOS transistors is combined in its structure. A device, made up of a semiconductor device, an antenna, a power supply, and a sensor, an indicator or memory, is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used at a high frequency, in particular, a Schottky barrier diode,
The present invention relates to a set of four bridge type diodes and a method of manufacturing the same, or a semiconductor device that requires high speed operation at low voltage.

Further, the present invention attaches a tag including a memory which is a storage medium to a moving object, and when necessary, non-contactly stores information stored in the moving object by radio wave, electromagnetic induction or optical communication. The present invention relates to an electronic device that can be read and can communicate with a mobile object.

[0003]

2. Description of the Related Art Conventionally, Schottky barrier diodes are widely used in mixers, modulators, phase detectors, and the like in VHF and UHF high-frequency bands and in SHF ultra-high-frequency bands. When a metal and a semiconductor having a difference (work function) between the vacuum level and the Fermi level are different from each other, charge is redistributed to bring the Fermi level to the same level. As a result, the space charge layer (barrier) layer)
Are formed to have a rectifying characteristic. The Schottky barrier diode utilizes this characteristic. A Schottky barrier diode is superior to a PN junction diode in terms of response speed in a high frequency band, and thus is suitable for a high-speed switching circuit. Further, since the rising voltage also has a relatively small value as compared with the PN junction diode, it does not require as much input voltage as the PN junction diode.

FIG. 22 shows a conventional Schottky barrier diode.
1 shows a schematic cross-sectional view of a card. High resistance silicon with low impurity concentration
Schottky metal (203) on the control board (201),
The ohmic metal (20) is formed through the high impurity region (202).
4) are formed. Normally n-type silicon substrate
Silicon is used for the silicon epitaxial layer
Impurities are implanted to form a high impurity region (202).
0.8 × 10 impurities ¹⁷~ 2 × 10¹⁸cm^-3High in the range
Doped to a concentration.

However, this type of Schottky barrier diode is difficult to use as an integrated circuit because electrodes are present on the upper and lower surfaces of the wafer. In addition, since the resistance value of the silicon substrate is high, power consumption increases. FIG. 23 is a schematic cross-sectional view showing a conventional semiconductor device having a plurality of Schottky diodes having anode and cathode electrodes on the same surface. An n-type silicon epitaxial layer (2) is formed on a p-type silicon substrate (205) having a specific resistance of about 1000 Ω · cm.
06) is formed. Here, an n-type silicon epitaxial layer (206) is used to electrically isolate each diode.
After the other portion except the upper portion is made porous using, for example, a porous reaction, the porous portion is converted into a porous oxide film in an oxidizing atmosphere, and the p + insulating film layer is formed. (20
Function 7). This p + insulating separation layer (207)
Separates the n-type silicon epitaxial layer (206) into individual operation regions. Then, a Schottky metal (203) and an ohmic metal (204) are formed on the surface of the operation region. In addition, a high impurity region (20
2) is formed.

FIG. 26 is a plan view of a semiconductor device in which four conventional Schottky barrier diodes are combined. N between the conventional Schottky barrier diodes and the parasitic N
Since an unnecessary current flows due to the PN, the distance must be at least 200 μm. Therefore, assuming that the pad connected to each connection terminal is 100 μm square, a semiconductor device in which four Schottky barrier diodes are combined requires an area of about 600 μm square per chip.

Here, when a semiconductor device in which four Schottky barrier diodes are combined is used as the switching device, the voltage of each Schottky barrier diode is reduced by the following equation.
It is possible to suppress the voltage input is smaller forward rising voltage (hereinafter referred to as V _F) at the current characteristics, it is possible to reduce the power consumption. V _F is as small as possible is desired in the above-described Schottky barrier diode for that.

[0008] Conventionally, it picks the Schottky metal to lower the V _F of the Schottky barrier diode had been produced a small Schottky barrier diode V _F. Thus the semiconductor device that combines four conventional Schottky barrier diode selects a small Schottky metal V _F above so, the Schottky metal side anode, a Schottky barrier diode of the unit the ohmic metal side to the cathode Then, each Schottky barrier diode is insulated by a p + insulating separation layer, and four Schottky barrier diodes are formed in a bridge type using wire bonding or metal wiring as shown in a schematic connection diagram in FIG. 24 or 25. The combined semiconductor device had a chip of about 600 μm square.

When connected as shown in FIGS. 24 and 25, the circuit thus assembled operates as a rectifier, and when connected as shown in FIGS. 41 and 42, it operates as a modulator.
FIGS. 24 and 25 or FIGS. 41 and 42 are completely equivalent circuit diagrams. Conventionally, as shown in FIG. 25, when the wiring of the diode bridge circuit is assembled into a cross, the wiring always crosses at one place, so that the wiring is insulated from each other. Such a three-layer structure had to be taken.

As shown in FIG. 62, a conventional overcurrent detecting circuit is a MOS transistor 62 for detecting the voltage of a current detecting resistor 6205 connected in series to a load 6207.
The control circuit 6208 responds to the output voltage of the
206 is controlled to interrupt or limit the current.
In such a circuit, the MOS transistor 6203
The substrate was connected to the source.

A MOS transistor as shown in FIG. 70 is known as a semiconductor device suitable for low voltage and high speed operation. FIG. 70 is a structural sectional view of a MOS transistor. For example, in the case of an N-type MOS transistor, an N + -type diffusion region 7202 as a source region and an N + -type diffusion region 7203 as a drain region are provided on the surface of a P-type silicon substrate 7201. A structure in which a gate electrode 7205 is provided over a gate insulating film 7204 is provided above.

The operation of the MOS transistor is performed on the substrate 720.
1 and the drain region 7 with reference to the source region 7202.
A positive drain voltage for carrier acceleration is applied to 203,
Further, by applying a positive gate voltage to the gate electrode 7205, the source region 7202 and the drain region 72
03 is controlled by controlling the impedance. By applying the gate voltage, the surface potential φs of the channel region (substrate surface portion between the source region 7202 and the drain region 7203) is controlled by the electric field effect up to the saturation level approximately as shown in equation (1). You.

[0013]

(Equation 1) C _OX denotes a gate insulating film capacitance, the C _S depletion layer capacitance formed in the channel region, the V _G is the gate voltage. When φ _S increases due to the electric field effect, the potential barrier between the source region 7202 and the channel region decreases. This allows the source
A channel current _ID flows between the drain regions. _ID increases exponentially with respect to the gate voltage as shown in equation (2).

[0014]

(Equation 2) Here, T is absolute temperature, K is Boltzmann's constant, and q is unit charge. I _D increases approximately according to equation (2) until the gate voltage reaches a value called the threshold voltage V _TH . When the gate voltage becomes higher than the threshold voltage, the surface potential becomes almost the saturation level, and a sufficiently low impedance state is obtained. The threshold voltage, which is the gate voltage for achieving a sufficiently low impedance state, is obtained by equation (3).

[0015]

(Equation 3) Where φ _MS is the work function difference between the substrate and the gate electrode, Q ₀
Is the effective fixed electric field in the gate insulating film, φ _f is the reference energy Fermi level, and Q _B is the depletion charge on the substrate surface.

[0016]

[SUMMARY OF THE INVENTION] However, to select a Schottky metal in order to reduce the V _F was done in Schottky barrier diode as the above-mentioned conventional. For example Ti, Cr, Au, W, etc. has a degree of vacuum needs to be ultra vacuum such as manufacturing limitations during vapor deposition, it has been impossible to obtain a sufficiently low V _F at ever. In the case of gallium sulfide, the surface state density is higher than that of silicon, and it is difficult to lower the forward rise voltage. Thus be sufficiently low V _F by the selection of the Schottky metal is generally could not.

In a Schottky barrier diode semiconductor device of a set of four, it is difficult to completely insulate and isolate each element, and it is difficult to reduce the area per chip due to the insulative isolation between the elements. there were. In addition, by crossing the wiring of the diode bridge circuit of the Schottky barrier diode semiconductor device, the manufacturing process increases,
The cost was high.

An object of the present invention is to provide a structure and a manufacturing method of a Schottky barrier diode semiconductor device for solving such a conventional problem.
In the conventional overcurrent detection circuit, when operating at a low voltage, the absolute value of the threshold voltage of the MOS transistor must be reduced. However, if the absolute value of the threshold voltage is reduced, the off-leak current of the MOS transistor increases. As a result, the current consumption of the circuit increases. Conversely MO
When the absolute value of the threshold voltage is increased in order to suppress the off-leak current of the S transistor, there is a problem that the sensitivity of the MOS transistor decreases.

An object of the present invention is to provide an overcurrent detection circuit which operates at a low voltage and has high sensitivity while solving the above problems. In the case of a conventional MOS transistor, if the high impedance state and the low impedance state are set to, for example, 6 digits or more, the threshold voltage must be set higher than 0.5V. As a result, high-speed operation at a power supply voltage of 1 V or less was difficult. Further, since the current path is limited to a very thin channel region on the surface of the substrate, the increase in current per unit area is worse than that of the bipolar transistor.

An object of the present invention is to provide a semiconductor device having a low-voltage high-speed operation and a high driving capability, which has been made to solve such problems.

[0021]

Means for Solving the Problems In order to solve the above problems, the present invention takes the following means. As a first means, a semiconductor substrate provided on a supporting substrate is constituted by a plurality of electrically separated semiconductor substrates.

As a second means, a semiconductor substrate having an insulating film on a supporting substrate and a semiconductor layer formed on the insulating film (hereinafter referred to as SOI, abbreviation for Silicon on Insulator) was used. As a third means, the silicon substrate formed a Schottky junction via the high-resistance polysilicon.

As a fourth means, a Schottky junction is formed on a silicon substrate having a plurality of levels of intermediate transitions at a plurality of levels. As a fifth means, a Schottky junction was formed on high-resistance polysilicon used as a silicon substrate.

As a sixth means, an extremely thin SiO ₂ layer was formed between the silicon substrate and the high-resistance polysilicon. As a seventh means, the surface of the high-resistance polysilicon is polished and smoothed to form a Schottky junction.

As an eighth means, a bridge is formed by using a MOS transistor instead of a diode. Ninth
In order to achieve this, a structure is adopted in which a part of the wiring of the diode bridge circuit passes outside the electrode pad.

As a tenth means, a bridge is formed by using a MOS transistor in which a gate and a substrate are connected instead of a diode. 11 as a means, constituted by a control circuit for controlling the power supply circuit and a memory and reading and writing of the memory to operate at the configured rectifier circuit and a low voltage at a low MOS transistors low diode or V _T of the antenna and V _F Was made a data carrier.

[0027] As a twelfth means, is composed of an acceleration sensor capable of detecting the power supply circuit and the acceleration operating in the configured rectifier circuit and a low voltage at a low MOS transistors low diode or V _T of the antenna and V _F Data carrier. 13 as a means, antenna and V _F low diode or V _T low MOS transistors composed of a rectifier circuit and a data carrier configured in operation to the power supply circuit and a temperature sensor capable of detecting the temperature at a low voltage I made it.

As a fourteenth means, an acceleration sensor is used in which the length of one side parallel to the plane from which acceleration can be detected is 1 mm or less. As a fifteenth means, a silicon substrate has formed a Schottky junction through polysilicon which has not been ion-implanted.

As a sixteenth means, the source is connected to the high voltage supply terminal, the drain is connected to the first resistor connected to the low voltage supply terminal at the other end, the gate is connected to the high voltage supply terminal at the other end. A MOS transistor respectively connected to the second resistor, a control circuit having an input connected to a connection point between the MOS transistor and the first resistor, a connection point between the gate of the MOS transistor and the second resistor, and the other end. Is connected between the load connected to the low voltage supply terminal, and the substrate and gate of the MOS transistor are connected in the overcurrent detection circuit including the switch whose output is connected to the input of the control circuit.

The following configuration is provided as the seventeenth means. A first semiconductor region comprising a semiconductor region of the first or second conductivity type, and second and third semiconductors of the first conductivity type connected to the first semiconductor region and provided on both sides and spaced from each other In a method of operating a semiconductor device comprising a region and a gate electrode provided on a first semiconductor region with a gate insulating film interposed therebetween, carrier acceleration is performed in a third semiconductor region based on a voltage of a second semiconductor region. And a first carrier control voltage for controlling the surface potential of the first semiconductor region to the gate electrode, and further apply the entire first semiconductor region to the first semiconductor region. By applying a second carrier control voltage for controlling the potential of the second semiconductor region synchronously with the same polarity as the first carrier control voltage, the impedance between the second semiconductor region and the third semiconductor region is controlled. It was operating method of the semiconductor device.

A channel formation region comprising a semiconductor region of the first or second conductivity type; a source / drain region of the first conductivity type connected to the channel formation region and provided on both sides at an interval; In a method of operating a semiconductor device comprising a gate electrode provided on a region with a gate insulating film interposed therebetween, a voltage for accelerating carriers is applied to the drain region with reference to a voltage of a source region, and a gate electrode and An operation method of a semiconductor device in which the impedance of a channel formation region is controlled by synchronously changing a first gate electrode and a second gate voltage having the same polarity to a channel formation region.

Source / drain of a MOS transistor,
In a MOS semiconductor device in which the voltage of each region of the gate and the bias voltage of the semiconductor substrate with respect to the source voltage can be independently controlled, the channel impedance between the source and the drain is reduced during the operation of the MOS transistor, Bias voltage control means for changing the bias voltage to have the same polarity and the same phase in synchronization with the change in the voltage applied to the gate so as to increase the channel impedance during operation is provided.

Further, a semiconductor device is provided in which the bias voltage control means is a voltage dividing circuit for the gate voltage.

[0034]

The following effects can be obtained by the above means. First
By the second means, even if the high-resistance silicon substrate is thin, the physical strength is strong and excellent air isolation can be easily obtained.

[0035] it is possible to lower the V _F without changing the Schottky metal by from the third seventh means. Further, the manufacturing cost can be reduced by the fourth means. Further, by the eighth means has the function of the Schottky barrier diode semiconductor device, a semiconductor device for use in high frequency and small ring mixer V _F is obtained.

Even when the wiring of the diode bridge circuit is assembled into a cross by the ninth means, it is not necessary to form a three-layer structure of wiring, insulating film, and wiring by passing a part of the wiring outside the electrode pad. Thus, a semiconductor device having a diode bridge circuit assembled in a cross at low cost can be obtained.

According to the tenth means, a semiconductor device having a smaller V _F and a smaller diode bridge circuit can be obtained. Since the voltage loss in the rectifier circuit is smaller than in the eleventh means, and the load on the interrogator is lighter, a data carrier capable of extending the communication distance between the interrogator and the transponder can be obtained.

With the twelfth and thirteenth means, it is possible to obtain an ever-changing environment or situation such as the temperature or acceleration of a non-contact moving object. With the fourteenth means, the sensitivity of detecting the magnitude of acceleration, force, or vibration applied to the side surface of the cylindrical object can be improved.

[0039] it is possible to lower the V _F without changing the Schottky metal by a 15 means. Since the surface potential of the channel forming region of the MOS transistor is controlled by both the gate voltage and the substrate applied voltage by the sixteenth means, it is possible to efficiently change the surface potential, and to suppress the off-leak current to a low level and to overcurrent with high sensitivity. Detection can be performed.

Since the surface potential of the channel formation region is controlled by both the gate voltage and the potential applied to the channel formation region by the seventeenth means, the efficiency is increased. Further, since the surface potential can be largely changed at a low gate voltage, the impedance can be controlled from a high impedance to a low impedance at a low gate voltage. That is,
Low voltage operation becomes possible. Furthermore, a large current can flow at the same gate voltage because a large surface potential change can be brought about. Further, by applying a bias to the channel forming regions in a larger order, a higher current including a bipolar operation can be achieved.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a schematic sectional view showing a semiconductor device having a quaternary Schottky barrier diode according to a first embodiment of the present invention.

A plurality of semiconductor substrates electrically separated, for example, an n-type silicon substrate 2 as a high-resistance silicon substrate were provided on a support substrate 1 made of quartz or silicon having an insulating film formed thereon. On this n-type silicon substrate 2, a Schottky metal 3 and an ohmic metal 4 were formed via an n + -type impurity region 5 as a high impurity region.

An n + type impurity region 6 is formed on the surface opposite to the surface on which the Schottky junction is formed. By forming this n + type impurity region 6, series resistance can be reduced. In order to form the n-type silicon substrate 2 of a plurality of semiconductor substrates electrically separated on the same surface of the support substrate 1, first, a support made of quartz or silicon having an insulating film formed thereon as shown in FIG. An n-type silicon substrate 2 having an n + type impurity region 6 formed thereon is bonded to the substrate 1 by electrostatic compression or thermocompression. Then, after the n-type silicon substrate 2 was polished to an appropriate thickness, a plurality of semiconductor substrates electrically separated from each other were formed on the same support substrate by chemical etching.

FIG. 14 is a schematic cross-sectional view of a manufacturing process showing a semiconductor device having a set of four Schottky barrier diodes according to a first embodiment of the present invention. n-type silicon substrate 2
An n + -type high impurity region 6 is formed on the back surface of FIG. 14A (FIG. 14B), and n
+ -Type impurity region 5 is partially formed (FIG. 14)
(C)). Here, a support substrate 1 made of quartz or silicon on which an insulating film is formed is bonded to the back surface of the n-type silicon substrate 2 by electrostatic compression or thermocompression (FIG. 14).
(D)), making the whole substrate. Here, an insulating film 7 which can withstand etching is formed on the surface using a mask (FIG. 14).
(E)), a mesa shape is formed by anisotropic chemical etching (FIG. 14 (f)). Then, the periphery of the mesa is covered with an insulating film 7 for protection or insulation separation (FIG. 14 (g)) to prevent electric leakage. After that, the n + type impurity region 5
The insulating film on the n-type silicon substrate 2 and the insulating film on the n-type silicon substrate 2 are contact-etched (FIG. 14F).
The Schottky metal 3 is formed as an electrode on the
4 (i)).

(Embodiment 2) FIG. 2 is a schematic sectional view showing a semiconductor device having a quaternary Schottky barrier diode according to a second embodiment of the present invention. A plurality of semiconductor substrates electrically separated on the same support substrate by forming an n + -type high impurity region 5 as a high impurity region in the SOI substrate 10 and etching it to the SiO ₂ film 9 to which an etch stop is applied by chemical etching. The high resistance n-type silicon substrate 2 is provided. An insulating film 7, a Schottky metal 3 and an ohmic metal 4 are formed thereon to complete each Schottky barrier diode.

FIG. 17 is a schematic cross-sectional view showing an SOI substrate used in a semiconductor device having a quaternary Schottky barrier diode according to a second embodiment of the present invention. In the SOI shown in FIG. 17, an n + -type impurity region 6 is formed on the lower surface side of an n-type silicon substrate bonded to an upper portion of an insulating film 7, and the surface on the n + -type impurity region side and the surface on the oxide film side are bonded together. N type silicon substrate 2, n + type impurity region 6,
S having a four-layer structure of insulating film 7 and n-type silicon substrate 2
OI. By using such an SOI substrate, when forming a mesa-type Schottky barrier diode as shown in FIG. 2, an n + impurity region 6 can be formed on the bottom of the mesa, and the series resistance can be reduced. .

FIG. 15 is a schematic cross-sectional view of a manufacturing process showing a semiconductor device having a set of four Schottky barrier diodes according to a second embodiment of the present invention. S as shown in FIG.
15 (a), the n + type impurity region 5 is provided on the upper surface of the OI substrate 8 (FIG. 15 (b)), and the insulating film 7 is formed on the upper surface thereof (FIG. 15 (c)). Thereafter, the insulating film to which an etch stop is applied is etched using anisotropic chemical etching to form a mesa shape (FIG. 15D). Then, the periphery of the mesa is covered with an insulating film 7 for protection or insulation separation (FIG. 15E), thereby preventing electricity leakage. Thereafter, contact etching is performed on the insulating film on the n + -type impurity region 5 and the n-type silicon substrate 2 (FIG. 15).
(F)), an ohmic metal 4 is formed on the n + type impurity region 5 and a Schottky metal 3 is formed on the n-type silicon substrate 2 as an electrode (FIG. 15 (g)).

As described above, a Schottky quaternary set of air isolation which is superior to the conventional isolation (electrical isolation) of a porous film utilizing a porous reaction in a semiconductor substrate by a p + insulating film. Barrier diodes are easily obtained. FIG. 16 is a plan view showing a semiconductor device in which four Schottky barrier diodes of the present invention are combined. As shown in FIG. 1 or FIG. 2, since excellent isolation between the Schottky barrier diodes is achieved by air isolation, a 200 μ
There is no need to separate m, and a sufficient insulation separation is possible at 50 μm. In a semiconductor device in which four Schottky barrier diodes thus manufactured are combined, about 30 chips per chip
It was possible to manufacture a semiconductor device sufficiently insulated and separated in an area of 0 μm square, and a low-cost semiconductor device was obtained.

(Embodiment 3) FIG. 3 is a schematic sectional view showing a Schottky barrier diode according to a third embodiment of the present invention. For example, P is 1 × 10 ^{14 on the} n-type silicon substrate 1.
A high-resistance polysilicon 10 ion-implanted at a concentration of atoms / cm ² or less is formed, and a Schottky metal 3 is formed thereon.

FIG. 55 is a schematic sectional view of a Schottky barrier diode according to a third embodiment of the present invention. An electrode, which is a Schottky metal, was formed on the n-type silicon substrate 1 via polysilicon not ion-implanted. FIG. 56 is a schematic sectional view of a Schottky barrier diode according to a third embodiment of the present invention. n-type high resistance polysilicon 1
An electrode, which is a Schottky metal, was formed on polysilicon 0 through polysilicon not ion-implanted.

(Embodiment 4) FIG. 4 shows a schematic cross section of a Schottky barrier diode according to a fourth embodiment of the present invention. At the time of contact etching for forming the Schottky metal 3 on the n-type silicon substrate 1, damage is given by reactive ion etching (RIE), which is plasma etching in a gas containing fluorine atoms such as CHF ₃ , so that multiple levels can be obtained. A region having a plurality of intermediate transition levels was formed in the contact portion between the Schottky metal 3 and the n-type silicon substrate 1.

[0052] has made it possible to lower the even V _F In the manner described above. (Embodiment 5) FIG. 5 is a schematic sectional view showing a Schottky barrier diode according to a fifth embodiment of the present invention. For example, the Schottky metal 3 is directly formed on the high-resistance polysilicon 10 into which P is ion-implanted at a concentration of 1 × 10 ¹⁴ atoms / cm ² or less, and the ohmic metal 4
Formed through. The effect of this is that the manufacturing cost can be reduced by using polysilicon instead of the single crystal silicon substrate. Also it was possible to obtain a small Schottky barrier diode having V _F in this manner.

(Embodiment 6) FIG. 6 is a schematic sectional view showing a diode having an SiO ₂ film of 10 ° or less according to a sixth embodiment of the present invention. After forming a thermal oxide film on the n-type silicon substrate 2, for example, a mixed solution of hydrochloric acid and hydrogen peroxide solution is applied for 8 hours.
10% or less of SiO ₂
A layer 9 was formed, and a high-resistance polysilicon 10 and an electrode 11 were further formed thereon.

[0054] Here, when a positive potential is applied to electrode 11, V _F accumulation layer is formed by negative charge under the SiO ₂ film 9 becomes the same as lower, negative potential to the electrode 11 inversion layer is formed by the positive charge under the case took SiO ₂ film 9, a depletion layer is formed, a small diode having V _F obtained in particular according easily the depletion layer extends in the high frequency.

Polysilicon is formed by a CVD method (chemical vapor deposition) under reduced pressure, and its surface has irregularities. Furthermore V _F in where the surface is polished to smooth
And the leakage current can be reduced. In the above description, an n-type silicon substrate has been described as an example of the high-resistance silicon substrate.

Further, any of the diodes according to the second to sixth embodiments of the present invention can be used as a four-piece Schottky barrier diode semiconductor device. (Embodiment 7) FIG. 9 shows an NMO according to a seventh embodiment of the present invention.
In a schematic cross-sectional view showing a semiconductor device in which four S transistors were combined, a p-type well 15 was formed in an n-type silicon substrate 2 and a source region 12 and a drain region 13 were formed, whereby a more excellent semiconductor device was obtained.

(Embodiment 8) FIG. 10 is a schematic sectional view showing a semiconductor device according to an eighth embodiment of the present invention in which four NMOS transistors are combined. First, an n-type silicon substrate 2 was epitaxially grown on the support substrate 1, and a source region 12 and a drain region 13 were formed on the upper surface of the n-type silicon substrate 2 that was epitaxially grown. Then, a gate electrode was formed on the n-type silicon substrate 2 via an insulating film.

(Embodiment 9) FIG. 11 is a schematic sectional view showing a semiconductor device according to a ninth embodiment of the present invention in which four NMOS transistors are combined. A high-resistance polysilicon 10 was formed on the support substrate 1 to form a source region 12 and a drain region 13 respectively. In each of FIGS. 10 and 11, a semiconductor device combining four excellent NMOS transistors was obtained. Polysilicon is CVD under reduced pressure
(Chemical vapor deposition method), but this surface has irregularities. Therefore, a more excellent result was obtained by polishing and smoothing the surface.

The semiconductor device in which four NMOS transistors according to the eighth or ninth embodiment shown in FIG. 10 or FIG. 11 are combined provides a plurality of semiconductor substrates in which each NMOS transistor is electrically separated on the same support substrate. Therefore, excellent insulation separation can be achieved by air damping.

(Embodiment 10) FIG. 12 shows a tenth embodiment of the present invention.
Four NMOS transistors of the embodiment are combined.
The threshold voltage of a semiconductor device is depletion
It is a characteristic view which shows a transistor. Here, the MOS tiger
The current flowing between the source and drain of the transistor (I_D)But
Potential difference between gate and source at 1 nA (V_GS)
Voltage (V _T ), But the threshold is depletion
The threshold voltage of the NMOS transistor becomes negative
And V_GSIs OV_DElectric current flows. V_GSIs 0V
I at the time_DIf the value of_GSO near 0V
N, OFF switching became possible. Also, I_D
V when the value of_T Is V_GSConcentrated near 0V
Was. Then I_D= 0 V
Threshold voltage V_TThe threshold with
If the NMOS transistor is used, V_GS0V
ON / OFF control with upside down
Semiconductor device.

(Embodiment 11) FIG. 13 shows an eleventh embodiment of the present invention, in which a semiconductor device in which four NMOS transistors are combined has an enhanced threshold voltage.
FIG. 4 is a characteristic diagram illustrating a transistor. In an NMOS transistor whose threshold value is enhanced, the threshold voltage becomes positive, so that _ID current does not flow when V _GS is OV. Therefore, V _GS when the current that can be detected flows
Is smaller as a switching element. If the threshold is an NMOS transistor of the enhancement small as V _T is the ideal semiconductor device as a switching element.

[0062] Figures 7 and 8 or FIG. 43 and FIG. 44 is a schematic wiring diagram of the MOS transistor 4 combined semiconductor device from 7th shown in the eleventh embodiment of the present invention, V _F in this manner Thus, a semiconductor device corresponding to a Schottky barrier diode semiconductor device having four elements and a small leakage current can be obtained.

FIGS. 7 and 8 are completely equivalent circuits. With such a connection, the circuit thus constructed operates as a rectifier. FIGS. 43 and 44 are also completely equivalent circuits, and with such a connection, they operate as a modulator. (Embodiment 12) FIG. 18 is a plan view showing a semiconductor device according to a twelfth embodiment of the present invention in which four Schottky barrier diodes are combined in a crossed manner. 8 and 2
As shown in FIG. 5, when a wiring pattern that connects diagonal electrode pads is designed, it is necessary to take measures to prevent two diagonal lines from intersecting with each other. In addition, if the wiring is divided into upper and lower two layers via an insulating film, the number of manufacturing steps increases, and the manufacturing cost increases. Therefore, as shown in FIG. 18, by connecting one diagonal line so as to pass outside the electrode pad 1801, it is not necessary to form a two-layer structure, which is advantageous in terms of manufacturing cost. However, when one of the diagonal wires is passed outside the electrode pad 1801, only one of the wires has a longer wiring portion than the other three wires.
Variations occur in individual characteristics. In particular, since the semiconductor device of the present invention is used at a high frequency, it is necessary to suppress variations. In order to match the length of the long wiring that passes the three short wirings out of the electrode pad, it is necessary to design the wiring so that the length of the four wirings is the same while appropriately folding the wiring. It can be suppressed. Therefore, by using the wiring pattern as shown in FIG. 18, it is possible to reduce the cost of a semiconductor device in which diagonal electrode pads are connected as shown in FIG. 25 or FIG.

FIGS. 19 and 2 show the semiconductor device of the present invention.
0, also applicable to the embodiment as shown in FIG. (Thirteenth Embodiment) FIG. 19 is a diagram showing a thirteenth embodiment of the present invention.
ced Mixer (hereinafter abbreviated as DBM). The semiconductor device of the present invention is applied to a broken line portion in FIG. In the DBM, if a diode with uneven characteristics is used, carrier leakage increases and satisfactory performance cannot be obtained. Therefore, it is important to use four diodes with uniform characteristics. Further, as can be seen from FIG. 19, a coil is used in the DBM, and connection between the input side and the output side is facilitated by using a semiconductor device in which wiring is crossed as shown in FIG.

(Embodiment 14) FIG. 20 is a circuit diagram of a data carrier functioning as a power supply according to a fourteenth embodiment of the present invention. This circuit receives the transmitted signal with an antenna, and the data is temporarily stored in a capacitor. The energy stored in this capacitor is used as a power source to transmit a signal in reverse. The semiconductor device of the present invention is used in the rectification section of the circuit, by using a MOS transistor or a Schottky barrier diode each element small threshold voltage V _F of the semiconductor device of the present invention, high speed and low voltage A drive circuit has become possible.

(Embodiment 15) FIG. 21 shows a receiving circuit including a signal processing circuit according to a fifteenth embodiment of the present invention. In this circuit, a signal received by the antenna 2101 is rectified and transmitted to a signal processing circuit made of CMOS. The semiconductor device of the present invention is used for the rectifier 2102 shown by the broken line, and a high-speed and low-voltage driving circuit can be realized.
Also, the external inductor can be easily connected by a diode bridge semiconductor device in which the wiring is crossed as shown in FIG. If a microinductor capable of high-frequency operation is used, an inductor, a Schottky barrier diode semiconductor device, and a CMOS signal processing circuit can be mounted on one chip, and can be directly manufactured on an IC substrate. Similarly, in the circuit of FIG. 19 and the circuit of FIG. 20, an on-chip type circuit could be manufactured on an IC substrate by using a micro inductor for the inductor portion.

(Embodiment 16) FIG. 38 is a schematic cross-sectional view of a semiconductor device according to a sixteenth embodiment of the present invention, in which wiring is performed so that the potentials of the gate and the substrate of the MOS transistor are equal. The structure of this semiconductor device will be described. p-type Si
An n-well diffusion layer or substrate 3802 is formed on a substrate 3801, and a source 3806 is formed in the diffusion layer.
And a drain 3807 and an n + diffusion layer 3808 were formed.
An oxide film 3803 was formed on the upper surface of the p-type Si substrate 3801, and the potential of the substrate 3802 via the source 3806, the drain 3807, and the n + diffusion layer 3808 was taken by the electrode 3804. Also, source 380
A channel region 3809 is formed between the gate electrode 6 and the drain 3807, and the polarity is inverted by the potential of the gate 3805 formed via the oxide film 3803 located above the channel region 3809. In the semiconductor device of the present invention, wiring is performed so that the potential of the gate 3805 and the potential of the substrate 3802 are equal.

In the conventional MOS transistor, the gate 38
05 and the potential of the substrate 3802 separately
Therefore, the potential of the substrate 3802 is usually kept constant.
The potential of the gate 3805 to change the source 3806.
The current flowing between the drains 3807 was controlled. Only
The gate 3805 and the substrate of the present invention shown in FIG.
MO by the method of wiring the potential of
Source 3806 and drain 38 in S transistor
The threshold voltage V which is the rising voltage during the period 07_TMentioned earlier
Threshold voltage of MOS transistor in conventional wiring
Pressure V_TMOS transistor with lower threshold voltage VT
And turn on the source 3806 and between the drain 3807
It is possible to pass a current. In the conventional wiring described above,
Of the potential of the gate 3805
The potential of the substrate 3802 is relatively
Due to the reverse substrate effect acting in the opposite direction, the threshold
Voltage V_TWorks in the direction of increasing. However, FIG.
Such as gate 3805 and substrate 3802
When a method of wiring to a potential is used, the gate 38
05 of the substrate 3802
To the forward substrate effect, where the positions are relatively in the same direction.
Therefore, the threshold voltage V of the MOS transistor _TIs small
It will work in a certain direction. That is, the gate 3 of the present invention
805 and substrate 3802 have the same potential
Gate 3805 and the substrate
The potential directions of the rate 3802 are relatively different directions
Voltage V according to the conventional method wired as_TYo
Even smaller threshold voltage V_TCan be.

By electrically wiring the gate 3805 and the substrate 3802 so that the potentials of the gate 3805 and the substrate 3802 are equal, the threshold voltage of the MOS transistor is further reduced. In the bridge circuit, the loss voltage is reduced, and the bridge circuit can operate at a lower voltage.

FIG. 45 is a schematic cross-sectional view of a MOS transistor according to a sixteenth embodiment of the present invention, in which the gate potential and the substrate potential are connected so as to have the same potential. FIG. 45 shows the same wiring as FIG.
01 of the MOS transistor formed on
5 and the substrate 4502 taken via the n + diffusion region 4508 were connected such that the potentials were equal. MOS transistors as a plurality of semiconductor substrates formed on the SOI substrate 4501 were chemically etched and etched to the SiO ₂ film 4511 to which an etch stop was applied, and were electrically separated on the same support substrate.
In FIG. 45, a plurality of semiconductor substrates formed over an SOI substrate 4501 serving as a support substrate are formed in an island shape. Therefore, a MOS transistor having excellent air isolation was formed.

FIG. 46 illustrates a plan view of an island-shaped MOS transistor formed as shown in FIG. FIG.
6, a silicon island 4601 is formed in a quadrangular shape as shown in a dotted line of FIG.
Between them, a gate 4603 was formed. Substrate 46
02 is formed over the entire surface of the Si island 4601, and its electrode changes with the potential of the gate 4603.
I took it on the upper surface like 6.

(Embodiment 17) FIGS. 47 and 48 show a seventeenth embodiment of the present invention. FIG. 46 is a schematic cross-sectional view of a MOS transistor of a wiring in which the potential of the gate substrate and the potential of the drain are connected to be equal in FIGS. 38 and 45, respectively. The MOS transistors connected as shown in FIGS. 47 and 48 exhibit rectifying characteristics like a diode. FIG. 49 or FIG. 50 shows a circuit diagram equivalent to this wiring. FIG. 49 is a wiring diagram of an n-channel MOS transistor, which has rectification in the direction from the drain to the source. FIG. 50 is a wiring diagram of a p-channel MOS transistor, which has a rectifying property in the direction from the source to the drain, contrary to the n-channel MOS transistor.
By connecting the gate and the substrate to the same potential, the direction of the potential of the gate and the direction of the potential of the substrate work in the same direction, so that the threshold voltage VT of the MOS transistor decreases due to the forward substrate effect. Work on. FIG. 43, FIG. 44 or FIG. 7, FIG.
Thus, a diode bridge or mixer operating at a lower voltage can be manufactured. Therefore, FIG. 57 shows the n of the wiring in which the potential of the gate substrate shown in FIG.
This is a diode bridge in which channel MOS transistors are connected as shown in FIG.

FIG. 53 shows that the MOS transistor is connected to the SOI (S
It is sectional drawing of a manufacturing process order which shows the manufacturing method of the semiconductor device of the 2nd Example in this invention which is manufactured on an (icon on insulator) substrate. The S formed on the single crystal Si layer (5301) on the SOI substrate in FIG.
The iN layer (5305) is region-patterned with a photoresist (5304) (FIG. 53 (b)). Next, the single-crystal Si layer (5305) region-parallelized with the photoresist (5304) is partially covered with the underlying SiO ₂ insulating layer (533).
02) is etched away in a range not to reach (FIG. 5)
3C). Next, the LOCOS oxide film (5
307) are formed and separated from each other.
8) is formed (FIG. 53D). A diffusion region (5310) is formed in the separated Si layer (5308), and is subjected to contact etching to provide a wiring and a protective film (FIG. 53 (e)). In this way, an island-shaped MOS transistor semiconductor device which is dielectrically separated from the SOI substrate is formed.

FIG. 54 is a sectional view of an SOI substrate used in the method of manufacturing the semiconductor device of the second embodiment shown in FIG. The SOI substrate is a single crystal Si5401 and a Si substrate 54.
In addition, an SiO ₂ insulating film is formed between the single crystal Si 5401 and the single crystal Si 5401, so that the etching is always stopped by the SiO ₂ insulating film 5403 even if the etching is performed along the patterning formed on the single crystal Si5401. . In the SOI substrate used for the semiconductor device of the present invention, a single crystal S
A diffusion layer 5402 was formed on the side of the SiO ₂ insulating film of i5401. For example, when a p-channel MOS transistor is formed using an SOI substrate, the substrate is an n-type substrate, and thus P or AS is ion-implanted into the diffusion layer 5402 at a concentration of 1 to 5 × 10 ¹⁵ / cm ^2. . As a result, an n-substrate having a low resistance region is formed on the bottom surface of the formed PMOS substrate, so that the resistance value when the MOS transistor is turned on can be suppressed.

As an example of the use of a semiconductor device in which the potentials of the gate and the substrate of a MOS transistor are connected at the same potential as shown in FIG. 38, there is a semiconductor overcurrent detection circuit which operates at a low voltage. FIG. 61 is a circuit diagram of the overcurrent detection circuit of the present invention. PMOS transistor 61
03 and the resistor 6104 are connected in series, the source of the PMOS transistor 6103 is connected to the high voltage supply terminal 6101, the source of the PMOS transistor 6103 is connected to the high voltage supply terminal 6101, and the other end of the resistor 6104 is connected to the low voltage supply terminal. 6102. Further, a resistor 6105, a switch 6106, and a load 6107 are connected in series. The other end of the resistor 6105 is connected to the high voltage supply terminal 6101, the other end of the load 6107 is connected to the low voltage supply terminal 6102, and a connection point 6109 between the resistor 6105 and the switch 6106.
Is connected to the gate of the PMOS transistor and the substrate. Further, a PMOS transistor 6103 and a resistor 610 are provided.
The connection point 6110 of 4 becomes an input of the control circuit 6108,
An output of the control circuit 6108 is an input of the switch 6106.

Next, the operation of the above configuration will be described. The resistance of the resistor 6105 is about 50 mΩ, and a current of about 1 A normally flows through this resistor. Therefore, the voltage drop between the high voltage supply terminal 6101 and the connection point 6109 is about 0.05 V, and the connection point 6109 is
Since it is connected to the gate of the S transistor, the PMOS
The gate voltage of the transistor is about 0.05V. Since this is sufficiently lower than the threshold voltage normally set to about 0.2 V to about 0.7 V, in this state, the PMOS transistor 6103 has a high impedance, and the potential of the connection point 6110 is set to the low voltage supply terminal 6102. Is sufficiently close to this potential. From this state, if the current value flowing through the resistor 6105 becomes larger than 1 A for some reason, for example, from 3 A to 4 A, the voltage drop from the potential of the high voltage supply terminal 6101 at the connection point 6109 becomes about 0.15 V to 0.2 V. Become. At this time, the gate voltage of the PMOS transistor approaches the threshold voltage, and the impedance of the PMOS transistor decreases. Therefore, the control circuit 610
The potential at node 6110, which is also the input of 8, rises and the output of control circuit 6108 operates to turn off switch 6106, thereby preventing overcurrent from flowing.

In the above operation, when the substrate of the conventional MOS transistor is connected to the source, the surface potential of the channel is between the substrate potential and the gate potential, whereas the gate potential of the MOS transistor is different from that of the conventional MOS transistor. When the substrate is connected, the surface potential of the channel becomes equivalent to the gate voltage and the substrate potential, so that the channel can be formed efficiently. Next, effects of the present invention will be described with reference to FIG. FIG. 60 is an operation characteristic diagram comparing a MOS transistor according to the present invention with a conventional MOS transistor. Comparing the operating characteristic 6001 according to the present invention with the conventional operating characteristic 6002,
Although there is not much difference when the gate voltage is 30 mV or less (off-leakage range), the gate voltage, which is the actual operating point, is 0.15.
At -0.25 V, the drain current value is improved by about one digit. With this improvement, in the overcurrent detection circuit of the present invention, it becomes possible to start the operation of the control circuit 6108 when the voltage drop at the connection point 6109 is small, so that a low voltage operation and a high sensitivity can be achieved.

First, the data carrier will be described here. This data carrier technology is a technology in which a card or tag storing information is attached to a moving object, and the information is read out by radio wave, electromagnetic coupling, or optical communication in a non-contact manner. For this purpose, there are an interrogator for issuing an instruction and a transponder for receiving an instruction integrated with an object and transmitting information.
The interrogator and the transponder are located at spatially separated places, and the transmission means between them uses mainly radio waves. Therefore, such an information medium that can carry and read and write information without contact using radio waves or light as transmission means is called a data carrier. Therefore, since the data carrier is capable of individually recognizing a person or an object and reading / writing attribute information from a remote place, it has an enormous merit of being able to identify a moving individual of a person or an object. Transmission media between the interrogator and the transponder are generally divided into three types: an electromagnetic induction type, an optical type, and a microwave type.

In the case of the electromagnetic induction system, a coil is used in the transmission / reception circuit, and the electromotive force is induced when the magnetic flux crossing the current path changes. Can be induced in response to the changed current and at the same time draw electricity. Power is supplied and data is transmitted and received using this electromagnetic induction. In this system, communication is performed at a distance of several millimeters to several tens of millimeters by coils that are close to each other, but the frequency is several tens of millimeters.
From 00 kHz to several MHz.

A data signal transmission method using the electromagnetic induction method will be described. For transmission and reception of information, a serial transmission signal from an interrogator is modulated to a predetermined frequency by a transmission circuit and sent to a transmission coil. The modulation method is the ASK method of turning on / off the signal of the frequency transmitter in accordance with the information, or the information of two different frequency signals is given to one frequency of logic 0 and the frequency of logic 1 is given different frequencies and switched. There is an FSK method. The information of the interrogator is modulated and sent out from the transmitting coil, and the induction signal received by the receiving coil is demodulated to the original digital signal by the demodulator of the receiving circuit. The demodulated serial signal is converted to a parallel signal by a serial / parallel converter, and a memory controller controls writing and reading in the memory and stores information in the memory at the same time.

In the optical system, both the interrogator and the transponder are provided with a light emitting element and a light receiving element. Mainly, the light emitting element is L
Since a photodiode is used for the ED and light receiving element,
The light becomes near infrared. On the interrogator side, the driving circuit drives the light emitting element with respect to the input pulse waveform to emit light. The emitted light is detected by the light receiving element on the transponder side, becomes a large signal by the amplifier, and the original waveform is restored through a detection circuit, a waveform shaping circuit and the like. Similarly, when a signal is returned from the transponder side, the light emitted from the light emitting element on the transponder side is received by the light receiving element on the interrogator side, and the signal is restored using an amplifier. Although the optical system is strong against electromagnetic noise, it is susceptible to dirt such as water or oil or disturbance light, and communication is not possible if light is blocked, and it is almost impossible to eliminate batteries.

The microwave system uses, as an information transmission medium, a radiated electromagnetic field (so-called radio wave) of a quasi-microwave of 2.45 GHz allocated for identification of a moving body in the private radio equipment. In this method, the communication distance between the antenna on the interrogator side and the antenna on the responder side is 2 to 3 m, and sharp directivity is obtained. Are suitable. The interrogator and the transponder are used by changing the polarization plane for transmission and reception with one attached antenna. The frequency in the 2.45 GHz band is a communication band specifically set for identifying a mobile unit, and is legally protected, so that stable communication can be expected. However, there is a disadvantage in that the conductor is easily reflected by the conductor and cut off by the human body.

FIG. 39 is a block diagram of a data carrier according to a fourteenth embodiment of the present invention. This system is composed of an interrogator that issues a command signal in a system called a data carrier or RF-ID, and a transponder that sends back data in response to the received command signal. The semiconductor device of the present invention is used in the rectification section of the circuit, a small MO each element of the semiconductor device of the present invention the threshold voltage V _F
By using the S transistor and the Schottky barrier diode, a high-speed and low-voltage driving circuit can be realized, and current loss in the rectifier circuit portion can be reduced. When the power supply circuit used for the data carrier can operate at a low voltage, the data carrier itself can operate at a low voltage together with a rectifier circuit capable of driving at a low voltage. As a result, communication over a longer distance than the previous data carrier becomes possible, and power consumption in the interrogator can be suppressed, thereby improving power transmission efficiency.

FIG. 39 shows a semiconductor device integrated into one chip.
Is shown in part A of FIG. By forming a rectifier circuit or a modulator operating at a low voltage, a power supply circuit operating at a low voltage, and a control circuit for controlling a signal to be output to a memory on a single chip as shown in part A of FIG. Since it is reduced and the chip area is remarkably reduced, it is applied to portable equipment or data carrier tags.

FIG. 63 is a block diagram showing the system configuration of the tag section of the data carrier. The rectifier circuit, the control circuit, and the power supply circuit shown in the part A of FIG. 39 correspond to the part A shown by the broken line in FIG. The data carrier tag shown in FIG.
Built-in EPROM. Coil L as antenna part
Is used, and communication is possible without a battery by an electromagnetic induction method. The internal circuit configuration is a full-wave rectifier circuit, constant voltage circuit, ASK data demodulation circuit, carrier pulse extraction circuit,
Communication logic, memory blocks including EEPROM,
It incorporates a minimum operating voltage detection circuit and a residual vibration absorption circuit that is a data transmission function.

A method of transmitting and receiving the data carrier tag will be described. The current generated by the coil L serving as the antenna unit or the current generated by the electric charge stored by the capacitor C1 is subjected to full-wave rectification by a diode bridge and a smoothing capacitor C2 which are full-wave rectifiers, and is fixed by a constant voltage circuit. Generate a DC power supply. The communication logic or the EEPROM is operated by the DC power supply.

Next, a data transmission / reception system will be described with reference to FIGS. 64 and 65. FIG. 64 shows waveforms at various points when data is received. As shown in FIG. 64A, pulse width modulation (Duty 70%: H, Du)
When the signal multiplied by (ty 30%: L) is transmitted, the resonance signal as shown in FIG. 64 (b) is demodulated through the ASK data demodulation circuit by diode detection to the pulse width modulated data clock as shown in FIG. 64 (c). . The carrier pulse in FIG. 64D is output from a carrier pulse extraction circuit by half-wave extraction. This data clock and carrier pulse are C
The signal is input to the MOSIC, demodulated into an NRZ code by the communication logic, and command processing and memory access are performed.
The operation of the communication logic is performed using the data clock as a basic clock. FIG. 65 shows waveforms at various points during data transmission. As shown in FIG.
uty 50% is transmitted. On the data carrier side, a resonance waveform is induced at both ends of the coil as shown in FIG. This resonance waveform is applied to the data clock (Dut) shown in FIG.
y50%). The communication logic operates using this clock as a basic clock, and generates data after memory access, processing results, and the like as transmission data in FIG. 65C in the communication logic.
Encoding is performed on the shunt pulse (reverberation vibration absorption pulse) shown in (d), and the presence / absence of reverberation vibration is controlled by transmission data in the reverberation absorption MOS-FET. The read / write head detects the presence / absence of the reverberation to receive transmission data from the data carrier.

[0088] In the full-wave rectifier circuit 6301 in FIG. 63, a low threshold voltage of the present invention represented by small MOS transistors V _T such connecting a small Schottky barrier diode and the gate and the substrate of V _F rectifier A semiconductor device having characteristics is used. As a result, the current consumption of the full-wave rectifier circuit 6301 can be made smaller than that of the conventional one, so that the power consumption of the data carrier tag itself can be suppressed. As a result, the communication distance becomes longer than that of the conventional one. If the communication distances are the same, the power consumption of the interrogator including the controller can be reduced.

FIG. 40 is an image diagram of a very small data carrier according to the fourteenth embodiment of the present invention. Capsule 4
The antenna 40 shown in the block diagram of FIG.
02, a power supply circuit 4003, a memory 4004 such as an EEPROM, a rectifier circuit, and a control circuit. The radius of the cylinder of this elongated chip is about 0.5 mm, and if an ultra-small winding bar antenna is used for the antenna 4001, it can be mounted in an elongated chip with a cylinder radius of 0.5 mm or less. Becomes

The ultra-compact, battery-less data carrier produced in this way may be used not only for animal breeding management but also as a human embedded ID. In other words, data such as passports, driver's licenses, and qualifications or careers possessed by the person as the human ID can be incorporated into this ultra-small data carrier, and the data carrier can be embedded in the human body and used Becomes

Further, the ultra-small data carrier may be used as a power source of a micro machine expected to be active in the field of medical equipment such as operating in a human body or a blood vessel. By embedding a carrier in the body of a competing human, more accurate measurement and timekeeping in the competition becomes possible.

In the data carrier as described above, it was possible to read and write information in the memory attached to the moving object, but the environment around the transponder where the ever-changing moving object is placed or I couldn't draw on the situation. Therefore, an information transmission system for reading out real-time data such as sensors and indicators in a non-contact manner will be described below.

(Embodiment 18) FIG. 27 is a block diagram of a data carrier having an acceleration sensor according to an eighteenth embodiment of the present invention. The controller and antenna written on the left are interrogators that issue command signals. The interrogator receives a command through a higher-level interface, and issues the command signal from the antenna to the transponder. A transponder in which an antenna, a rectifier circuit, a power supply circuit, and an acceleration sensor written on the right side are attached to a moving body. The semiconductor device of the present invention is applied to a rectifier circuit drawn in a transponder. Each element of the threshold voltage V _F of small MOS transistors and Schottky barrier diode fast and low-voltage drive circuit by using a semiconductor device of the present invention is possible, the threshold voltage V _F in the rectifier circuit Power loss is reduced. The transponder receives the command signal emitted from the interrogator by the antenna, is rectified by the rectifier circuit using the semiconductor device of the present invention, enters the power supply circuit, and generates the reference voltage V _CC . Reference voltage V _CC made by power supply circuit
Is the input voltage of the acceleration sensor. When the output of the acceleration sensor is an analog signal as shown in FIG.
/ D conversion and conversion into a digital signal output. When a comparator is included in the output circuit of the sensor, its output becomes a digital signal as it is. The signal received by the antenna is temporarily stored in a capacitor. When the signal has been completely sent from the interrogator, the energy stored in the capacitor is used as a power source,
The response signal from the transponder is sent back to the interrogator. Then, the interrogator receiving the signal transmits the data to the upper interface. With this configuration, it is possible to detect the magnitude of the acceleration or force applied to the moving body in a non-contact manner without mounting a battery on the transponder.

FIG. 28 is a perspective view of an acceleration sensor section of a data carrier having an acceleration sensor according to an eighteenth embodiment of the present invention. This acceleration sensor includes a Si substrate 2806 on which a diffusion resistor 2802 is formed, a weight 2801 serving as a weight of a cantilever, and a support substrate 2805. When the Si substrate 2806 receives acceleration, the weight 2
Since 801 has a cantilever shape, it is in the direction of receiving the acceleration. Therefore, the diffusion resistance 2802 embedded in the beam portion of the cantilever receives a stress proportional to the acceleration, and changes with respect to the stress applied with the resistance value of the diffusion resistance 2802. This electrical change is applied to the support substrate 2805 through the pad 2803 and the wire bonding 2804.
It is transmitted to. The Si substrate 2806 is divided into a sensor portion and a support portion with the beam portion upside down. The support portion of the acceleration sensor is attached to the support substrate 2805 and is completely fixed.

FIG. 34 is a perspective view of an acceleration sensor section of a data carrier having an acceleration sensor according to the eighteenth embodiment of the present invention. The acceleration sensor of FIG.
Si substrate 3401 on which support 4 is formed and support substrate upper portion 3402
And a support substrate lower portion 3403. In this acceleration sensor, the Si substrate 3401 has the diffusion resistance 3
The patterning surface on which the 404 is formed is placed sideways, and the laterally oriented Si substrate 3401 is fixed by sandwiching the upper support substrate 3402 and the lower support substrate 3403. For this purpose, the upper support substrate 3402 or the lower support substrate 3
When acceleration in the vertical direction is applied to the bonding surface between the 403 and the Si substrate 3401, the Si substrate 3401 is distorted in the direction in which the acceleration is applied, and a stress proportional to the acceleration is applied to the diffusion resistor 3404. As a result, the resistance value of the diffusion resistor 3404 changes with respect to the applied stress, and the output voltage changes in proportion to the acceleration. Since the Si substrate 3401 is obtained by laying chips obtained by cutting a Si wafer into a length L and a width W sideways, t in the figure is the thickness of the Si wafer itself. It is also possible to make the thickness smaller than the thickness of the Si wafer. If W is reduced, the sensitivity of the sensor can be improved. However, since there is a limit in dicing processing accuracy, W is limited to about 100 μm.

FIG. 29 is a circuit diagram of an acceleration sensor section of a data carrier having an acceleration sensor according to an eighteenth embodiment of the present invention. The diffused resistor 2802 depicted in the acceleration sensor of FIG. 28 is the bridge circuit 2901 depicted in FIG.
Is a variable resistor. When acceleration is applied to the acceleration sensor, the resistance value of the variable resistor of the bridge circuit 2901 changes.
The output voltage of the bridge circuit 2901 also changes in proportion to the magnitude of the acceleration applied to the acceleration sensor. The output voltage of bridge circuit 2901 is amplified to some extent by preamplifier 2902. The amplified signal is supplied to a temperature compensation circuit 290
3, the signal is amplified by the final amplifier 2904 to a desired level of sensitivity.

FIG. 35 is a circuit diagram of an acceleration sensor section of a data carrier having an acceleration sensor according to an eighteenth embodiment of the present invention. This circuit diagram is a circuit assembled for an acceleration sensor having a diffusion resistance that receives a tensile stress and a compressive stress when an acceleration is applied in a certain direction as in the acceleration sensor shown in FIG. is there. Diffusion resistance, which increases in resistance under tensile stress, decreases in resistance under compressive stress, and diffusion resistance, which increases in resistance under compressive stress, decreases in resistance under tensile stress. In the acceleration sensor Si substrate 3401 shown in FIG. 34, when acceleration is applied from above the paper surface to below the paper surface, the diffusion resistor 3404 attached above the Si substrate 3401 receives a tensile stress,
The diffusion resistor 3404 provided on the lower side of the substrate 3401 receives a compressive stress. When an acceleration is applied from below the paper surface to the paper surface, opposite stresses are applied to each. Thus, the bridge circuit 3501 is assembled as shown in FIG. 35 by combining the diffusion resistances having the resistance values opposite to each other. Thus, when acceleration is applied to the acceleration sensor, the resistance value of the variable resistor of the bridge circuit 3501 changes, and the output voltage of the bridge circuit 3501 also changes in proportion to the magnitude of the acceleration applied to the acceleration sensor. The output voltage of the bridge circuit 3501 is
It is amplified to some extent by 502. The amplified signal passes through a temperature compensation circuit 3503 and is amplified by a final amplifier 3504 to a desired level of sensitivity.

FIG. 30 is an output characteristic diagram of an acceleration sensor section of a data carrier having an acceleration sensor according to the eighteenth embodiment of the present invention. This output voltage is an output voltage passed through the circuit shown in FIG. The output voltage when no acceleration is applied is set to 0V, the output voltage when + 1G is applied is 2V, and the output voltage when -1G is applied is -2V. Thus, in the ideal characteristic diagram, an output voltage proportional to the acceleration applied to the acceleration sensor can be obtained.

(Embodiment 19) FIG. 31 is a block diagram of a data carrier having a temperature sensor according to a nineteenth embodiment of the present invention. The nineteenth embodiment is an example in which a temperature sensor is mounted instead of the acceleration sensor as in the eighteenth embodiment. The controller and antenna written on the left are interrogators that issue command signals. The interrogator receives a command through a higher-level interface, and issues the command signal from the antenna to the transponder. This is a transponder in which the antenna, rectifier circuit, power supply circuit, and temperature sensor written on the right side are attached to the moving object. The semiconductor device of the present invention is applied to a rectifier circuit drawn in a transponder.

Each element of this semiconductor device is connected to a threshold voltage V
By using a MOS transistor having a small _F or a Schottky barrier diode, a high-speed and low-voltage driving circuit can be realized, and power loss corresponding to the threshold voltage V _F in the rectifier circuit is reduced. The transponder receives the command signal emitted from the interrogator by an antenna, rectifies the signal by a rectifier circuit using the semiconductor device of the present invention, enters a power supply circuit, and generates a reference voltage V _CC . The reference voltage V _{CC generated} by the power supply circuit becomes the input voltage of the temperature sensor. Figure 3 shows the output of the temperature sensor.
The signal becomes an analog signal as shown in FIG. 3, but becomes a digital signal after A / D conversion. When a comparator is included in the output circuit of the sensor, the output is a digital signal. The signal received by the antenna is temporarily stored in a capacitor. When the signal has been completely transmitted from the interrogator, the energy sensor temporarily sends the output signal of the temperature sensor back to the interrogator using the energy stored in the capacitor as a power source. Then, the interrogator receiving the signal transmits the data to the upper interface.
With such a configuration, it is possible to detect the surface temperature of the moving body itself or its surrounding temperature in a non-contact manner without mounting a battery on the transponder.

FIG. 32 is a circuit diagram of a temperature sensor section of a data carrier having a temperature sensor according to a nineteenth embodiment of the present invention. A constant current circuit is placed at the norator 3201. The temperature sensor has a linear output characteristic with respect to a change in temperature as shown in FIG. A constant current generated by the constant current circuit flows through the temperature sensor, and the potential difference between both ends of the temperature sensor changes with a change in temperature. The potential difference of the temperature sensor is output as an output voltage through an output circuit 3202 such as a buffer or a comparator. In addition, a desired output voltage can be obtained by connecting a feedback resistor or the like and using the output circuit 3202 as an amplifier.

FIG. 33 is an output characteristic diagram of a temperature sensor section of a data carrier having a temperature sensor according to a nineteenth embodiment of the present invention. As temperature sensors, there are temperature sensors such as a thermistor, a resistance temperature detector, or an IC temperature sensor using a temperature coefficient of a forward voltage drop between a base and an emitter of a bipolar transistor. FIG. 33 is convenient for forming an IC. The temperature output voltage characteristics of an IC temperature sensor having high linearity with respect to temperature and high sensitivity are shown.

In the above, mounting of sensor devices such as an acceleration sensor and a temperature sensor in place of a memory and a control circuit for controlling the memory has been described. In addition, an indicator such as a buzzer and an LED is mounted.
It is also possible to add a function of making a sound or emitting light when a signal is received. (Embodiment 20) FIG. 37 is a cross-sectional view of a twentieth embodiment of the present invention when measuring vibration of a cylindrical system. As shown in the figure, if the acceleration sensor is attached to the side of the cylindrical object facing the axis of the cylindrical system toward the axis where the acceleration can be detected, it is possible to detect vibration in the side direction from the axis of the cylinder,
The magnitude of vibration in a certain direction can be detected in real time.
Here, if the width of the acceleration sensor is wide, the detection range of the vibration becomes the size of the range of the angle β shown in FIG. If the detection range is wide, vibrations in other directions besides the vibration in the target direction are also widened, so that the sensitivity of the magnitude of the vibration in the target direction is reduced and the error increases. In the measurement of vibration of a cylindrical system using a conventional acceleration sensor, since the width of the acceleration sensor required 1 mm or more, vibration in the range of the angle β corresponding to the width was detected.

FIG. 36 is a cross-sectional view when measuring the vibration in the side direction of the cylindrical system using the acceleration sensor according to the twentieth embodiment of the present invention. As shown in FIG. 36, when measuring the vibration in the side direction of the cylindrical system, if an acceleration sensor is attached to the side of the cylindrical object facing the axis of the cylindrical system, the measurement range is the acceleration. The magnitude of vibration in a range corresponding to the magnitude of the angle α corresponding to the width of the sensor is detected. Therefore, if the width of the acceleration sensor that determines the range of the vibration measurement is reduced, the vibration measurement range angle α is also reduced, and the sensitivity of the magnitude of the vibration in the target direction can be improved, and the error can be reduced. Since the width of the acceleration sensor used in the present invention is formed of a chip having a width of 1 mm or less, the measurement range is narrower and narrower than that of a conventional measurement of a vibration system using a wide acceleration sensor. Therefore, it is possible to improve the sensitivity of vibration in a target direction.

When the vibration system is measured in this way, by mounting such an acceleration sensor having a narrow measurement range on the acceleration sensor of the system as shown in FIG. It is possible to read the force, acceleration or vibration with high sensitivity and without contact at any time.

A system for measuring a vibration system in a non-contact manner using such an acceleration sensor is applied in various fields. For example, daily necessities are used to control the vibration of a washing machine, and ABS control and motor or engine control can be performed in a non-contact manner as car parts, so that effective measurement and control can be performed. Also, the use of a pressure sensor makes it possible to measure the tire pressure of a car in a non-contact manner.

(Embodiment 21) FIG. 58 is a circuit diagram of a DC-DC converter according to a twenty-first embodiment of the present invention. DC
The -DC converter is a circuit for converting a DC voltage into another DC voltage, and is classified into a step-down type, a step-up type, and an inversion type. The semiconductor device of the present invention is used for this DC-DC converter. These types differ depending on the configuration of switches, coils, capacitors, and rectifier diodes, and the semiconductor device of the present invention is used for the rectifier diode portions 5801 to 5803.

FIG. 58A shows a step-down DC-DC converter. First, the switch is turned on, and current flows from the input-side power supply to the coil. At this time, if the value of the flowing current changes, a back electromotive force _VL is generated in the coil, and DC-DC
The output voltage of the converter becomes V _i -V _L. The capacitor C is under voltage of V _i -V _L. At this time, an electromotive force is generated in the coil in a direction opposite to that in the ON state. The current flows from the ground to the semiconductor device 58 of the present invention having a rectifying characteristic.
01 and stored in a capacitor. Output voltage rises than the V _i -V _L. However, the charge stored in the capacitor is discharged via the load resistor R. When the output voltage drops, the switch is turned on again, and the above operation is repeated. Therefore, a desired output voltage can be set by controlling the duty ratio of the switch.

FIG. 58B shows a step-up DC-DC converter. In the initial state is under voltage V _i -V _D to the capacitor C. V _D is a forward voltage of the semiconductor device 5802 of the present invention having rectification characteristics. ON the switch from this state Then, current flows from the coil to the switch, at both ends of the coil voltage V _i of the input voltage and the reverse direction is generated. Since a voltage is applied to the semiconductor device 5802 of the present invention in the reverse direction, the input side and the load side are cut off. When the next switch is turned off, a voltage _{VL in the} same direction as the input voltage is generated in the coil. Then, the capacitor C has V _i + V _L
Takes the voltage of -V _D, the output voltage is boosted by V _L -V _D. Set V _L > V _D.

FIG. 58C shows an inverting type DC-DC converter. When the switch is turned on, a current flows through the coil, and a voltage VL in the opposite direction to the input voltage is generated at both ends of the coil. Semiconductor device 5803 of the present invention having rectification characteristics
Is reverse biased, and the input side and load side are cut off. OFF switch Then, the coil voltage -V _L of the input voltage and the forward direction is generated. The capacitor is a semiconductor device 580
Since a voltage of-(V _L -V _D ) is applied via 3, the output voltage becomes negative.

When the semiconductor devices 5801 to 5803 of the present invention are used in the rectifying element portion of such a DC-DC converter, the semiconductor device of the present invention has a lower rising voltage in the forward direction than the conventional rectifying device. It is possible to reduce the amount of power loss in the element. That is, the conversion efficiency of the DC-DC converter increases due to the reduction in the amount of power loss in the rectifier.

FIG. 66 is a block diagram of a step-down DC-DC converter employing a synchronous rectification system according to a twenty-first embodiment of the present invention. This type of converter is characterized by an n-channel MOS for synchronous rectification in parallel with the rectifier diode 6601.
The point is that the FET 6603 is inserted. This MOSF
The ET6603 operates in synchronization with the MOSFET 6602 for the switch. The operation method will be described below.
Switch MOSFET 6602 is turned on by control IC.
N. Then, a current flows through the coil, and an electromotive force is generated. Next, the control IC turns off the switching MOSFET 6602. Accordingly, the energy stored in the coil is extracted to the output side. MOSFET for switch
At the same time as turning off 6602, the control IC turns on rectifying MOSFET 6603 and supplies current to the coil. The control IC monitors the output voltage, detects a change in the output voltage, and changes the switching duty ratio. The output voltage is determined by the product of the duty ratio of the switching frequency and the input voltage. FIG. 67 is a block diagram of a step-down DC-DC converter according to a twenty-first embodiment of the present invention. This converter does not have a MOSFET for synchronous rectification or a switch control circuit for synchronous rectification.
When FF is performed, current is supplied to the coil only by the rectifier diode 6701.

DC-DC of synchronous rectification system shown in FIG.
The converter can reduce power loss in the rectifier diode 6604 by using the MOSFET 6603 for rectification as compared with the DC-DC converter shown in FIG. The only current supply element connected to the coil in the DC-DC converter shown in FIG. 67 is a rectifier diode 6701, but the synchronous rectification type DC-DC converter shown in FIG. A MOSFET 6603 is inserted, and a signal having a phase opposite to the signal input to the gate of the switching n-channel MOSFET 6602 is input to the gate electrode of the n-channel MOSFET 6603. For example, if the output current is 1A,
If only a rectifier diode with a forward voltage of 0.5 V is used, the power consumption of the diode is 500 mW. If an n-channel MOSFET with an ON resistance of 50 mΩ is inserted in parallel with the rectifier diode, the power consumption can be reduced to 50 mW. Normally, an n-channel MOSFET is used because an n-channel MOSFET has a lower ON resistance than a p-channel MOSFET. In addition, the DC-DC converter of the synchronous rectification system has a drive circuit that synchronously moves the MOSFET for the switch and the MOSFET for the rectification. In addition, by providing a period in which both MOSFETs are OFF, two MOSFETs are switched at the time of switching. Preventing the current flowing through it. Thus, in the DC-DC converter of the synchronous rectification system, it is possible to reduce the power loss in the rectifier diode unit 6604.

Here, a semiconductor device such as a Schottky diode or a MOS transistor of the present invention which operates at a low voltage and has a rectifying characteristic is used in place of the rectifying elements 6601, 6603, 6701 shown in FIG. 66 or 67. This makes it possible to further reduce the power loss in the rectifying element, so that a DC-DC converter with high conversion efficiency can be manufactured. A DC-DC converter with high conversion efficiency can also be manufactured by arranging MOS transistors connected so that the potential of the gate and the potential of the substrate are equal as in the sixteenth embodiment as shown in FIG. . A MOS transistor having a gate and a substrate connected as shown in FIG. 68 can have the same effect as the rectifying diode unit 6604 having the rectifying characteristics shown in FIG.

FIG. 59 shows a bus according to a twenty-second embodiment of the present invention.
FIG. 2 is a block diagram of a battery backup switching IC.
You. At the locations of the diode elements 5901 and 5902 in the figure,
The semiconductor device having the rectification characteristics of the present invention is used. V
_SWThe detection circuit is V_ROMonitors voltage and switches the detection result
Send to control circuit. The switch control circuit is V_SWDetection circuit
These signals are received to control M1 and M2. V_INBut
A certain reference voltage V _REFUntil it exceeds, switch system
The control circuit is V_SWM1 is turned on regardless of the state of the detection circuit,
M2 is turned off. Therefore, V_OUTOutput from
Is V_ROAnd the voltage obtained by subtracting the voltage drop due to M1 from
Become. V_INBut once V_REFExceed the switch control times
Road is V_SWReceives a signal from the detection circuit and exceeds a certain voltage
Then, M1 is turned on and M2 is turned off.
Turns M1 OFF and M2 ON. Therefore
The semiconductor device of the present invention has a diode element 5901 shown in FIG.
Used at 5902. The diode in the figure is reverse current
Rectifier element to prevent
The rise voltage of the conductor device is smaller than the conventional one.
Utilizing the characteristics, the semi-invented semiconductor device is used.
This can reduce the input / output voltage difference of the switch section.
As a result, it is possible to continue using the battery until the last minute.
You. In addition, a CMOS or SOI substrate
Is a rectifier with a dielectrically separated Schottky diode
Since the isolation between the elements can be completed by forming
By using the semiconductor device of the present invention, the circuit shown in FIG.
Manufacturing the semiconductor device of the present invention on the same substrate including
Becomes possible.

FIG. 69 is a sectional view of an embodiment of the semiconductor device according to the present invention. A second gate region 7101 serving as a channel formation region is formed of P-type single crystal silicon;
A case where the source region 7102 and the drain region 7103 are formed using an N + type silicon semiconductor will be described. Second gate region 7101 between source and drain regions
Is provided with a first gate electrode 7105 via a gate insulating film 7104. The surface potential φ _S of the second gate region 7101 between the source and drain regions is the applied voltage V _G1 to the first gate electrode, and the surface potential φ _S of the second gate region 7101 is the applied voltage to the first gate electrode. Controlled by V _G2 .

[0117]

(Equation 4) C _OX is the capacitance of the gate insulating film, and C _S is the capacitance in the channel formation region. Accordingly, the channel current _ID flowing between the source and drain regions is as shown in equation (5).

[0118]

(Equation 5) For example, when operating the semiconductor device of the present invention at _{V G = V G1 = V G2} ≧ 0 channel current is as equation (6).

[0119]

(Equation 6) Figure 71 is a characteristic diagram showing the changes in the channel current I _DS versus gate voltage V _G. By the _{V G = V G1 = V G2} , solid characteristic is shown by the broken line characteristic. A value called an S value, which is a gate voltage change required for the channel current I _DS to change by one digit, is as shown in equation (7).

[0120]

(Equation 7) For example, when the temperature T is a temperature, S = 60 mV / digit, which is an ideal value of the conventional MOS transistor operation. S
Since the value can be reduced to a small value as in the expression (7), when the semiconductor device is operated at a current ratio of 6 digits, the semiconductor device of the present invention can operate at a gate voltage of 0.35 V or less.
Therefore, in a circuit in which the load and the semiconductor device of the present invention are connected in series, it is possible to operate at a power supply voltage of 0.6 V or less. At a power supply voltage higher than 0.6 V, an operation faster than before becomes possible.

In the semiconductor device of the present invention, when a plurality of transistors are formed on the same substrate, the voltage of the second gate region differs between the transistors. Therefore, the second gate region of each transistor needs to be electrically isolated. It can be separated by PN junction isolation or dielectric isolation.

FIG. 72 is a cross-sectional view of an embodiment in which a plurality of semiconductor devices of the present invention are formed on the same substrate and each transistor is dielectrically separated. Insulating substrate 74
00 and the transistor Tr1 and the transistor Tr2
Are source regions 7402 and 7407 and drain region 7, respectively.
403, 7408, channel formation regions (second gate regions) 7401, 7406, gate insulating films 7404, 74
09 and the gate electrodes 7405 and 7410.

The substrate 7400 may be a substrate made of an entire insulating material such as glass or a semiconductor substrate having an oxide film formed on the surface. Each area has S1, S2, D1,
Electrodes D2, G11, G21, G12 and G22 are provided so that a voltage can be applied to each area.

Generally, the source region 7402, the channel formation region 7401, and the drain region 7403 of the transistor Tr1 are formed in the same film. Similarly, a source region 7407, a channel formation region 7406, and a drain region 7408 of the transistor Tr2 are formed in the same film.

The semiconductor device of the present invention is manufactured by using SOI (Silic).
When dielectric isolation is performed using a technique such as on-on-insulator, it is necessary to provide an electrode with a small area in a channel formation region. FIG. 73 is a plan view and a cross-sectional view of an embodiment in which a channel formation region also serves as a contact to a gate electrode. FIG. 73 (a) is a plan view, and FIG. 73 (b) is FIG.
3A is a sectional view taken along line AA ′, and FIG. 73C is a sectional view taken along line BB ′ in FIG. 73A. A common contact hole 7505b is formed in the P + type diffusion layer provided for ohmic contact between the gate electrode 7505 and the channel formation region 7501, and is connected to the common wiring 7506.

FIG. 74 is a sectional view of an embodiment having a structure in which the gate electrode 7605 is directly connected to the diffusion layer 7607 for ohmic contact. A contact hole for wiring to the gate electrode 7605 is provided at another location. Here, when the transistor of the present invention is operated with V _G = V _G1 = V _G2 , if V _G > V _B (V _B is the built-in potential between the source / drain region and the channel formation region), the source is switched from the channel formation region to the source. -A forward current flows to the drain region.

FIG. 75 shows an embodiment of the present invention in which a limit resistor R is provided between the channel forming region and the second gate electrode G2 to prevent the injection of the forward current. In order to set the forward current to 1 μA or less, V _G ≦ 1 V
Requires the formation of a resistance of R ≧ 10 ⁶ Ω.

FIG. 76 shows an embodiment in which bias control means for controlling the potential of the channel formation region is provided by a method different from that of the resistor. Figure 76 (a) is an equivalent circuit diagram, FIG. 76 (b) is a waveform diagram showing a signal change in the applied voltage Vsub to the applied voltage V _G and the channel forming region to the first gate electrode.

[0129] As the bias control means, an example using a divider circuit for dividing in half a voltage to V _G. FIG.
Applied at Vsub = V _G / 2 as shown in (b). For example, when operating at V _G ≦ 1 V, Vsub ≦ 0.5
Since it is V, the transistor can be operated with almost no forward current flowing.

As described above, by setting the potentials of the gate and the substrate of the MOS transistor to the same potential, or by applying a voltage having the same characteristics as the gate to the substrate in synchronization by wiring as shown in FIG. 76, M at low voltage
The OS transistor can be turned ON, and by connecting the OS transistor to the drain as shown in FIG. 49 or FIG. 50, a diode characteristic with a low rising voltage can be obtained. FIG. 76
Can control the potential of the channel region of the MOS transistor, so that a plurality of MOS transistors separated by PN junction isolation or dielectric isolation on the same supporting substrate can be controlled.
This is convenient for controlling the characteristics of individual MOS transistors when forming the transistors.

FIG. 51 shows a MOS transistor 510 according to a seventeenth embodiment of the present invention in which the gate potential, the substrate potential, and the drain potential are connected so as to be at the same potential.
FIG. 4 is a circuit diagram of a charge transport method (hereinafter referred to as a charge pump) configured using 2 to 5104 and capacitors 5109 to 5112. Here, as shown in FIG. 52, by inputting a signal (C _b ) having a phase opposite to that of the repetitive signal (C _K ) generated by the transmission circuit, the output voltage V
_{OUT is, V OUT = V IN + nV} IN - given by (n + 1) V _T. Here, n is a MOS transistor 5102
5104 and the number of pairs of capacitors 5109 to 5112. _VT is a rising voltage of the MOS transistor when the gate, the substrate, and the drain are connected. Since the MOS transistor when the gate, the substrate and the drain are connected can rise at a voltage lower than the rising voltage of the MOS transistor when the conventional diode or the gate and the drain are connected, the above equation is used. As described above, it is possible to obtain a larger V _OUT 5105 than the conventional V _IN even with the same V _IN .

[0132]

As described above, a Schottky barrier diode having a small threshold voltage and an excellent isolation can be obtained, thereby obtaining a Schottky barrier diode semiconductor device having a low voltage, low power consumption and low cost.

Further, it is possible to read out a constantly changing situation such as the acceleration applied to the moving body or the temperature around the non-contacting body at any time without contact. Further, since the surface potential of the channel formation region of the MOS transistor is controlled by both the gate voltage and the voltage applied to the substrate, an overcurrent detection circuit that can operate with high sensitivity and low voltage can be obtained.

By applying a voltage having the same characteristic as the gate voltage to the channel formation region in synchronization, a semiconductor device which operates at high speed and at low voltage can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a semiconductor device having a quaternary Schottky barrier diode according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a semiconductor device having a quaternary Schottky barrier diode according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a Schottky barrier diode according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a Schottky barrier diode according to a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a Schottky barrier diode according to a fifth embodiment of the present invention.

FIG. 6 is a view showing a sixth embodiment of the present invention, in which Si is 10 ° or less.
FIG. 3 is a schematic sectional view showing a diode having an O ₂ film.

FIG. 7 is a schematic connection diagram showing a semiconductor device in which four MOS transistors of the present invention are combined.

FIG. 8 is a schematic connection diagram showing a semiconductor device in which four MOS transistors of the present invention are combined.

FIG. 9 is a schematic sectional view showing a semiconductor device according to a seventh embodiment of the present invention in which four NMOS transistors are combined.

FIG. 10 is a schematic sectional view showing a semiconductor device in which four NMOS transistors according to an eighth embodiment of the present invention are combined.

FIG. 11 is a schematic sectional view showing a semiconductor device according to a ninth embodiment of the present invention in which four NMOS transistors are combined.

FIG. 12 is a characteristic diagram showing an NMOS transistor having a depletion threshold in a semiconductor device in which four NMOS transistors according to a tenth embodiment of the present invention are combined.

FIG. 13 is a characteristic diagram showing an NMOS transistor with an enhanced threshold in a semiconductor device in which four NMOS transistors according to an eleventh embodiment of the present invention are combined.

FIG. 14 is a schematic cross-sectional view of a manufacturing process showing the semiconductor device having the quaternary Schottky barrier diode according to the first embodiment of the present invention;

FIG. 15 is a schematic cross-sectional view of a manufacturing process showing a semiconductor device having a quaternary Schottky barrier diode according to a second embodiment of the present invention.

FIG. 16 shows a Schottky barrier diode of the present invention as 4
It is a top view which shows the semiconductor device which combined.

FIG. 17 is a view showing a semiconductor device having a Schottky barrier diode in groups of four according to a second embodiment of the present invention;
It is a schematic cross section showing an OI substrate.

FIG. 18 is a plan view showing a semiconductor device according to a twelfth embodiment of the present invention in which four Schottky barrier diodes are combined in a crossed manner.

FIG. 19 is a circuit diagram of a double balanced frequency mixing modulator according to a thirteenth embodiment of the present invention.

FIG. 20 is a data carrier circuit diagram serving as a power supply according to a fourteenth embodiment of the present invention.

FIG. 21 shows a receiving circuit including a signal processing circuit according to a fifteenth embodiment of the present invention.

FIG. 22 is a schematic sectional view showing a conventional Schottky barrier diode.

FIG. 23 is a schematic cross-sectional view showing a conventional semiconductor device having a quaternary Schottky barrier diode.

FIG. 24 is a schematic wiring diagram showing a semiconductor device in which four conventional Schottky barrier diodes are combined.

FIG. 25 is a schematic connection diagram showing a semiconductor device in which four conventional Schottky barrier diodes are combined.

FIG. 26 is a plan view showing a semiconductor device in which four conventional Schottky barrier diodes are combined.

FIG. 27 is a block diagram of a data carrier equipped with an acceleration sensor according to an eighteenth embodiment of the present invention.

FIG. 28 is a perspective view of an acceleration sensor section of a data carrier equipped with an acceleration sensor according to an eighteenth embodiment of the present invention.

FIG. 29 is a circuit diagram of an acceleration sensor unit of a data carrier equipped with an acceleration sensor according to an eighteenth embodiment of the present invention.

FIG. 30 is an output characteristic diagram of an acceleration sensor of a data carrier equipped with an acceleration sensor according to an eighteenth embodiment of the present invention.

FIG. 31 is a perspective view of an acceleration sensor section of a data carrier equipped with an acceleration sensor according to a nineteenth embodiment of the present invention.

FIG. 32 is a circuit diagram of an acceleration sensor unit of a data carrier equipped with an acceleration sensor according to a nineteenth embodiment of the present invention.

FIG. 33 is a block diagram of a data carrier equipped with a temperature sensor according to a nineteenth embodiment of the present invention.

FIG. 34 is a circuit diagram of a temperature sensor section of a data carrier equipped with a temperature sensor according to an eighteenth embodiment of the present invention.

FIG. 35 is an output characteristic diagram of a temperature sensor of a data carrier equipped with a temperature sensor according to an eighteenth embodiment of the present invention.

FIG. 36 is a block diagram of a data carrier according to a twentieth embodiment of the present invention.

FIG. 37 is a cross-sectional view of the twentieth embodiment of the present invention in which an acceleration sensor is mounted on a cylindrical system and vibration is measured.

FIG. 38 is a cross-sectional view of a sixteenth embodiment of the present invention when measuring vibration of a cylindrical system.

FIG. 39 is a schematic sectional view of a semiconductor device in which a gate and a substrate in a MOS transistor according to a fourteenth embodiment of the present invention are electrically wired so as to have the same potential.

FIG. 40 is an image diagram of a very small data carrier according to an eleventh embodiment of the present invention.

FIG. 41 is a schematic wiring diagram showing a semiconductor device in which four conventional Schottky barrier diodes are combined.

FIG. 42 is a schematic wiring diagram showing a semiconductor device in which four conventional Schottky barrier diodes are combined.

FIG. 43 is a schematic connection diagram showing a semiconductor device in which four MOS transistors of the present invention are combined.

FIG. 44 is a schematic connection diagram showing a semiconductor device in which four MOS transistors of the present invention are combined.

FIG. 45 is a schematic cross-sectional view of a MOS transistor according to a sixteenth embodiment of the present invention, in which a gate potential and a substrate potential are connected so as to have the same potential.

FIG. 46 is a schematic plan view of a MOS transistor according to a sixteenth embodiment of the present invention, in which a gate potential and a substrate potential are connected so as to have the same potential.

FIG. 47 is a schematic plan view of a MOS transistor according to a seventeenth embodiment of the present invention, in which a gate potential, a substrate potential, and a drain potential are connected so as to have the same potential.

FIG. 48 is a schematic plan view of a MOS transistor according to a seventeenth embodiment of the present invention, in which the gate potential, the substrate potential, and the drain potential are connected so as to have the same potential.

FIG. 49 is a wiring diagram of an n-channel MOS transistor having rectification characteristics.

FIG. 50 is a wiring diagram of a P-channel MOS transistor having rectification characteristics.

FIG. 51 is a circuit diagram of a charge pump according to a seventeenth embodiment of the present invention, which is configured by using a MOS transistor in which a gate potential, a substrate potential, and a drain potential are connected to have the same potential.

FIG. 52 is a diagram showing a seventeenth embodiment of the transmission circuit for operating a charge pump constituted by using MOS transistors in which a gate potential, a substrate potential, and a drain potential are connected to have the same potential. This is the created repetition signal.

FIG. 53 is a sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment of the present invention, in the order of manufacturing steps.

FIG. 54 is a sectional view of an SOI substrate used for the semiconductor device according to the second embodiment of the present invention;

FIG. 55 is a schematic sectional view showing a Schottky barrier diode according to a thirteenth embodiment of the present invention.

FIG. 56 is a schematic sectional view showing a Schottky barrier diode according to a thirteenth embodiment of the present invention.

FIG. 57 is a schematic battle view showing a semiconductor device in which four MOS transistors of the present invention are combined.

FIG. 58 is a circuit diagram of a DC-DC converter according to a twenty-first embodiment of the present invention.

FIG. 59 is a block diagram of a battery backup switching IC according to a twenty-second embodiment of the present invention.

FIG. 60 shows a MOS transistor according to the present invention and a conventional M transistor.
FIG. 4 is an operation characteristic diagram comparing OS transistors.

FIG. 61 is a circuit diagram of an overcurrent detection circuit according to the present invention.

FIG. 62 is a circuit diagram of a conventional overcurrent detection circuit.

FIG. 63 is a block diagram illustrating a system configuration of a tag unit of a data carrier.

FIG. 64 is a waveform diagram of each unit at the time of data reception of the tag unit of the data carrier.

FIG. 65 is a waveform diagram of each section when data is transmitted from the tag section of the data carrier.

FIG. 66 is a block diagram of a step-down DC-DC converter employing a synchronous rectification system according to a twenty-first embodiment of the present invention.

FIG. 67 shows a step-down DC according to a twenty-first embodiment of the present invention.
It is a block diagram of a DC converter.

FIG. 68 is a block diagram of a step-down DC-DC converter employing a synchronous rectification system according to a twenty-first embodiment of the present invention.

FIG. 69 is a cross-sectional view of the semiconductor device of the present invention.

FIG. 70 is a cross-sectional view of a conventional semiconductor device.

FIG. 71 is a graph showing a relationship between a gate voltage and a channel current of the semiconductor device of the present invention.

FIG. 72 is a sectional view of another embodiment of the present invention.

73 (a) is a plan view of another embodiment of the present invention, FIG. 73 (b) is a sectional view taken along line AA ′ of FIG. 73 (a), and FIG. 73 (c) is FIG. 73 is a cross-sectional view of FIG. 73 (a) taken along the line BB ′.

FIG. 74 is a sectional view of another embodiment of the present invention.

FIG. 75 is a sectional view of another embodiment of the present invention.

76 (a) is an electrical equivalent circuit diagram of the semiconductor device of the present invention, and FIG. 76 (b) is a waveform diagram of each terminal in FIG. 76 (a).

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 support substrate 2 n-type silicon substrate 3 Schottky metal 4 ohmic metal 5 n + -type high impurity region 6 n + -type impurity region 7 insulating film 8 SOI substrate 9 SiO 2 film 10 high-resistance polysilicon 11 electrode 12 source region 13 drain region Reference Signs List 14 gate electrode 15 p-type well 201 silicon substrate 202 high impurity region 203 Schottky metal 204 ohmic metal 205 silicon substrate 206 n-type silicon epitaxial layer 207 p + insulating film 5401 single-crystal Si 5402 diffusion layer 5403 SiO2 insulating film 5404 Si substrate 5501 Non-doped polySi 5601 Non-doped polySi

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 29/786 (31) Priority claim number Japanese Patent Application No. Hei 7-14738 (32) Priority date Heisei 7 January 31, 1995 (Jan. 31, 1995) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 7-79176 (32) Priority date April 4, 1995 (1995) (4.4) (33) Priority Country Japan (JP) (72) Inventor Masataka Shinogi 1-8-8 Nakase, Mihama-ku, Chiba City, Chiba Prefecture Inside Seiko Instruments Inc. (72) Inventor Keiji Sato Chiba Prefecture 1-8-8 Nakase, Mihama-ku, Chiba-shi Seiko Instruments Inc. (72) Inventor Yoshikazu Kojima 1-8-8 Nakase, Mihama-ku, Chiba-shi Seiko Instruments Inc. (72) Inventor Jun Koyamauchi Chiba 1-8-8 Nakase, Mihama-ku, Haha City F-term in Seiko Instruments Inc. BA16 BE04 5F110 AA09 AA30 BB04 BB11 CC02 DD03 DD05 DD13 DD24 EE24 GG02 GG12 GG13 GG32 GG34 GG42 GG47 GG60 HJ01 NN02 NN23 NN62 NN63 NN65 NN66 NN71 QQ17

Claims (5)

[Claims] 1. A semiconductor device comprising: a plurality of semiconductor substrates electrically separated on a supporting substrate; wherein the semiconductor substrate has a Schottky junction and an ohmic junction electrically connected to the Schottky junction. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said Schottky junction is made through high-resistance polysilicon. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon and has a plurality of intermediate transition levels of a plurality of levels between the Schottky electrode and the silicon.
13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of high-resistance polysilicon. 5. The semiconductor substrate is a silicon substrate,
Schottky junction of the silicon substrate, having a thickness 10Å or less of the SiO ₂ layer, and the high resistance polysilicon electrically connected to the SiO ₂ layer, an electrode electrically connected to the high resistance polysilicon The semiconductor device according to claim 1, wherein: