JPH0685184A - Integrated circuit of data carrier - Google Patents

Abstract

PURPOSE:To reduce the number of constituent parts of data carrier, by forming an equivalent diode wherein the source of an N-channel MOS transistor is made an equivalent cathode. CONSTITUTION:A P well 2 composed of P-type semiconductor is independently formed on the surface of a silicon wafer 1 being N-type semiconductor. Two N-type semiconductor regions 3, 4 are formed on the surface of the P well 2. A gate part member 6 is laminanted on the surface of the P well 2 between the two N-type semiconductor regions 3 and 4, so as to interpose a gate oxide film 5. This constitution is wholly the same as an N channel MOS transistor. An electrode is formed in the first N-type semiconductor region 3 and made an equivalent cathode 7. An electrode formed in the second N-type semiconductor region 4 is connected with the gate part member 6, and made an equivalent anode 8. A current can be made to flow or blocked according to the relation of the potentials of the two N-type semiconductor regions, so that an equivalent diode 9 can be constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data carrier for exchanging data with fixed facilities by radio waves or alternating magnetic fields, and more particularly to an integrated circuit used for the data carrier and its usage. is there. The data carrier mentioned here refers to an industrial data tag, a non-contact type IC card, a livestock individual identification mark, an electronic ticket, an electronic tag, an electronic key and the like.

[0002]

2. Description of the Related Art Although it is not limited to data carrier ICs, it has been extremely difficult to form a diode separated from a power supply line on the same chip at the same time as other circuit elements in a C-MOS-IC. Was said. FIG. 4 shows the structure of a diode commonly used in a conventional C-MOS-IC, and shows a cross section of an IC chip formed on an N-type semiconductor silicon wafer. On the drawing,
In (a), the cathode is the component substrate of the IC itself and cannot be separated from the positive power supply line. On the other hand, what is shown in (b) is P between the P- layer and the N + layer.
There is an N junction, but if you include the IC component substrate, N
It has a PN transistor structure. Therefore, the P
When the current Ib is applied to the N-junction, the current Ic flows from the N- layer to the N + layer.
Therefore, the PN junction cannot be used as a diode. Normally, this PN junction has a P-layer
It is used as a protection device for the input terminal of the IC by connecting to the negative power line of C.

[0003]

For the above reasons, in the conventional data carrier, the electric power induced in the coil by the electric wave or the alternating magnetic field sent from the fixed facility is rectified to be used as the power source or rectified and detected. It was necessary to prepare a diode necessary for receiving a signal by a separate device from the IC forming the main circuit of the data carrier. For this reason, there is an obstacle to downsizing and thinning of the device, and at the same time there is a problem in cost.

An object of the present invention is to reduce the number of data carrier components by mounting a rectifier diode for a power source and a diode for signal detection in an integrated circuit having a C-MOS structure including a main circuit of a data carrier. , Thereby achieving downsizing and thinning of the data carrier and cost reduction.

[0005]

In order to solve the above problems, according to the present invention, in an integrated circuit having a C-MOS structure formed on the surface of an N-type semiconductor, the integrated circuit is independently formed on the surface of the N-type semiconductor. Provided on the P well and an enhancement-type N-channel MOS formed on the P well
A drain and a gate of the N-channel MOS transistor are connected to form an equivalent anode while the P-well is in a floating state.
An equivalent diode having the source of the N-channel MOS transistor as an equivalent cathode was provided.

Further, C formed on the surface of the P-type semiconductor
In an integrated circuit having a MOS structure, an N-well independently provided on the surface of the P-type semiconductor and an enhancement-type P-channel MOS formed on the N-well
A drain and a gate of the P-channel MOS transistor are connected to form an equivalent cathode while the N-well is in a floating state.
An equivalent diode having the source of the P-channel MOS transistor as an equivalent anode was provided.

[0007]

The operation of the present invention can be explained by the sectional structure of the integrated circuit which is the most basic embodiment of the present invention shown in FIGS. 1 (a) and 1 (b). The operation of the above means will be described below with reference to FIG.

In FIG. 1A, a P well 2 made of a P type semiconductor is formed by an ion implantation method on the surface of a silicon wafer 1 which is an N type semiconductor serving as a circuit board of an IC. Two N-type semiconductor regions 3 and 4 are also formed on the surface of the well 2 by the ion implantation method. A gate member 6 is laminated on the surface of the P well 2 between the two N-type semiconductor regions 3 and 4 with a gate oxide film 5 of thin silicon oxide interposed therebetween. Such a structure is exactly the same as the N-channel MOS transistor. An electrode is provided in the first N-type semiconductor region 3 to serve as an equivalent cathode 7, and an electrode provided in the second N-type semiconductor region 4 is connected to the gate member 6 to serve as an equivalent anode 8. ing. On the other hand, ordinary C-MOS-I
In C, the P well 2 connected to the minus power supply line is provided independently and does not have any ohmic connection member.

In such a structure, the potential Vp of the P well 2 is not fixed and becomes substantially equal to the lower potential of the N type semiconductor regions 3 and 4. Now, assuming that the potential of the silicon wafer 1 is the reference potential V0, the potential of the equivalent anode 8 is Va, the potential of the equivalent cathode 7 is Vk, and V0>Va> Vk, the charge of the P well 2 is the first N It moves to the type semiconductor region 3 and becomes approximately Vp = Vk.
At this time, the first N-type semiconductor region 3 can be regarded as the source of the N-channel transistor, and the second N-type semiconductor region 4 can be regarded as the drain of the N-channel transistor. Further, since the gate member 6 is supplied with a potential Va that can be regarded as a drain voltage, the N-channel transistor is turned on, and a current flows from the equivalent anode 8 to the equivalent cathode 7. On the other hand, Va <Vk
Then, Vp = Va approximately, and at this time, the first N-type semiconductor region 3 is regarded as the drain of the N-channel transistor, and the second N-type semiconductor region 4 is regarded as the source. Further, the gate member 6 has a potential V that can be regarded as a source voltage.
Given a, the N-channel transistor turns off and blocks current. As described above, since the current can be passed or blocked depending on the potential of the two N-type semiconductor regions, it can be regarded as the equivalent diode 9.

In FIG. 1B, an N well 11 made of an N type semiconductor is formed by an ion implantation method on the surface of a silicon wafer 10 which is a P type semiconductor serving as a circuit board of an IC. Two P-type semiconductor regions 12 and 13 are also formed on the surface of the well 11 by the ion implantation method. The two P-type semiconductor regions 12
A gate member 15 is laminated on the surface of the N-well 11 between and 13 with a thin silicon oxide gate oxide film 14 interposed therebetween. Such a structure is exactly the same as the P-channel MOS transistor. First P-type semiconductor region 1
2 is provided with an electrode to serve as an equivalent anode 16, and the electrode provided to the second P-type semiconductor region 13 is connected to the gate member 15 to serve as an equivalent cathode 17. On the other hand, in a normal C-MOS-IC, the N well 11 connected to the positive power supply line is provided independently and does not have any ohmic connection member.

In such a structure, the potential Vn of the N well 11 is not fixed, and the P type semiconductor regions 12 and 1 are not fixed.
It becomes almost equal to the higher one of the three.
If the potential of the silicon wafer 10 is the reference potential V0, the potential of the equivalent cathode 17 is Vk, the potential of the equivalent anode 16 is Va, and V0 <Va <Vk, the charge of the second P-type semiconductor region 13 is set. Moves to N well 11 and is roughly Vn
= Vk. At this time, the first P-type semiconductor region 12 is P
It can be regarded as the drain of the channel transistor, and the second P-type semiconductor region 13 can be regarded as the source of the P-channel transistor. Also, the gate member 1
Since the potential Vk which can be regarded as the source voltage is applied to the P-channel transistor 5, the P-channel transistor is turned off and the current is blocked. On the other hand, if Va> Vk, then approximately Vn = Va, and at this time, the first P-type semiconductor region 12 is regarded as the source of the P-channel transistor and the second P-type semiconductor region 13 is regarded as the drain. Further, since the gate member 15 is supplied with the potential Va that can be regarded as a drain voltage, the P-channel transistor is turned on and a current flows from the equivalent anode 16 to the equivalent cathode 17. As described above, since the current can be passed or blocked depending on the potential of the two P-type semiconductor regions, it can be regarded as the equivalent diode 18.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the most basic embodiment of the present invention, the construction and operation of which are as described above.

FIG. 2 shows a circuit example of an electromagnetic coupling type data carrier according to the present invention, which is one of the embodiments of the present invention. In the drawing, the portion surrounded by the alternate long and short dash line is included in the IC formed on the N-type semiconductor, and is connected to the external circuit by the bonding pads P1, P2, P3, and P4. The IC includes a C-MOS data carrier main circuit, an N-channel transistor T1 as an equivalent diode for power supply rectification, an N-channel transistor T2 as an equivalent diode for signal detection, a capacitor CD and a resistor RD for signal detection, and It is composed of a P-channel transistor T3 for output modulation.

The positive power supply terminal of the data carrier main circuit is connected to the bonding pad P1 and serves as a reference potential line VDD. On the other hand, the negative side power supply terminal of the data carrier main circuit is connected to the bonding pad P4 to become the power supply line VSS, and is also connected to the gate and drain of the N-channel transistor T1 formed on the independent P well. The source of the transistor T1 is connected to the bonding pad P3, but the P well substrate is in a floating state without ohmic electrical connection. The bonding pad P3
Is connected to the source of an N-channel transistor T2 formed on an independent P well. The P well substrate of the transistor T2 is also in a floating state, but its gate and drain are connected to a time constant circuit composed of a capacitor CD and a resistor RD to form a signal detection circuit, the output signal of which is the data carrier main. It is the input of the circuit. The source and substrate of the P-channel transistor T3 are connected to the reference potential line VDD, and the drain is connected to the bonding pad P2. The gate is connected to the output terminal of the data carrier main circuit, and the transistor T3 is turned on / off by the output data of the data carrier.

The external circuit of the IC is a coil L, a resonance capacitor C1, a modulation capacitor C2, and a rectifying capacitor C3.
It consists of and. Coil L and resonance capacitor C1
Are connected in parallel to form a resonance circuit, one end of which is connected to the IC through the bonding pad P1. The other end of the resonance circuit is connected to the IC as an AC voltage line VAC via a bonding pad P3 and is also connected to one end of the modulation capacitor C2. The modulation capacitor C
The other end of 2 is connected to the bonding pad P2.
Bonding pads P1 and P4 which are power source terminals of the IC
A rectifying capacitor C3 is connected between the two and is used for stabilizing the power supply. In such a circuit configuration, when the data carrier receives a radio wave or an AC magnetic field emitted from a fixed facility of the data carrier system, AC power is induced in the resonant circuit and an AC voltage is generated in the AC voltage line VAC. The AC voltage is rectified by the N-channel transistor T1 functioning as an equivalent diode for rectification and becomes the power supply voltage of the data carrier main circuit. Further, the data transmitted by amplitude-modulating the radio wave or the AC magnetic field is demodulated by detecting the AC voltage by the N-channel transistor T2 which functions as an equivalent diode for signal detection, and is received by the data carrier main as received data. Is transmitted to the circuit. Output data from the data carrier is sent by amplitude-modulating the current of the coil L by turning on / off the P-channel transistor T3 and connecting or disconnecting the modulation capacitor C2 in parallel with the resonance circuit to change the resonance condition. Of.

FIG. 3 is also a circuit diagram showing the structure of an electromagnetic coupling type data carrier realized by the present invention, which is an embodiment of the present invention. This embodiment is a further practical improvement of the embodiment of FIG. 2, in which a level shift capacitor C4 is inserted in the AC voltage line VAC and a level shift diode D is provided between the bonding pads P1 and P3. There is. With this level shift circuit,
On the AC voltage line VAC in the IC, a voltage waveform in which a negative DC voltage having a magnitude equal to the amplitude of the AC voltage induced in the coil L is superimposed on the AC voltage is generated. This voltage is equivalent to the N-channel transistor T which is an equivalent diode.
The DC voltage obtained by rectifying at 1 can be doubled in the case of the embodiment of FIG. Similarly, if the signal is detected by the N-channel transistor T2, the magnitude of the detected output can be doubled.

Although the embodiments of the data carrier of FIGS. 2 and 3 have been described above, these circuits use an IC formed on an N-type semiconductor circuit board. Therefore, the equivalent diode used is represented by an N-channel MOS transistor as shown in FIG. If the constituent substrate of the IC is a P-type semiconductor, the equivalent diode used can be replaced with a P-channel MOS transistor as shown in FIG. Of course, at this time, the P-channel transistor T3 must be changed to an N-channel transistor.

[0018]

According to the present invention, the rectifying diode and the detecting diode can be formed on-chip by a normal method for manufacturing a C-MOS-IC without requiring a special step for manufacturing the IC. For this reason, the diode externally attached to the IC becomes unnecessary, and the number of parts can be reduced. Further, as a result, the structure of the data carrier is simplified, so that the data carrier can be downsized or thinned, and it becomes easy to realize a card type data carrier or an ultra-small data carrier. Further, the manufacturing process is simplified, and the reliability of the product is improved and at the same time the cost is reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an IC chip showing an embodiment of an integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a data carrier of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a data carrier of the present invention.

FIG. 4 is a cross-sectional view of a conventional integrated circuit.

[Description of Reference Signs] 1 silicon wafer 2 P-well 3 first N-type semiconductor region 4 second N-type semiconductor region 5 gate oxide film 6 gate member 7 equivalent cathode 8 equivalent anode 10 silicon wafer 11 N-well 12 second One P-type semiconductor region 13 Second P-type semiconductor region 14 Gate oxide film 15 Gate member 16 Equivalent anode 17 Equivalent cathode

Claims (6)

[Claims] 1. A CM formed on the surface of an N-type semiconductor.
An integrated circuit having an OS structure has a P-well independently provided on the surface of the N-type semiconductor and an enhancement-type N-channel MOS transistor formed on the P-well, and the P-well is in a floating state. The drain and gate of the N-channel MOS transistor are connected to form an equivalent anode.
An integrated circuit of a data carrier, comprising an equivalent diode having a source of a channel MOS transistor as an equivalent cathode. 2. The data carrier integrated circuit according to claim 1, wherein the equivalent diode is used as a signal detection diode. 3. The equivalent anode of an equivalent diode is connected to a power source terminal on the negative side of the integrated circuit, and the equivalent cathode is configured to be connectable to the outside of the integrated circuit via a bonding terminal. A coil is directly or indirectly connected between the positive power source terminal of the circuit and the bonding terminal, and the AC power induced in the coil is rectified by the equivalent diode. Power supply circuit for the described data carrier. 4. A CM formed on the surface of a P-type semiconductor.
An integrated circuit having an OS structure has an N well independently provided on the surface of the P type semiconductor and an enhancement type P channel MOS transistor formed on the N well, and the N well is in a floating state. The drain and gate of the P-channel MOS transistor are connected to form an equivalent cathode,
An integrated circuit of a data carrier, comprising an equivalent diode in which a source of a channel MOS transistor is an equivalent anode. 5. The integrated circuit of the data carrier according to claim 4, wherein the equivalent diode is used as a signal detection diode. 6. The integrated cathode of an equivalent diode is connected to a power source terminal on the plus side of the integrated circuit, and the equivalent anode is configured to be connectable to the outside of the integrated circuit via a bonding terminal. 5. A coil is directly or indirectly connected between the negative power supply terminal of the circuit and the bonding terminal, and the AC power induced in the coil is rectified by the equivalent diode. Power supply circuit for the described data carrier.