JP3501541B2 - Full-wave rectifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full-wave rectifier circuit for converting an AC signal into a DC signal, and is particularly suitable for application to a rectifier circuit used in a power source section of an IC card.

[0002]

2. Description of the Related Art In recent years, an IC card incorporating a microcomputer and an IC memory has been put into practical use. In such an IC card, an EEPROM is used as a non-volatile memory.
In some cases, most of the circuits including the logic section are composed of CMOS type integrated circuits.

On the other hand, there is a method using electromagnetic induction as a method of supplying electric power to such a built-in IC of an IC card. In this method, as shown in FIG. 8, between the load circuit 13 which is the main part of the card IC and the coil L, there are four rectifying elements connected in a bridge type and a smoothing capacitor C. A phase full-wave rectifier circuit is provided to rectify the AC current induced in the coil L according to the change in the magnetic field supplied from the outside and supply the rectified AC current to the load circuit 13.

[0004]

However, in the conventional IC card, a bipolar element such as a diode or a thyristor is used as a rectifying element.
It was relatively difficult to mount it on the same chip as the part of the load circuit 13 manufactured by the S process to form one chip.
Therefore, conventionally, the load circuit 1 which is the main part of the built-in IC has been used.
The rectifier circuit was formed on a chip different from the part of 3.

However, if the rectifier circuit portion is formed as a chip separate from the load circuit 13 in this way, a connection portion between them is required, which reduces the reliability of strength of the IC card and increases the number of assembling steps, resulting in high cost. However, there is a problem that the device built in the IC card becomes large.

On the other hand, if the rectifier circuit composed of the bipolar element is formed on the same chip as the load circuit 13, the manufacturing process becomes complicated and the cost of the chip itself increases.

Therefore, an object of the present invention is to provide a full-wave rectifier circuit which can be formed on the same chip as a CMOS type integrated circuit in an IC card without complicating the manufacturing process.

[0008]

In order to solve the above-mentioned problems, a full-wave rectifier circuit according to the present invention is a p-type semiconductor substrate.
And a first n-channel MOSFE formed on the surface of the p-type semiconductor substrate, the drain and the gate of which are both connected to the second output terminal and the source of which is connected to the first input terminal.
T and a second n-channel MO formed on the surface of the p-type semiconductor substrate, having a drain and a gate both connected to the second output terminal and a source connected to the second input terminal.
And SFET, formed on the surface of the p-type semiconductor substrate, drain and gate are both connected to said first input terminal, a third n-channel MOSFET having a source connected to the first output terminal, said p Formed on the surface of semiconductor substrate
A fourth n-channel MOSFET having a drain and a gate both connected to the second input terminal and a source connected to the first output terminal; the first output terminal and the second output terminal; And a ripple filter capacitor connected between the second output terminal and the p-type
At least the first n-channel connected to the semiconductor substrate
MOSFET and the second n-channel MOSFET
Threshold voltage is in the range of 50 to 200 mV
It is characterized by being set .

Another full-wave rectifier circuit according to the present invention is a p-type
A semiconductor substrate and a surface of the p-type semiconductor substrate,
A first n-channel MOSFET having a drain connected to the second output terminal, a source connected to the first input terminal, and a gate connected to the second input terminal; and the p-type semiconductor
Formed on the surface of the substrate, the drain is connected to the second output terminal, the source is connected to the second input terminal,
A second n-channel MOSFET having a gate connected to the first input terminal and formed on the surface of the p-type semiconductor substrate
A third n-channel MOSFET having a drain and a gate both connected to the first input terminal and a source connected to the first output terminal, and a surface of the p-type semiconductor substrate.
A fourth n-channel MOSFET having a drain and a gate both connected to the second input terminal and a source connected to the first output terminal, the first output terminal and the second and a ripple filter capacitor connected between the output terminal, the second output terminal before
Connected to the p-type semiconductor substrate and at least the first n-type
Channel MOSFET and the second n-channel MOS
The threshold voltage of the FET is 50 to 200 mV
It is characterized by being set in the range .

[0010]

[0011]

[0012]

[0013]

In the present invention, since four n-channel MOSFETs are connected in a bridge type to form a rectifier circuit, the rectifier circuit can be manufactured by the MOS process.
The rectifier circuit can be formed relatively easily on the same chip as a CMOS type integrated circuit such as a card IC, without complicating the manufacturing process.

Further, by setting the threshold voltage of the first n-channel MOSFET and the second n-channel MOSFET of the four n-channel MOSFETs to a relatively low range of 50 to 200 mV, respectively, the p-type substrate is formed. The amount of current flowing through the parasitic diode, which is formed between the n-type impurity diffusion layer and the n-type impurity diffusion layer and is forward-biased, can be minimized.

Further, the gate of the first n-channel MOSFET is connected to the second input terminal instead of the drain, and the second
By connecting the gates of the n-channel MOSFETs to the first input terminal again rather than the drain, the voltage drop across those MOSFETs can be made smaller.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS.

FIG. 1 shows an IC according to the first embodiment of the present invention.
FIG. 3 shows the circuit configuration of a single-phase full-wave rectifier circuit for a card, and the element structure of its transistor portion is shown in FIG.

As shown in FIG. 4, when the IC card 2 of this embodiment is inserted into a slot of a dedicated terminal, for example, I
The coil L in the C card 2 and the coil provided in the fixed station 1 in the dedicated terminal come close to each other, and by the electromagnetic coupling of both coils, AC power is taken from the fixed station 1 into the IC card 2 and built in. Supplied to IC3.

As shown in FIG. 1, both ends of the coil L to capture the AC signal by electromagnetic induction are respectively connected to the input terminal P _1, P _2, input terminals P _1, P ₂ and the output terminal O
Four n-channel MOS transistors Tr _{1 to} Tr ₄ are provided between ₁ and O ₂ in a bridge type. A ripple filter capacitor C forming a smoothing circuit is connected between the output terminals O ₁ and O ₂ .
The load circuit 13 connected between the output terminals O ₁ and O ₂ is
A main circuit that processes various signals in the IC card.
This is a load when viewed from the rectifier circuit of this embodiment. Further, the output terminal O ₂ is set to the reference potential common to the load circuit 13, that is, the substrate potential of the p-type silicon substrate of FIG.

Four MOS transistors Tr _{1 to} Tr ₄
Of these, the MOS transistors Tr ₁ and Tr ₂ have their drains and gates both connected to the output terminal O ₂ , and the source of the MOS transistor Tr ₁ is the input terminal P ₁
The source of the MOS transistor Tr ₂ is the input terminal P ₂
Connected to each. On the other hand, the MOS transistor Tr
The sources of ₃ and Tr ₄ are both connected to the output terminal O ₁ , and the drain and gate of the MOS transistor Tr ₃ are both connected to the input terminal P ₁ and the MOS transistor Tr _{4 is connected.}
Both the drain and the gate of are connected to the input terminal P ₂ .

As shown in FIG. 3, each of the four MOS transistors Tr _{1 to} Tr ₄ has an n ⁺ polycide gate structure, the gate oxide film thickness is 200 Å, and the surface substrate concentration is 2 × 10 ¹⁵ / cm 2. ³ , the threshold voltage is about 100m
V. The threshold voltage is adjusted by adjusting the gate oxide film thickness and the dose of impurities to the substrate.
It may be set appropriately in the range of 50 to 200 mV.

Further, each of the MOS transistors Tr _{1 to} Tr
_A pn junction diode (parasitic diode) occurs between the source / drain (n ⁺ ) of 4 and the substrate (p), respectively, but corresponds to the _four MOS transistors Tr _{1 to} Tr 4 in FIGS. 1 and 3. The parasitic diodes are referred to as D ₁ and D ₂ , D ₃ and D ₄ , D ₅ and D _6, and D ₇ and D ₈ , respectively.

Next, the operation of the single-phase full-wave rectifier circuit of this embodiment will be described.

As shown in FIG. 4, when an alternating current flows through the coil on the primary side in the fixed station 1, the IC is generated by electromagnetic induction.
An alternating current is generated in the coil L in the card 2, and the alternating current is input from the input terminals P ₁ and P ₂ .

At this time, as shown in FIG. 1, the input terminal P ₁
Is higher than the input terminal P ₂ , the current flows from the input terminal P ₁ to the input terminal P ₂ through the MOS transistor Tr ₃ , the capacitor C and the MOS transistor Tr ₂ . At this time, the MOS transistor Tr ₄
And the source of the MOS transistor Tr ₂ are
Since both of them have the same potential as the input terminal P ₂ , the potential becomes lower than the reference potential (substrate potential), and as a result, the parasitic diodes D ₇ and D ₄ are forward biased and current flows.

When a large current flows through the substrate through these parasitic diodes D ₄ and D ₇ , it causes a malfunction in which the electrodes which should not be conducted are electrically connected to each other. The current flowing from the substrate to the input terminal P ₂ through these parasitic diodes D ₄ and D ₇ is the n ⁺ diffusion layer in the portion of the MOS transistor Tr ₃ shown in FIG. 3, the p-type substrate and the source of the MOS transistor Tr ₂ or It can be considered as a current flowing through the npn parasitic transistor formed by the drain of the MOS transistor Tr ₂ and the n ⁺ diffusion layer, and should flow from the MOS transistor Tr ₃ through the capacitor C to the MOS transistor Tr ₂ in FIG. A part of the current flows through the npn parasitic transistor to the input terminal P ₂ directly without passing through the capacitor C. Therefore, the voltage of the capacitor C drops correspondingly, and the ripple becomes large, so that the rectification efficiency is lowered. Further, those currents also cause latch-up.

However, in this embodiment, those parasitic diodes D ₄ and D ₇ are provided between the substrate and the input terminal P _2.
The threshold voltage of the MOS transistor Tr ₂ that enters in parallel with the threshold voltage of the normal MOS transistor used for the MPU in the load circuit 13 or the memory is 0.
Approximately 100 mV, while it is set to 4 to 0.7 V
Therefore, the voltage drop in the portion of the MOS transistor Tr ₂ can be reduced, and the currents flowing through the parasitic diodes D ₄ and D ₇ can be made extremely small. In addition, the parasitic diode D ₄
And the current flowing through D ₇ becomes smaller, the voltage drop between the output terminal O ₂ (= substrate potential) and the input terminal P ₂ becomes smaller. The MOS transistor Tr ₂
The same effect can be obtained as long as the threshold voltage is within the range of 50 to 200 mV.

On the other hand, when the input terminal P ₂ has a higher potential than the input terminal P ₁ , the current flows from the input terminal P ₂ to the MOS.
It flows through the route returning to the input terminal P ₁ through the transistor Tr ₄ , the capacitor C and the MOS transistor Tr ₁ . Even at this time, the parasitic diode D ₅ of the parasitic diode D ₂ and the MOS transistor Tr ₃ of the MOS transistor Tr ₁ is biased respectively forward, but occurs quite similar problems, in this embodiment, MOS transistor Tr _Since the threshold voltage of ₁ is set to about 100 mV, the currents flowing through the parasitic diodes D ₂ and D ₅ can be extremely small.

In short, in this embodiment, the threshold voltage of the _four nMOS transistors Tr _{1 to} Tr 4 coupled in the bridge type is set to a range of 50 to 200 mV, which is lower than usual, so that, for example, a parasitic diode is formed. The amount of current flowing through is extremely small, and rectification efficiency is improved. For the purpose of minimizing the amount of current flowing through the parasitic diode, the four nMOS transistors Tr _{1 to} Tr _{4 are}
Only the threshold voltages of the two low-potential-side nMOS transistors Tr ₁ and Tr ₂ among them should be set within the range of 50 to 200 mV.

FIG. 2 shows operation waveforms of the single-phase full-wave rectifier circuit of this embodiment. In addition, in FIG. 2, the solid line shows the operating waveform under a light load, and the broken line shows the operating waveform under a heavy load.

2A shows the potential difference between both ends of the coil L, that is, the input terminals P ₁ and P ₂ , and FIG. 2B shows the input terminal P ₁ whose reference point is the reference potential GND. Electric potential, Figure 2
(C) shows an input terminal P ₂ with the reference potential GND as a reference point.
2D shows the difference between the potential V _DD of the output terminal O ₁ and the reference potential GND (potential of the output terminal O ₂ ), respectively.

[0032] When the input terminal P ₁ is a potential higher than P _2, the value obtained by subtracting the potential of the P ₂ from the potential of the P ₁ Moreover,, P ₁
The value obtained by subtracting the GND potential from the potential of 1 is positive, and the value obtained by subtracting the GND potential from the potential of P ₂ is slightly negative. This is because the MOS transistor Tr ₂ is interposed between the output terminal O ₂ and the input terminal P ₂ and a current flows through it. In this embodiment, the threshold voltage of the MOS transistor Tr ₂ is set low, and
As a result, the amount of current flowing through the parasitic diodes D ₄ and D ₇ is extremely small, so that the difference between the potential of P ₂ and the GND potential can be suppressed to a relatively small value. Therefore, the output voltage V _DD -GND can be increased. That is,
Since V _DD -GND = V _DD -P _2- (GND-P ₂ ), when P ₂ is at a low potential, the smaller the value of (GND-P ₂ ) is, the less the decrease of the output voltage V _DD -GND is. It can be said that it can be suppressed and the rectification efficiency is good. The same is true when the input terminal P ₂ has a higher potential than P ₁ .

FIG. 5 shows the circuit structure of a single-phase full-wave rectifier circuit for an IC card according to the second embodiment of the present invention, and FIG. 7 shows the element structure of its transistor part.

In this embodiment, the gates of n-channel MOS transistors Tr ₅ and Tr ₆ corresponding to the MOS transistors Tr ₁ and Tr ₂ of the first embodiment shown in FIG. 1 are connected to input terminals P ₂ and P ₁ , respectively. Except for this, it has the same configuration as the first embodiment shown in FIG. The junction diodes D _{13 to} D ₁₆ are MOS transistors Tr ₅ and Tr _6.
It is a parasitic diode.

Next, the operation of the single-phase full-wave rectifier circuit of the second embodiment will be described.

The input terminal P ₁ is at high potential than P _2, a high voltage is applied from the input terminal P ₁ to the gate of the MOS transistor Tr ₆ MOS transistor Tr ₆ is turned on. Therefore, the current flows from the input terminal P ₁ to the MOS transistor Tr ₃ , the capacitor C and the MOS transistor Tr.
It flows through the route returning to the input terminal P ₂ through ₆ . At this time, the parasitic diodes D ₇ and D ₁₆ are forward biased, respectively, and a current flows through these parasitic diodes D ₇ and D _16. However, in the present embodiment as well as in the case of the first embodiment described above, The threshold voltage of the transistor Tr ₆ is 50
Since the voltage is set in the range of ˜200 mV, the current flowing through the parasitic diodes D ₇ and D ₁₆ can be made extremely small. On the other hand, when the input terminal P ₂ has a higher potential than P ₁ , the input terminal P _{2 transfers} to the MOS transistor Tr ₅
High voltage is applied to the gate of the MOS transistor Tr
₅ is turned on, and the current flows from the input terminal P ₂ to the MOS transistor Tr ₄ , the capacitor C and the MOS transistor Tr.
It flows through the route returning to the input terminal P ₁ through ₅ . Also at this time, the threshold voltage of the MOS transistor Tr ₅ is 50 to
Since it is set in the range of 200 mV, the amount of current flowing through the forward-biased parasitic diodes D ₅ and D ₁₄ can be made extremely small.

In this embodiment, the high voltage from the input terminals P ₁ and P _{2 is} applied to the gates of the MOS transistors Tr ₆ and Tr ₅ , respectively, and the MOS transistors Tr ₆ and T ₅ are applied.
Since r ₅ is turned on, those MOS transistors T
The voltage drop across r ₆ and Tr ₅ is determined by the MOS of the first embodiment.
It can be made smaller than that of the transistors Tr ₂ and Tr ₁ . As a result, the current flowing through each parasitic diode can be further suppressed to a very small amount, and the potential difference between the output terminal O ₂ and the input terminals P ₂ and P ₁ on the low potential side can be reduced, which further increases the rectification efficiency. .

FIG. 6 shows operation waveforms of the single-phase full-wave rectifier circuit according to the second embodiment. Incidentally, also in FIG.
The solid line shows the operating waveform when the load is light, and the broken line shows the operating waveform when the load is heavy. Further, (a) to (d) of FIG.
(A) to (d) of FIG.

In this embodiment, the MOS transistor T
Since each of r ₅ and Tr ₆ operates in a completely ON state, the MOS transistor is different from the case of the first embodiment shown in FIG.
Since the voltage drop in the transistors Tr ₅ and Tr ₆ becomes small and the current flowing through each parasitic diode becomes extremely small, the input terminals P ₁ and P ₂ on the low potential side and the GND are connected.
The difference from the electric potential becomes smaller and the rectification efficiency improves.

[0040]

According to the present invention, a rectifier circuit is provided, for example,
It can be relatively easily formed on the same chip as a CMOS type integrated circuit such as a card IC without complicating the manufacturing process.

Two n-channel MOSs on the low potential side
By setting the threshold voltages of the FETs to relatively low ranges of 50 to 200 mV, respectively, the current flowing through the parasitic diode that is formed between the p-type substrate and the n-type impurity diffusion layer and is forward-biased is controlled. The amount can be made minute and the rectification efficiency can be improved.

Furthermore, two n-channel MOSs on the low potential side
By connecting the gates of the FETs to the input terminals on the high potential side for operation, the voltage drop in those MOSFETs can be made smaller, and the rectification efficiency can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a single-phase full-wave rectifier circuit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the single-phase full-wave rectifier circuit of FIG.

3 is a cross-sectional view showing the element structure of the single-phase full-wave rectifier circuit of FIG.

FIG. 4 is a conceptual diagram showing a method of supplying power to an IC card.

FIG. 5 is a circuit diagram showing a configuration of a single-phase full-wave rectifier circuit according to a second embodiment of the present invention.

6 is an operation waveform diagram of the single-phase full-wave rectifier circuit of FIG.

7 is a cross-sectional view showing an element structure of the single-phase full-wave rectifier circuit of FIG.

FIG. 8 is a circuit diagram of a conventional single-phase full-wave rectifier circuit.

[Explanation of symbols]

1 Fixed Station 2 IC Card 3 Built-in IC 13 Load Circuit L Coil P ₁ , P ₂ Input Terminal Tr ₁ ~ Tr ₆ n Channel MOS Transistor C Ripple Filter Capacitor O ₁ , O ₂ Output Terminal D ₁ ~ D ₈ , D ₁₃ ~ D ₁₆ pn junction diode (parasitic diode)

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 7/219 H01L 21/8234 H01L 27/088

Claims (2)

(57) [Claims] 1. A p-type semiconductor substrate and a first p-type semiconductor substrate formed on a surface of the p-type semiconductor substrate , wherein a drain and a gate are both connected to a second output terminal and a source is connected to a first input terminal. n-channel MOSFET
And a second n-channel MOSFE formed on the surface of the p-type semiconductor substrate, having a drain and a gate both connected to the second output terminal and a source connected to the second input terminal.
T and a third n-channel MOSFE formed on the surface of the p-type semiconductor substrate, having a drain and a gate both connected to the first input terminal and a source connected to the first output terminal.
T and a fourth n-channel MOS formed on the surface of the p-type semiconductor substrate, having a drain and a gate both connected to the second input terminal and a source connected to the first output terminal.
A ripple filter capacitor connected between the first output terminal and the second output terminal, wherein the second output terminal is connected to the p-type semiconductor substrate , and at least the first output terminal is connected to the p-type semiconductor substrate . 1 n-channel MOSFET and said
If the threshold voltage of the second n-channel MOSFET is
A full-wave rectifier circuit, which is also set in the range of 50 to 200 mV . 2. A p-type semiconductor substrate and a second drain formed on the surface of the p-type semiconductor substrate .
Of the first n-channel MOSFET connected to the output terminal of the p-type semiconductor substrate , the source connected to the first input terminal and the gate connected to the second input terminal, and the drain formed on the surface of the p-type semiconductor substrate. A second n-channel MOSFET connected to the second output terminal, a source connected to the second input terminal, and a gate connected to the first input terminal; and a surface of the p-type semiconductor substrate. A third n-channel MOSFE having a drain and a gate both connected to the first input terminal and a source connected to the first output terminal.
T and a fourth n-channel MOS formed on the surface of the p-type semiconductor substrate, having a drain and a gate both connected to the second input terminal and a source connected to the first output terminal.
A ripple filter capacitor connected between the first output terminal and the second output terminal, wherein the second output terminal is connected to the p-type semiconductor substrate , and at least the first output terminal is connected to the p-type semiconductor substrate . 1 n-channel MOSFET and said
If the threshold voltage of the second n-channel MOSFET is
A full-wave rectifier circuit, which is also set in the range of 50 to 200 mV .