JP2995778B2 - Integrated circuit - Google Patents

Integrated circuit

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Publication number
JP2995778B2
JP2995778B2 JP2024175A JP2417590A JP2995778B2 JP 2995778 B2 JP2995778 B2 JP 2995778B2 JP 2024175 A JP2024175 A JP 2024175A JP 2417590 A JP2417590 A JP 2417590A JP 2995778 B2 JP2995778 B2 JP 2995778B2
Authority
JP
Japan
Prior art keywords
integrated circuit
voltage
power supply
potential
circuit block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2024175A
Other languages
Japanese (ja)
Other versions
JPH03228366A (en
Inventor
二郎 小出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2024175A priority Critical patent/JP2995778B2/en
Publication of JPH03228366A publication Critical patent/JPH03228366A/en
Application granted granted Critical
Publication of JP2995778B2 publication Critical patent/JP2995778B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体集積回路の電子回路形成手法に関す
る。
Description: TECHNICAL FIELD The present invention relates to a method for forming an electronic circuit of a semiconductor integrated circuit.

[従来の技術] 従来より半導体集積回路の電源供給を少しでも容易に
すべく、半導体集積回路に電源用の電子回路を組み込む
ことは考えられていた。例えば直流電源系の電圧が著し
く異なる集積回路を電子機器に組み込む場合には、電子
機器の他の電子回路用電源と共存が可能となり、かつで
きる限り外付けの部品点数を減らす目的で集積回路の電
源入口に直流安定化電源回路を組むなどの試みがその好
例である。
[Prior Art] Conventionally, it has been considered to incorporate an electronic circuit for a power supply into a semiconductor integrated circuit in order to make the power supply of the semiconductor integrated circuit slightly easier. For example, when an integrated circuit having a significantly different voltage of the DC power supply system is incorporated in an electronic device, the integrated circuit can coexist with another electronic circuit power supply of the electronic device, and the number of external components can be reduced as much as possible. A good example is an attempt to build a DC stabilized power supply circuit at the power supply inlet.

[発明が解決しようとする課題] 現在ではチョッパ型電源技術の普及により商用電源か
ら所望の直流電源を作り出すことが容易になっている
が、電子機器への組み込みスペースは極めて大きいとい
わざるをえない。このような問題は軽薄短小化が好まれ
る今日においてはますます無視できない状況にある。
[Problems to be Solved by the Invention] At present, it is easy to produce a desired DC power supply from a commercial power supply due to the spread of chopper type power supply technology, but it can be said that the space for incorporation into electronic equipment is extremely large. Absent. Such a problem is increasingly not negligible in today's world where lightness and size are preferred.

本発明は、かかる技術課題を大幅に緩和するための集
積回路のあり方に目を向け、その課題の解決に有効な手
法を提供することを目的としている。
An object of the present invention is to provide an effective method for solving such a problem by focusing on an integrated circuit for greatly reducing such a technical problem.

[課題を解決するための手段] 本発明の集積回路は、半導体基板と、前記半導体基板
上に形成される絶縁膜と、前記絶縁膜上に形成されるP
型の半導体領域と、前記絶縁膜上に形成されかつ前記P
型の半導体領域と接するように配置されるN型の半導体
領域と、前記P型及びN型の半導体領域のそれぞれと接
続される配線層と、を有するダイオードよりなる整流手
段と、前記整流手段の出力電圧を平滑化する安定化電源
と、を備えることを特徴とする。
[Means for Solving the Problems] An integrated circuit according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a P formed on the insulating film.
A semiconductor region formed on the insulating film, and
A rectifier comprising a diode having an N-type semiconductor region arranged to be in contact with the semiconductor region of the type, and a wiring layer connected to each of the P-type and N-type semiconductor regions; And a stabilized power supply for smoothing the output voltage.

[実施例] 以下具体的実施例をとおして本発明の作用を説明す
る。
[Examples] Hereinafter, the operation of the present invention will be described through specific examples.

第1図は本発明の基本構成図である。図中1は整流手
段、2は集積回路ブロック、3,4は商用電源(交流)入
力端子、5は集積回路ブロックの高電位電源線、6は集
積回路ブロックの低電位電源線、7は電源安定化手段で
ある。
FIG. 1 is a basic configuration diagram of the present invention. In the figure, 1 is a rectifier, 2 is an integrated circuit block, 3 and 4 are commercial power (AC) input terminals, 5 is a high-potential power line of the integrated circuit block, 6 is a low-potential power line of the integrated circuit block, and 7 is a power supply. It is a stabilizing means.

商用電源が3,4の入力端子に印加されると、商用電源
は整流手段1によって整流され、商用電源の周波数もし
くはその2倍の周波数の変動を有する準直流電圧(脈
流)に変換される。そしてその準直流電圧は電源安定化
手段7により、平滑化・適正化される。
When the commercial power is applied to the input terminals 3 and 4, the commercial power is rectified by the rectifier 1 and converted into a quasi-DC voltage (pulsating current) having a fluctuation of the frequency of the commercial power or twice the frequency of the commercial power. . The quasi DC voltage is smoothed and optimized by the power supply stabilizing means 7.

一方集積回路ブロック2は電源安定化手段7によって
平滑化・適正化された電圧が印加され、動作する。
On the other hand, the voltage smoothed and optimized by the power supply stabilizing means 7 is applied to the integrated circuit block 2 to operate.

また電源安定化手段7については例えば集積プロセス
がバイポーラ素子工程なら、安定化回路として電圧制御
素子にバイポーラ素子を、定電圧発生回路としてバンド
ギャップリファレンス回路や、ツエナダイオード回路、
誤差電圧増幅回路として演算増幅器のような差動電圧増
幅回路を形成すればよく、CMOS等のプロセス工程であれ
ば、基準電圧発生回路としてゲート材料の仕事関数差発
生回路、CMOS差動増幅回路を形成すればよく、きわめて
容易に集積化することが可能である。
For the power supply stabilizing means 7, for example, if the integration process is a bipolar element process, a bipolar element is used as a voltage control element as a stabilizing circuit, a band gap reference circuit, a zener diode circuit,
It is sufficient to form a differential voltage amplifier circuit such as an operational amplifier as an error voltage amplifier circuit, and in the case of a process such as CMOS, a work function difference generation circuit of a gate material and a CMOS differential amplifier circuit are used as reference voltage generation circuits. It can be formed and can be integrated very easily.

以上のように整流手段、電源安定化手段を集積化する
ことにより、集積回路全体に商用電源を印加することが
可能になる。
By integrating the rectifying means and the power stabilizing means as described above, it becomes possible to apply commercial power to the entire integrated circuit.

第2図は本発明の具体的構成例を示す。1′は整流手
段、2は集積回路ブロック、3′,4′は商用電源入力端
子、5は集積回路ブロック2の高電位電源線、6は集積
回路ブロック2の低電位電源線、7は電源安定化手段、
8,9,10,11は集積回路ブロックと同一基板上に形成され
たpn接合ダイオードである。ここで整流手段1′はpn接
合ダイオード8〜11によって構成され、両波整流、即ち
3′,4′の入力端子に印加された商用電源の電圧極性が
時間と共に正電圧、負電圧に入れ替わる周期に同期して
整流動作を行う。まず商用電源が3′に正電圧、4′に
負電圧という状態で印加された場合を考えると、3′か
ら入った正電圧はダイオード8のアノードに加わる。そ
してダイオード8のカソードから流出した電流は電源安
定化手段7の高電位側電源線5−>電源安定化手段の内
部−>電源安定化手段7の低電位側電源線6の経路を経
てダイオード10のアノードに入る。ダイオード10はこの
とき順方向(即ち電流を流す方向)に電圧印加されるた
め、導通し、ダイオード10のカソードから4′の商用電
源(負電圧)へと流れ込む。
FIG. 2 shows a specific configuration example of the present invention. 1 'is a rectifying means, 2 is an integrated circuit block, 3' and 4 'are commercial power input terminals, 5 is a high potential power supply line of the integrated circuit block 2, 6 is a low potential power supply line of the integrated circuit block 2, and 7 is a power supply. Stabilization means,
8, 9, 10, and 11 are pn junction diodes formed on the same substrate as the integrated circuit block. Here, the rectifying means 1 'is constituted by pn junction diodes 8 to 11, and is a double-wave rectification, that is, a period in which the voltage polarity of the commercial power supply applied to the input terminals of 3' and 4 'is switched over time with a positive voltage and a negative voltage. The rectification operation is performed in synchronization with. First, when a commercial power supply is applied with a positive voltage at 3 'and a negative voltage at 4', the positive voltage input from 3 'is applied to the anode of the diode 8. The current flowing out of the cathode of the diode 8 passes through the path of the high-potential-side power supply line 5 of the power supply stabilizing means 5-> the inside of the power supply stabilizing means-> the low-potential power supply line 6 of the power supply stabilizing means 7. Enter the anode. At this time, the voltage is applied to the diode 10 in the forward direction (that is, the direction in which the current flows), so that the diode 10 conducts and flows from the cathode of the diode 10 to the 4 'commercial power supply (negative voltage).

次に逆の動作を考える。即ち商用電源が4′に正電
圧、3′に負電圧という状態で印加された場合を考える
と、4′から入った正電圧はダイオード9のアノードに
加わる。そしてダイオード9のカソードから流出した電
流は集積回路ブロック2の高電位側電源線5−>集積回
路ブロック内部−>集積回路ブロック2の低電位側電源
6の経路を経てダイオード11のアノードに入る。ダイオ
ード11はこのとき順方向(即ち電流を流す方向)に電圧
印加されるため、導通し、ダイオード11のカソードから
3′の商用電源(負電圧)へと流れ込む。以上の説明か
ら明らかなように商用電源の電圧極性の交番動作に合わ
せ、ダイオード8〜11で構成される整流手段が集積回路
ブロック2にかかる電源の極性を一方向に揃えるため、
集積回路ブロック2は正常に動作することが可能にな
る。
Next, consider the reverse operation. That is, considering the case where the commercial power supply is applied with a positive voltage at 4 'and a negative voltage at 3', the positive voltage input from 4 'is applied to the anode of the diode 9. The current flowing out of the cathode of the diode 9 enters the anode of the diode 11 through the path of the high-potential power supply line 5-> inside the integrated circuit block-> the low-potential power supply 6 of the integrated circuit block 2 of the integrated circuit block 2. At this time, the voltage is applied to the diode 11 in the forward direction (that is, the direction in which the current flows), so that the diode 11 conducts and flows from the cathode of the diode 11 to the 3 'commercial power supply (negative voltage). As is apparent from the above description, the rectifier composed of the diodes 8 to 11 aligns the polarity of the power supply applied to the integrated circuit block 2 in one direction in accordance with the alternating operation of the voltage polarity of the commercial power supply.
The integrated circuit block 2 can operate normally.

第3図は第2図に示した整流手段の集積平面図であ
る。図中3″,4″は商用電源入力用金属配線、5′は集
積回路ブロックの高電位供給用金属配線、6′は集積回
路ブロックの低電位供給用金属配線、31,32は絶縁層上
に形成された半導体領域、33,34,35,36は31,32の半導体
領域に形成されたpn接合境界、37,38,39,40,41,42は電
源用金属配線(3″,4″,5′,6′)と半導体領域31,32
とを電気的に接続するためのコンタクトホール(絶縁層
の穴)である。
FIG. 3 is an integrated plan view of the rectifying means shown in FIG. In the figure, 3 "and 4" are metal wirings for inputting commercial power, 5 'is a metal wiring for supplying a high potential of the integrated circuit block, 6' is a metal wiring for supplying a low potential of the integrated circuit block, and 31 and 32 are on the insulating layer. Semiconductor regions 33, 34, 35, and 36 are pn junction boundaries formed in the semiconductor regions 31 and 32, and 37, 38, 39, 40, 41, and 42 are metal wirings for power supply (3 ″, 4 ″, 5 ′, 6 ′) and semiconductor regions 31,32
And a contact hole (a hole in an insulating layer) for electrically connecting the.

第4図は整流手段集積部の断面図である。図中4″は
商用電源入力用金属層、5′は集積回路ブロックの高電
位供給用金属配線、6′は集積回路ブロックの低電位供
給用金属配線、51は集積回路形成用半導体基板、52はシ
リコン酸化絶縁膜、43,44は絶縁膜52の上に形成された
半導体領域、45,46,47,48は金属配線層との電気的接続
のためのコンタクトホール、49は半導体領域43,44と金
属配線層を電気的に分離するための絶縁膜、50は半導体
集積回路の最終工程で形成される不活性化膜(パシベー
ション膜)である。
FIG. 4 is a cross-sectional view of the rectifying means integrated portion. In the figure, 4 "is a metal layer for inputting commercial power, 5 'is a metal wiring for supplying a high potential of the integrated circuit block, 6' is a metal wiring for supplying a low potential of the integrated circuit block, 51 is a semiconductor substrate for forming an integrated circuit, 52 Is a silicon oxide insulating film, 43 and 44 are semiconductor regions formed on the insulating film 52, 45, 46, 47 and 48 are contact holes for electrical connection with a metal wiring layer, and 49 is a semiconductor region 43 and An insulating film 44 for electrically separating 44 and the metal wiring layer, and 50 is a passivation film (passivation film) formed in the final step of the semiconductor integrated circuit.

このように絶縁層の上に整流手段を形成するのは、整
流用の半導体素子を基板41から完全に絶縁分離し、寄生
ダイオードを排除するためである。従って例えばSOS(s
ilicon on saphire)、SOI(silicon on insulator)、
SIPOX(silicon implanted oxidation)などと呼ばれる
絶縁分離技術においてはさらに簡便な構造で実現するこ
とができる。なぜならそれらはpn接合の逆方向バイアス
による素子分離ではなく、電気的に完全独立した素子群
を絶縁性の基板上に形成できるからである。
The reason why the rectifying means is formed on the insulating layer is to completely insulate and separate the semiconductor element for rectification from the substrate 41 and eliminate a parasitic diode. So, for example, SOS (s
ilicon on saphire), SOI (silicon on insulator),
In an insulation isolation technique called SIPOX (silicon implanted oxidation) or the like, it can be realized with a simpler structure. This is because they can form an electrically independent element group on an insulating substrate instead of element isolation by a reverse bias of a pn junction.

第5図は本発明における電圧安定化手段の一構成例で
ある。図中51は整流手段からの高電位電圧入力端子、52
は整流手段からの低電位電圧入力端子、53は演算増幅
器、54は基準電圧源、55はMOS電界効果トランジスタ、5
6,57は抵抗器、58は安定化された高電位電源出力端子、
59は低電位電源出力端子である。ここでは入力端子51か
ら加えられた不安定な電源電圧がMOS電界効果トランジ
スタ55を介して出力端子58に伝えられるが、出力端子58
に現われる電圧が分割抵抗56,57により定められた電圧
値に比べて高い値である時、分割抵抗57に発生する電圧
降下量が設定値、すなわち基準電圧源54の値より大きく
なる。そのため基準電圧源54の出力電圧と分割抵抗57に
発生する電圧との差分が、演算増幅器53により増幅さ
れ、MOS電界効果トランジスタ55のゲート電圧として印
加される。今の説明の場合、分割抵抗57に発生する電圧
量が基準電圧源54の出力より大きいため、演算増幅器の
反転入力電圧<非反転入力電圧となり、演算増幅器の出
力電圧は高電位電源を出力するように動作する。従って
MOS電界効果トランジスタ55のゲート電位は高電位、つ
まり不安定な整流手段高電位電圧付近まで近付くため、
ソース電位とゲート電位との落差が小さくなり、電界効
果トランジスタ55は導通抵抗が増加するようになる。そ
の結果58の出力端子の電圧を低く抑えるように作用す
る。仮に入力電圧が設定電圧より低くなると、今までの
説明と正反対に動作し、電界効果トランジスタ55の導通
抵抗が低くなるように作用する。このような動作の繰り
返しにより、整流手段からの出力電圧は安定化され出力
端子58には集積回路の動作にふさわしい安定した電圧が
得られる。
FIG. 5 shows an example of the configuration of the voltage stabilizing means in the present invention. In the figure, 51 is a high-potential voltage input terminal from the rectifier, 52
Is a low potential voltage input terminal from the rectifier, 53 is an operational amplifier, 54 is a reference voltage source, 55 is a MOS field effect transistor, 5
6, 57 is a resistor, 58 is a stabilized high-potential power output terminal,
59 is a low potential power output terminal. Here, the unstable power supply voltage applied from the input terminal 51 is transmitted to the output terminal 58 via the MOS field-effect transistor 55.
Is higher than the voltage value determined by the divided resistors 56 and 57, the amount of voltage drop generated in the divided resistor 57 becomes larger than the set value, that is, the value of the reference voltage source 54. Therefore, the difference between the output voltage of the reference voltage source 54 and the voltage generated at the dividing resistor 57 is amplified by the operational amplifier 53 and applied as the gate voltage of the MOS field effect transistor 55. In the case of the present description, since the amount of voltage generated in the dividing resistor 57 is larger than the output of the reference voltage source 54, the inverting input voltage of the operational amplifier <the non-inverting input voltage, and the output voltage of the operational amplifier outputs the high potential power supply. Works like that. Therefore
Since the gate potential of the MOS field-effect transistor 55 approaches a high potential, that is, the vicinity of the unstable rectifier high potential voltage,
The drop between the source potential and the gate potential is reduced, and the conduction resistance of the field effect transistor 55 increases. As a result, the voltage at the output terminal 58 acts to be kept low. If the input voltage becomes lower than the set voltage, the operation is performed in a manner opposite to the above description, and the conduction effect of the field effect transistor 55 is reduced. By repeating such operations, the output voltage from the rectifier is stabilized, and a stable voltage suitable for the operation of the integrated circuit is obtained at the output terminal 58.

[発明の効果] 以上説明してきたように本発明を実施すれば直流電源
を電子機器に組み込む必要性が極めて低くなり、電子機
器の高密度組立が容易になる。
[Effects of the Invention] As described above, when the present invention is implemented, the necessity of incorporating a DC power supply into an electronic device is extremely reduced, and high-density assembly of the electronic device is facilitated.

また本発明によれば従来の集積回路のように、電源の
電圧印加方法を誤って集積回路を破壊させることを防止
することができる。
Further, according to the present invention, it is possible to prevent the integrated circuit from being erroneously destroyed as in the case of a conventional integrated circuit.

本発明は広範囲に応用できる。例えば自動車に搭載す
る電子機器ではエンジンの動力で発電された交流電圧を
直接利用することが可能になる。またその他電気釜、電
気掃除機、電気洗濯機等など日常の家庭電化製品につい
てはそのほとんどに応用がきく。また太陽電池駆動式電
子機器に利用すれば太陽電池パネルの出力電圧の安定化
作用と同時に、組み込む場合の太陽電池パネルの電極接
続ミスによる集積回路の破壊を防止でき、かつ逆接続に
よっても支障なく電子機器が動作できるようになる。こ
れはメンテナンス性能を著しく向上させる一例である。
また一部の電子時計にみられる自動巻機構による交流発
電、電子回路駆動のメカニズムをより広くその他の携帯
機器に応用できるようになる。
The invention has a wide range of applications. For example, an electronic device mounted on an automobile can directly use an AC voltage generated by the power of an engine. In addition, most home electric appliances such as electric kettles, vacuum cleaners, electric washing machines, etc. can be applied to most of them. In addition, when used in solar cell driven electronic devices, the output voltage of the solar panel can be stabilized, and at the same time, the integrated circuit can be prevented from being damaged due to a mistake in the electrode connection of the solar panel when incorporated. The electronic device can operate. This is an example that significantly improves maintenance performance.
In addition, the mechanism of AC power generation and electronic circuit drive by an automatic winding mechanism found in some electronic timepieces can be widely applied to other portable devices.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の基本構成図、第2図は本発明の具体的
構成例の図、第3図は本発明の集積回路平面図、第4図
は本発明の集積回路断面図、第5図は本発明の電源安定
化手段の一構成図である。 図中 1,1′……整流手段 2,2′,2″……集積回路ブロック 3,3′,3″……商用電源入力端子 4,4′,4″……商用電源入力端子 5,5′,5″……集積回路ブロック高電位線 6,6′,6″……集積回路ブロック低電位線 7……電源安定化手段 31,32……絶縁膜上の半導体領域 43,44……絶縁膜上の半導体領域 53……演算増幅器 54……基準電圧源 55……MOS電界効果トランジスタ 56,57……抵抗器
FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a diagram of a specific configuration example of the present invention, FIG. 3 is a plan view of an integrated circuit of the present invention, FIG. FIG. 5 is a configuration diagram of the power supply stabilizing means of the present invention. In the figure, 1,1 '... rectifying means 2, 2', 2 "... integrated circuit block 3, 3 ', 3" ... commercial power input terminal 4, 4', 4 "... commercial power input terminal 5, 5 ', 5 "... High potential line of integrated circuit block 6,6', 6" ... Low potential line of integrated circuit block 7 ... Power supply stabilizing means 31,32 ... Semiconductor area on insulating film 43,44 ... ... Semiconductor area on insulating film 53 ... Operational amplifier 54 ... Reference voltage source 55 ... MOS field effect transistor 56,57 ... Resistor

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/822 H01L 21/8222 H01L 27/04 H01L 27/06 H01L 29/861 ──────────────────────────────────────────────────続 き Continued on the front page (58) Surveyed fields (Int.Cl. 6 , DB name) H01L 21/822 H01L 21/8222 H01L 27/04 H01L 27/06 H01L 29/861

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板と、前記半導体基板上に形成さ
れる絶縁膜と、前記絶縁膜上に形成されるP型の半導体
領域と、前記絶縁膜上に形成されかつ前記P型の半導体
領域と接するように配置されるN型の半導体領域と、前
記P型及びN型の半導体領域のそれぞれと接続される配
線層と、を有するダイオードよりなる整流手段と、前記
整流手段の出力電圧を平滑化する安定化電源と、を備え
ることを特徴とする集積回路。
1. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a P-type semiconductor region formed on the insulating film, and a P-type semiconductor region formed on the insulating film. A rectifier comprising a diode having an N-type semiconductor region disposed in contact with the semiconductor device, and a wiring layer connected to each of the P-type and N-type semiconductor regions; and smoothing an output voltage of the rectifier. And a stabilized power supply.
JP2024175A 1990-02-02 1990-02-02 Integrated circuit Expired - Lifetime JP2995778B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024175A JP2995778B2 (en) 1990-02-02 1990-02-02 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2024175A JP2995778B2 (en) 1990-02-02 1990-02-02 Integrated circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11203624A Division JP2000069755A (en) 1999-07-16 1999-07-16 Rectifying circuit and semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH03228366A JPH03228366A (en) 1991-10-09
JP2995778B2 true JP2995778B2 (en) 1999-12-27

Family

ID=12131016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024175A Expired - Lifetime JP2995778B2 (en) 1990-02-02 1990-02-02 Integrated circuit

Country Status (1)

Country Link
JP (1) JP2995778B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101055772B1 (en) 2005-12-15 2011-08-11 서울반도체 주식회사 Light emitting device
KR100875443B1 (en) 2006-03-31 2008-12-23 서울반도체 주식회사 Light emitting device

Also Published As

Publication number Publication date
JPH03228366A (en) 1991-10-09

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