JP2000069755A - Rectifying circuit and semiconductor integrated circuit - Google Patents

Rectifying circuit and semiconductor integrated circuit

Info

Publication number
JP2000069755A
JP2000069755A JP11203624A JP20362499A JP2000069755A JP 2000069755 A JP2000069755 A JP 2000069755A JP 11203624 A JP11203624 A JP 11203624A JP 20362499 A JP20362499 A JP 20362499A JP 2000069755 A JP2000069755 A JP 2000069755A
Authority
JP
Japan
Prior art keywords
integrated circuit
power supply
voltage
rectifying
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11203624A
Other languages
Japanese (ja)
Inventor
Jiro Koide
二郎 小出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11203624A priority Critical patent/JP2000069755A/en
Publication of JP2000069755A publication Critical patent/JP2000069755A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/56Power conversion systems, e.g. maximum power point trackers

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Rectifiers (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate production of a high density electronic apparatus by forming a pn junction rectifying means and a voltage stabilizing means on a thin isolation film between an integrated circuit board for forming an electronic circuit and a wiring layer thereby incorporating a DC power supply circuit in a semiconductor integrated circuit. SOLUTION: An electronic circuit for supplying an integrated circuit block 2 with DC power produced by rectifying and smoothing power from a commercial power supply applied to input terminals 3', 4' through a rectifying means 1' and a power supply stabilizing means 7 is constituted of a semiconductor integrated circuit. The rectifying means 1' is formed as pn junction diodes 8-11 in a semiconductor region on a silicon oxide film isolating a semiconductor substrate for forming the integrated circuit block 2 from a wiring layer. Similarly the power supply stabilizing means 7 is integrated by an integration process. According to the arrangement, power can be applied directly from a commercial power to the entire integrated circuit.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路の電子回
路形成手法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an electronic circuit of a semiconductor integrated circuit.

【0002】[0002]

【従来の技術】従来より半導体集積回路の電源供給を少
しでも容易にすべく、半導体集積回路に電源用の電子回
路を組み込むことは考えられていた。例えば直流電源系
の電圧が著しく異なる集積回路を電子機器に組み込む場
合には、電子機器の他の電子回路用電源と共存が可能と
なり、かつできる限り外付けの部品点数を減らす目的で
集積回路の電源入口に直流安定化電源回路を組むなどの
試みがその好例である。
2. Description of the Related Art Conventionally, it has been considered to incorporate a power supply electronic circuit into a semiconductor integrated circuit in order to make it easier to supply power to the semiconductor integrated circuit. For example, when an integrated circuit having a significantly different voltage of the DC power supply system is incorporated in an electronic device, the integrated circuit can coexist with another electronic circuit power supply of the electronic device, and the number of external components can be reduced as much as possible. A good example is an attempt to build a DC stabilized power supply circuit at the power supply inlet.

【0003】[0003]

【発明が解決しようとする課題】現在ではチョッパ型電
源技術の普及により商用電源から所望の直流電源を作り
出すことが容易になっているが、電子機器への組み込み
スペースは極めて大きいといわざるをえない。このよう
な問題は軽薄短小化が好まれる今日においてはますます
無視できない状況にある。
At present, the spread of chopper type power supply technology makes it easy to produce a desired DC power supply from a commercial power supply. However, it can be said that the space for assembling into electronic equipment is extremely large. Absent. Such a problem is increasingly not negligible in today's world where lightness and size are preferred.

【0004】本発明は、かかる技術課題を大幅に緩和す
るための集積回路のあり方に目を向け、その課題の解決
に有効な手法を提供することを目的としている。
An object of the present invention is to provide an effective method for solving such a problem by focusing on an integrated circuit for greatly reducing such a technical problem.

【0005】[0005]

【課題を解決するための手段】本発明では課題解決の具
体的手段として、集積回路基板、前記集積回路基板上に
形成された電子回路、前記電子回路の製造過程において
形成される、前記集積回路基板と配線層との絶縁分離薄
膜、前記薄膜上に形成されるpn接合整流手段、前記整
流手段の出力を安定化する電圧安定化手段とを有し、前
記整流手殴のカソードは前記電圧安定化手段の高電位入
力端子に、前記整流手段のアノードは前記電圧安定化手
段の低電位入力端子に接続され、前記電子回路の電源が
前記電圧安定化手段の出力により与えられる。
According to the present invention, an integrated circuit substrate, an electronic circuit formed on the integrated circuit substrate, and the integrated circuit formed in a process of manufacturing the electronic circuit are concrete means for solving the problem. A thin film for insulating and separating a substrate and a wiring layer, a pn junction rectifying means formed on the thin film, and a voltage stabilizing means for stabilizing an output of the rectifying means; The anode of the rectifier is connected to the low potential input terminal of the voltage stabilizing means, and the power supply of the electronic circuit is provided by the output of the voltage stabilizing means.

【0006】ように配置したことを特徴とする。It is characterized by being arranged as described above.

【0007】[0007]

【実施例】以下具体的実施例をとおして本発明の作用を
説明する。
The operation of the present invention will be described below with reference to specific examples.

【0008】図1は本発明の基本構成図である。図中1
は整流手段、2は集積回路ブロック、3,4は商用電源
(交流)入力端子、5は集積回路ブロックの高電位電源
線、6は集積回路ブロックの低電位電源線、7は電源安
定化手段である。
FIG. 1 is a basic configuration diagram of the present invention. 1 in the figure
Is a rectifier, 2 is an integrated circuit block, 3 and 4 are commercial power (AC) input terminals, 5 is a high-potential power supply line of the integrated circuit block, 6 is a low-potential power supply line of the integrated circuit block, and 7 is power supply stabilizing means. It is.

【0009】商用電源が3,4の入力端子に印加される
と、商用電源は整流手段1によって整流され、商用電源
の周波数もしくはその2倍の周波数の変動を有する準直
流電圧(脈流)に変換される。そしてその準直流電圧は
電源安定化手段7により、平滑化・適正化される。
When the commercial power supply is applied to the input terminals 3 and 4, the commercial power supply is rectified by the rectifier 1 to a quasi-DC voltage (pulsating flow) having a fluctuation of the frequency of the commercial power supply or twice the frequency of the commercial power supply. Is converted. The quasi DC voltage is smoothed and optimized by the power supply stabilizing means 7.

【0010】一方集積回路ブロック2は電源安定化手段
7によって平滑化・適正化された電圧が印加され、動作
する。
On the other hand, the voltage smoothed and optimized by the power supply stabilizing means 7 is applied to the integrated circuit block 2 to operate.

【0011】また電源安定化手段7については例えば集
積プロセスがバイポーラ素子工程なら、安定化回路とし
て電圧制御素子にバイポーラ素子を、定電圧発生回路と
してバンドギャップリファレンス回路や、ツエナダイオ
ード回路、誤差電圧増幅回路として演算増幅器のような
差動電圧増幅回路を形或すればよく、CMOS等のプロ
セス工程であれば、基準電圧発生回路としてゲート材料
の仕事関数差発生回路、CMOS差動増幅回路を形成す
ればよく、きわめて容易に集積化することが可能であ
る。
For the power supply stabilizing means 7, for example, if the integration process is a bipolar element process, a bipolar element is used as a voltage control element as a stabilizing circuit, and a band gap reference circuit, a Zener diode circuit, an error voltage amplifying circuit as a constant voltage generating circuit. The circuit may be a differential voltage amplifier such as an operational amplifier. In the case of a process such as CMOS, a work function difference generator for a gate material and a CMOS differential amplifier may be formed as a reference voltage generator. And it can be very easily integrated.

【0012】以上のように整流手段、電源安定化手段を
集積化することにより、集積回路全体に商用電源を印加
することが可能になる。
By integrating the rectifying means and the power stabilizing means as described above, it becomes possible to apply commercial power to the entire integrated circuit.

【0013】図2は本発明の具体的構成例を示す。1’
は整流手段、2は集積回路ブロック、3’,4’は商用
電源入力瑞子、5は集積回路ブロック2の高電位電源
線、6は集積回路ブロック2の低電位電源線、7は電源
安定化手段、8,9,10,11は集積回路ブロックと
同一基枚上に形成されたpn接合ダイオードである。こ
こで整流手段1’はpn接合ダイオード8〜11によっ
て構成され、両波整流、即ち3’,4’の入力端子に印
加された商用電源の電圧極性が時間と共に正電圧、負電
圧に入れ替わる周期に同期して整流動作を行う。まず商
用電源が3’に正電圧、4’に負電圧という状態で印加
された場合を考えると、3’から入った正電圧はダイオ
ード8のアノードに加わる。そしてダイオード8のカソ
ードから流出した電流は電源安定化手段7の高電位側電
源線5−>電源安定化手段の内部−>電源安定化手段7
の低電位側電源線6の経路を経てダイオード10のアノ
ードに入る。ダイオード10はこのとき順方向(即ち電
流を流す方向)に電圧印加されるため、導通し、ダイオ
ード10のカソードから4’の商用電源(負電圧)へと
流れ込む。
FIG. 2 shows a specific configuration example of the present invention. 1 '
Is a rectifier, 2 is an integrated circuit block, 3 'and 4' are commercial power supply input lines, 5 is a high potential power line of the integrated circuit block 2, 6 is a low potential power line of the integrated circuit block 2, and 7 is power supply stabilization. Means 8, 9, 10, and 11 are pn junction diodes formed on the same substrate as the integrated circuit block. Here, the rectifying means 1 'is constituted by pn junction diodes 8 to 11, and is a double-wave rectification, that is, a period in which the voltage polarity of the commercial power supply applied to the input terminals 3' and 4 'is switched over time with a positive voltage and a negative voltage. The rectification operation is performed in synchronization with. First, considering the case where a commercial power supply is applied with a positive voltage at 3 'and a negative voltage at 4', the positive voltage input from 3 'is applied to the anode of the diode 8. The current flowing out of the cathode of the diode 8 is supplied to the high-potential-side power supply line 5 of the power supply stabilization means 7-> the inside of the power supply stabilization means-> the power supply stabilization means 7
And enters the anode of the diode 10 via the path of the low-potential-side power supply line 6. At this time, since a voltage is applied to the diode 10 in the forward direction (that is, the direction in which current flows), the diode 10 conducts, and flows from the cathode of the diode 10 to the 4 'commercial power supply (negative voltage).

【0014】次に逆の動作を考える。即ち商用電源が
4’に正電圧、3’に負電圧という状態で印加された場
合を考えると、4’から入った正電圧はダイオード9の
アノードに加わる。そしてダイオード9のカソードから
流出した電流は集積回路ブロック2の高電位側電源線5
−>集積回路ブロック内部−>集積回路ブロック2の低
電位側電源6の経路を経てダイオード11のアノードに
入る。ダイオード11はこのとき順方向(即ち電流を流
す方向)に電圧印加されるため、導通し、ダイオード1
1のカソードから3’の商用電源(負電圧)へと流れ込
む。以上の説明から明らかなように商用電源の電圧極性
の交番動作に合わせ、ダイオード8〜11で構成される
整流手段が集積回路ブロック2にかかる電源の極性を一
方同に揃えるため、集積回路ブロック2は正常に動作す
ることが可能になる。
Next, the reverse operation will be considered. That is, considering the case where the commercial power is applied with a positive voltage at 4 'and a negative voltage at 3', the positive voltage input from 4 'is applied to the anode of the diode 9. The current flowing out of the cathode of the diode 9 is applied to the high potential side power supply line 5 of the integrated circuit block 2.
-> Inside the integrated circuit block-> The anode of the diode 11 enters the path of the low potential side power supply 6 of the integrated circuit block 2. At this time, the voltage is applied to the diode 11 in the forward direction (that is, the direction in which the current flows), so that the diode 11 conducts,
1 flows into the 3 'commercial power supply (negative voltage) from the cathode. As is apparent from the above description, the rectifying means composed of the diodes 8 to 11 makes the polarity of the power supply applied to the integrated circuit block 2 one-sided in accordance with the alternating operation of the voltage polarity of the commercial power supply. Can operate normally.

【0015】図3は図2に示した整流手段の集積平面図
である。図中3'',4''は商用電源入力用金属配線、
5’は集積回路ブロックの高電位供給用金属配線、6’
は集積回路ブロックの低電位供給用金属配線、31,3
2は絶縁層上に形成された半導体領域、33,34,3
5,36は31,32の半導体領域に形成されたpn接
合境界、37,38,39,40,41,42は電源用
金属配線(3'',4'',5’,6’)と半導体領域3
1,32とを電気的に接続するためのコンタクトホール
(絶縁層の穴)である。
FIG. 3 is an integrated plan view of the rectifier shown in FIG. 3 ″ and 4 ″ in the figure are metal wiring for commercial power input,
5 'is a metal wiring for supplying a high potential of the integrated circuit block, 6'
Are metal wirings for supplying a low potential of the integrated circuit block;
2 is a semiconductor region formed on the insulating layer, 33, 34, 3
Reference numerals 5 and 36 denote pn junction boundaries formed in the semiconductor regions 31 and 32, and reference numerals 37, 38, 39, 40, 41 and 42 denote power supply metal wirings (3 ″, 4 ″, 5 ′ and 6 ′). Semiconductor region 3
These are contact holes (holes in an insulating layer) for electrically connecting the first and second electrodes 32 to each other.

【0016】図4は整流手段集積部の断面図である。図
中4''は商用電源入力用金属層、5’は集積回路ブロッ
クの高電位供給用金属配線、6’は集積回路ブロックの
低電位供給用金属配線、51は集積回路形成用半導体基
板、52はシリコン酸化絶縁膜、43,44は絶縁膜5
2の上に形成された半導体領域、45,46,47,4
8は金属配線層との電気的接続のためのコンタクトホー
ル、49は半導体領域43,44と金属配線層を電気的
に分離するための絶縁膜、50は半導体集積回路の最終
工程で形成される不活性化膜(パシベーション膜)であ
る。
FIG. 4 is a sectional view of the rectifying means integrated portion. In the figure, 4 ″ is a metal layer for inputting commercial power, 5 ′ is a metal wiring for supplying a high potential of the integrated circuit block, 6 ′ is a metal wiring for supplying a low potential of the integrated circuit block, 51 is a semiconductor substrate for forming an integrated circuit, 52 is a silicon oxide insulating film, 43 and 44 are insulating films 5
Semiconductor regions 45, 46, 47, 4 formed on
8 is a contact hole for electrical connection with the metal wiring layer, 49 is an insulating film for electrically separating the semiconductor regions 43 and 44 from the metal wiring layer, and 50 is formed in the final step of the semiconductor integrated circuit. It is a passivation film (passivation film).

【0017】このように絶縁層の上に整流手段を形成す
るのは、整流用の半導体素子を基板41から完全に絶縁
分離し、寄生ダイオードを排除するためである。従って
例えばSOS(silicon on saphire)、SOI(sili
con on insulator)、SIPOX(silicon implant
ed oxidation)などと呼ばれる絶縁分離技術において
はさらに簡便な構造で実現することができる。なぜなら
それらはpn接合の逆方向バイアスによる素子分離では
なく、電気的に完全独立した素子群を絶縁性の基板上に
形成できるからである。
The reason why the rectifying means is formed on the insulating layer is to completely insulate and separate the semiconductor element for rectification from the substrate 41 and eliminate the parasitic diode. Therefore, for example, SOS (silicon on saphire), SOI (sili
con on insulator), SIPOX (silicon implant)
In the case of an insulation separation technique called ed oxidation, etc., it can be realized with a simpler structure. This is because they can form an electrically independent element group on an insulating substrate instead of element isolation by a reverse bias of a pn junction.

【0018】図5は本発明における電圧安定化手段の一
構成例である。図中51は整流手段からの高電位電圧入
力端子、52は整流手段からの低電位電圧入力端子、5
3は演算増幅器、54は基準電圧源、55はMOS電界
効果トランジスタ、56,57は抵抗器、58は安定化
された高電位電源出力端子、59は低電位電源出力端子
である。ここでは入力端子51から加えられた不安定な
電源電圧がMOS電界効果トランジスタ55を介して出
力端子58に伝えられるが、出力端子58に現われる電
圧が分割抵抗56,57により定められた電圧値に比べ
て高い値である時、分割抵抗57に発生する電圧降下量
が設定値、すなわち基準電圧源54の値より大きくな
る。そのため基準電圧源54の出力電圧と分割抵抗57
に発生する電圧との差分が、演算増幅器53により増幅
され、MOS電界効果トランジスタ55のゲート電圧と
して印加される。今の説明の場合、分割抵抗57に発生
する電圧量が基準電圧源54の出力より大きいため、演
算増幅器の反転入力電圧<非反転入力電圧となり、演算
増幅器の出力電圧は高電位電源を出力するように動作す
る。従ってMOS電界効果トランジスタ55のゲート電
位は高電位、つまり不安定な整流手段高電位電圧付近ま
で近付くため、ソース電位とゲート電位との落差が小さ
くなり、電界効果トランジスタ55は導通抵抗が増加す
るようになる。その結果58の出力端子の電圧を低く抑
えるように作用する。仮に入力電圧が設定電圧より低く
なると、今までの説明と正反対に動作し、電界効果トラ
ンジスタ55の導通抵抗が低くなるように作用する。こ
のような動作の繰り返しにより、整流手段からの出力電
圧は安定化され出力端子58には集積回路の動作にふさ
わしい安定した電圧が得られる。
FIG. 5 shows an example of the configuration of the voltage stabilizing means according to the present invention. In the figure, 51 is a high potential voltage input terminal from the rectifier, 52 is a low potential voltage input terminal from the rectifier, 5
3 is an operational amplifier, 54 is a reference voltage source, 55 is a MOS field effect transistor, 56 and 57 are resistors, 58 is a stabilized high potential power output terminal, and 59 is a low potential power output terminal. Here, the unstable power supply voltage applied from the input terminal 51 is transmitted to the output terminal 58 via the MOS field-effect transistor 55, and the voltage appearing at the output terminal 58 becomes the voltage value determined by the division resistors 56 and 57. When the value is higher, the amount of voltage drop generated in the divided resistor 57 becomes larger than the set value, that is, the value of the reference voltage source 54. Therefore, the output voltage of the reference voltage source 54 and the dividing resistor 57
Is amplified by the operational amplifier 53 and applied as the gate voltage of the MOS field effect transistor 55. In the case of the present description, since the voltage generated in the dividing resistor 57 is larger than the output of the reference voltage source 54, the inverted input voltage of the operational amplifier <the non-inverted input voltage, and the output voltage of the operational amplifier outputs the high potential power supply. Works like that. Therefore, the gate potential of the MOS field-effect transistor 55 approaches a high potential, that is, near the unstable rectifier high potential voltage, so that the drop between the source potential and the gate potential becomes small, and the conduction resistance of the field-effect transistor 55 increases. become. As a result, the voltage at the output terminal 58 acts to be kept low. If the input voltage becomes lower than the set voltage, the operation is performed in a manner opposite to the above description, and the conduction effect of the field effect transistor 55 is reduced. By repeating such operations, the output voltage from the rectifier is stabilized, and a stable voltage suitable for the operation of the integrated circuit is obtained at the output terminal 58.

【0019】[0019]

【発明の効果】以上説明してきたように本発明を実施す
れば直流電源を電子機器に組み込む必要性が極めて低く
なり、電子機器の高密度組立が容易になる。
As described above, according to the present invention, the necessity of incorporating a DC power supply into electronic equipment is extremely reduced, and high-density assembly of electronic equipment is facilitated.

【0020】また本発明によれば従来の集積回路のよう
に、電源の電圧印加方法を誤って集積回路を破壊させる
ことを防止することができる。
Further, according to the present invention, it is possible to prevent the integrated circuit from being erroneously destroyed as in the case of the conventional integrated circuit.

【0021】本発明は広範囲に応用できる。例えば自動
車に搭載する電子機器ではエンジンの動力で発電された
交流電圧を直接利用することが可能になる。またその他
電気釜、電気掃除機、電気洗濯機等など日常の家庭電化
製品についてはそのほとんどに応用がきく。また太陽電
池駆動式電子機器に利用すれば太陽電池パネルの出力電
圧の安定化作用と同時に、組み込む場合の太陽電池パネ
ルの電極接続ミスによる集積回路の破壊を防止でき、か
つ逆接続によっても支障なく電子機器が動作できるよう
になる。これはメンテナンス性能を著しく向上させる一
例である。また一部の電子時計にみられる自動巻機構に
よる交流発電、電子回路駆動のメカニズムをより広くそ
の他の形態機器に応用できるようになる。
The invention has a wide range of applications. For example, an electronic device mounted on an automobile can directly use an AC voltage generated by the power of an engine. In addition, most home electric appliances such as electric kettles, vacuum cleaners, electric washing machines, etc. can be applied to most of them. In addition, when used in solar cell driven electronic devices, the output voltage of the solar panel can be stabilized, and at the same time, the integrated circuit can be prevented from being damaged due to a mistake in the electrode connection of the solar panel when incorporated. The electronic device can operate. This is an example that significantly improves maintenance performance. Also, the mechanism of AC power generation and electronic circuit drive by an automatic winding mechanism found in some electronic timepieces can be more widely applied to other forms of equipment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の基本構成図。FIG. 1 is a basic configuration diagram of the present invention.

【図2】 本発明の具体的構成例の図。FIG. 2 is a diagram of a specific configuration example of the present invention.

【図3】 本発明の集積回路平面図。FIG. 3 is a plan view of an integrated circuit according to the present invention.

【図4】 本発明の集積回路断面図。FIG. 4 is a cross-sectional view of the integrated circuit of the present invention.

【図5】 本発明の電源安定化手段の一構或図である。FIG. 5 is a diagram or a configuration of a power supply stabilizing unit of the present invention.

【符号の説明】[Explanation of symbols]

1,1’…………整流手段 2,2’,2''…集積回路ブロック 3,3’,3''…商用電源入力端子 4,4’,4''…商用電源入力端子 5,5’,5''…集積回路ブロック高電位線 6,6’,6''…集積回路ブロック低電位線 7 …………電源安定化手段 31、32……絶縁膜上の半導体領域 43、44……絶縁膜上の半導体領域 53 ………演算増幅器 54 ………基準電圧源 55 ………MOS電界効果トランジスタ 56,57……抵抗器 1, 1 '... rectifying means 2, 2', 2 "... integrated circuit block 3, 3 ', 3" ... commercial power input terminal 4, 4', 4 "... commercial power input terminal 5, 5 ′, 5 ″ integrated circuit block high-potential line 6, 6 ′, 6 ″ integrated circuit block low-potential line 7 power stabilizing means 31, 32 semiconductor region 43 on insulating film 43 44 semiconductor region on insulating film 53 operational amplifier 54 reference voltage source 55 MOS field effect transistors 56 and 57 resistors

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成11年7月26日(1999.7.2
6)
[Submission date] July 26, 1999 (1999.7.2)
6)

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】発明の名称[Correction target item name] Name of invention

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【発明の名称】 整流回路及び半導体集積回路Title of the invention Rectifier circuit and semiconductor integrated circuit

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【手続補正3】[Procedure amendment 3]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図2[Correction target item name] Figure 2

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図2】 FIG. 2

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H02M 7/04 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H02M 7/04

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 集積回路基板、前記集積回路基板上に形
成された電子回路、前記電子回路の製造過程において形
成される、前記集積回路基板と配線層との絶縁分離薄
膜、前記薄膜上に形成されるpn接合整流手段、前記整
流手段の出力を安定化する電圧安定化手段とを有し、前
記整流手段のカソードは前記電圧安定化手段の高電位入
力端子に、前記整流手段のアノードは前記電圧安定化手
段の低電位入力端子に接続され、前記電子回路の電源が
前記電圧安定化手段の出力により与えられることを特徴
とする集積回路。
1. An integrated circuit substrate, an electronic circuit formed on the integrated circuit substrate, a thin insulating film between the integrated circuit substrate and a wiring layer formed in a process of manufacturing the electronic circuit, and formed on the thin film Rectifying means, and voltage stabilizing means for stabilizing the output of the rectifying means. The cathode of the rectifying means is connected to a high potential input terminal of the voltage stabilizing means, and the anode of the rectifying means is connected to the An integrated circuit connected to a low potential input terminal of a voltage stabilizing means, wherein power of the electronic circuit is provided by an output of the voltage stabilizing means.
JP11203624A 1999-07-16 1999-07-16 Rectifying circuit and semiconductor integrated circuit Pending JP2000069755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11203624A JP2000069755A (en) 1999-07-16 1999-07-16 Rectifying circuit and semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11203624A JP2000069755A (en) 1999-07-16 1999-07-16 Rectifying circuit and semiconductor integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2024175A Division JP2995778B2 (en) 1990-02-02 1990-02-02 Integrated circuit

Publications (1)

Publication Number Publication Date
JP2000069755A true JP2000069755A (en) 2000-03-03

Family

ID=16477135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11203624A Pending JP2000069755A (en) 1999-07-16 1999-07-16 Rectifying circuit and semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2000069755A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916755A (en) * 2010-09-03 2010-12-15 四川太晶微电子有限公司 Plane rectifier
CN105409922A (en) * 2015-12-23 2016-03-23 南京信息职业技术学院 Dot frequency ultrasonic electronic insect repellent circuit
CN111244037A (en) * 2020-03-11 2020-06-05 天水天光半导体有限责任公司 Integrated manufacturing method of reverse voltage 40V or 60V bridge rectifier circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916755A (en) * 2010-09-03 2010-12-15 四川太晶微电子有限公司 Plane rectifier
CN105409922A (en) * 2015-12-23 2016-03-23 南京信息职业技术学院 Dot frequency ultrasonic electronic insect repellent circuit
CN111244037A (en) * 2020-03-11 2020-06-05 天水天光半导体有限责任公司 Integrated manufacturing method of reverse voltage 40V or 60V bridge rectifier circuit
CN111244037B (en) * 2020-03-11 2023-06-02 天水天光半导体有限责任公司 Integrated manufacturing method of reverse voltage 40V or 60V bridge rectifier circuit

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