JPH0686355U - Complementary metal-oxide semiconductor device - Google Patents
Complementary metal-oxide semiconductor deviceInfo
- Publication number
- JPH0686355U JPH0686355U JP036605U JP3660593U JPH0686355U JP H0686355 U JPH0686355 U JP H0686355U JP 036605 U JP036605 U JP 036605U JP 3660593 U JP3660593 U JP 3660593U JP H0686355 U JPH0686355 U JP H0686355U
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- semiconductor device
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- 230000000295 complement effect Effects 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 title claims 2
- 150000004706 metal oxides Chemical class 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Rectifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 本考案は、相補型ＣＭＯＳ技術を用いた集積
回路デバイスに形成された全波整流器に関し、特に、従
来実現が困難であったＣＭＯＳ全波整流器を提供するこ
とを目的とする。
【構成】 本件考案は、通常全波整流器に用いられる４
個のダイオードのうちの２個をＮＭＯＳトランジスタで
置き換え、当該トランジスタがダイオードスイッチとし
て機能するように接続して動作させることを特徴とし、
寄生トランジスタに起因する接地への短絡電流の問題を
解消することで、集積回路デバイスに形成された全波整
流器を提供することが可能となる。
(57) [Summary] [Object] The present invention relates to a full-wave rectifier formed in an integrated circuit device using complementary CMOS technology, and in particular, to provide a CMOS full-wave rectifier that has been difficult to realize in the past. To aim. [Structure] The present invention is commonly used in full-wave rectifiers.
Characterized in that two of the diodes are replaced by NMOS transistors, and the transistors are connected and operated so as to function as a diode switch.
By eliminating the problem of short circuit current to ground due to parasitic transistors, it is possible to provide a full wave rectifier formed in an integrated circuit device.
Description
【０００１】[0001]
本考案は相補型金属−酸化物−半導体（ＣＭＯＳ）技術を用いた集積回路（Ｉ Ｃ）デバイスに形成された全波整流器に係る。 The present invention relates to a full-wave rectifier formed in an integrated circuit (IC) device using complementary metal-oxide-semiconductor (CMOS) technology.
【０００２】[0002]
ＣＭＯＳ全波整流器は実現が困難である。その理由は従来全波整流器を規定す るために用いられたダイオードは、寄生トランジスタ動作を通して、チップ基板 を通して、接地への短絡電流を流し、回路機能を妨げる働きがあるからである。 CMOS full wave rectifiers are difficult to implement. The reason is that the diode conventionally used to define the full-wave rectifier has a function of passing a short-circuit current to the ground through the chip substrate through the operation of the parasitic transistor and hindering the circuit function.
【０００３】[0003]
基板を通した接地への短絡電流の問題は、通常全波整流に用いられる４個のダ イオードの２個をＮＭＯＳトランジスタで置き換え、２個のトランジスタが“ダ イオード”ターン・オン及びターン・オフとして機能するように、それらを接続 及び動作させることにより避けられる。実施例において、トランジスタのゲート 電極はパワー源間に接続され、基板は電気的に浮いたままに保たれ、“ダイオー ド”の“ソース”は負荷への接続のため、相互接続される。 The problem of short-circuit current to ground through the substrate is that two of the four diodes normally used for full-wave rectification are replaced by NMOS transistors, the two transistors being "diode" turn-on and turn-off. They are avoided by connecting and operating them so that they function as. In an embodiment, the gate electrode of the transistor is connected between the power sources, the substrate is kept electrically floating, and the "source" of the "diode" is interconnected for connection to the load.
【０００４】[0004]
図１は従来技術の全波整流器の概略回路ダイアグラム１０を示す。ダイアグラ ムはノード１６、１７、１８及び１９間に接続された４個のダイオード１１、１ ２、１３及び１４の通常のブリッジ構成を示す。負荷抵抗２０がノード１６及び １８間に接続される。信号源２１がノード１７及び１９間に接続される。従来技 術の全波整流器の動作については、よく知られており、ここではこれ以上議論し ない。 FIG. 1 shows a schematic circuit diagram 10 of a prior art full wave rectifier. The diagram shows a conventional bridge configuration of four diodes 11, 12, 13 and 14 connected between nodes 16, 17, 18 and 19. A load resistor 20 is connected between nodes 16 and 18. A signal source 21 is connected between nodes 17 and 19. The operation of conventional full-wave rectifiers is well known and will not be discussed further here.
【０００５】 そのような動作は、ＣＭＯＳ ＩＣチップでは現在実現することができない。 この理由について、図２に関連して述べる。図２はＣＭＯＳ ＩＣチップの一部 の断面を示す。チップは表面５１に隣接した二つのＰ形及び二つのＮ形拡散領域 を有する電圧ＶDDに保たれたＮ形基板５０を有し、Ｎ形領域はＰ−タブ５２中に 形成されている。拡散領域は、図１中に示されたようなダイオードを規定し、図 のような極性にある。Such operations are currently not achievable with CMOS IC chips. The reason for this will be described with reference to FIG. FIG. 2 shows a cross section of a part of the CMOS IC chip. The chip has an N-type substrate 50 held at a voltage V DD having two P-type and two N-type diffusion regions adjacent a surface 51, the N-type region being formed in a P-tab 52. The diffusion region defines the diode as shown in FIG. 1 and has the polarity as shown.
【０００６】 図２の構造は寄生ＮＰＮトランジスタ６０及び６３が存在するため、全波整流 器としては動作させられない。たとえばダイオード１３が順方向バイアスされた 時、電流は（負荷）抵抗２０ではなく基本的には基板を通ってトランジスタ６０ 中に流れ全波整流を妨げる。同様のトランジスタ動作は、ダイオード１４が寄生 トランジスタ６３を経て順方向にバイアスされた時起る。The structure of FIG. 2 cannot operate as a full-wave rectifier because of the presence of parasitic NPN transistors 60 and 63. For example, when diode 13 is forward biased, current flows essentially through the substrate rather than (load) resistor 20 into transistor 60, impeding full wave rectification. Similar transistor operation occurs when diode 14 is forward biased through parasitic transistor 63.
【０００７】 図３はＣＭＯＳ技術に改良できる全波整流器７０の概略図を示す。図３のダイ オード７１及び７２はそれぞれ図１のダイオード１１及び１２に対応し、トラン ジスタ７３及び７４はダイオード１４及び１３に対応する。信号源７８は図１の 信号源２１に対応する。FIG. 3 shows a schematic diagram of a full wave rectifier 70 that can be modified to CMOS technology. Diodes 71 and 72 of FIG. 3 correspond to diodes 11 and 12 of FIG. 1, respectively, and transistors 73 and 74 correspond to diodes 14 and 13, respectively. The signal source 78 corresponds to the signal source 21 in FIG.
【０００８】 図１のノード１６、１７、１８及び１９はそれぞれ図３のノード８２、８３、 ８４及び８５に対応する。トランジスタ７４のゲート電極は、ノード８５に接続 され、トランジスタ７３のゲート電極は、ノード８３に接続されていることに注 意すべきである。トランジスタ７３及び７４のソースは、対照的にそれぞれノー ド８５及び８３に接続され、ドレインはノード８４に接続されている。ノード８ ３及び８５は回路の入力端子と考えられ、ノード８２及び８４は出力端子と考え られる。The nodes 16, 17, 18 and 19 of FIG. 1 correspond to the nodes 82, 83, 84 and 85 of FIG. 3, respectively. It should be noted that the gate electrode of transistor 74 is connected to node 85 and the gate electrode of transistor 73 is connected to node 83. The sources of transistors 73 and 74, by contrast, are connected to nodes 85 and 83, respectively, and the drains are connected to node 84. Nodes 83 and 85 are considered input terminals of the circuit, and nodes 82 and 84 are considered output terminals.
【０００９】 図４は図３の回路を改良したＩＣの一部の断面を示す。この部分はＮ形基板か ら成り、その中に二つのＰ−タブ領域１０１及び１０２が形成されている。Ｎ＋ 形拡散領域１０４、１０５、１０６、１０７は、それぞれそれらの間に、図３の トランジスタ７４及び７３を規定する。FIG. 4 shows a partial cross-section of an IC which is an improvement of the circuit of FIG. This part consists of an N-type substrate in which two P-tub regions 101 and 102 are formed. The N + -type diffusion regions 104, 105, 106, 107 respectively define between them the transistors 74 and 73 of FIG.
【００１０】 各種の領域は図３に概略的に示されるように、相互接続されている。たとえば 、領域１０５及び１０６は、負荷抵抗９０に接続するため、ノード８４で電気的 に相互接続されている（図３）。図２のトランジスタ６０及び６３の動作と等価 な寄生動作をする寄生トランジスタは存在しない。The various areas are interconnected as shown schematically in FIG. For example, regions 105 and 106 are electrically interconnected at node 84 to connect to load resistor 90 (FIG. 3). There is no parasitic transistor that has a parasitic operation equivalent to that of the transistors 60 and 63 in FIG.
【００１１】 動作中、ノード８５が信号源７８により、正に駆動された時、電流はダイオー ド７１を通って、負荷９０に流れる。また、トランジスタ７４はゲート・オンさ れ、そのため電流はトランジスタを通って信号源７８に流れる。トランジスタ７ ３には電流は流れない。ノード８３が正に駆動された時、トランジスタ７３はゲ ート・オンされる。その結果、電流はトランジスタ７３及びダイオード７２を経 て、負荷９０中に流れる。このようにして、全波整流が実現される。 チップ基板を通して電流を流す図１及び図２の装置における寄生トランジスタ動 作は、動作の各周期の適当な位相において、ゲート・オフされたトランジスタを 用いることにより避けられる。In operation, when node 85 is driven positive by signal source 78, current flows through diode 71 to load 90. Also, transistor 74 is gated on, so that current flows through it to signal source 78. No current flows through the transistor 73. When node 83 is driven positive, transistor 73 is gated on. As a result, current flows through transistor 73 and diode 72 into load 90. In this way, full-wave rectification is achieved. Parasitic transistor behavior in the devices of FIGS. 1 and 2 which draw current through the chip substrate is avoided by using gated off transistors at the appropriate phase of each cycle of operation.
【００１２】 動作はＡＣ源及び負荷間の別の完全な電流路を形成すると考えてよい。各完全 な電流路は、ソース及び負荷間に、第１または第２の部分を添加することにより 、形成される。この場合、各部分はダイオード及びトランジスタを含み、それぞ れが即座には使用されないダイオードを含む第１または第２の部分の反対の側に あるトランジスタのみのゲートを駆動させるのに適している。Operation may be considered to form another complete current path between the AC source and the load. Each complete current path is formed by adding a first or second portion between the source and the load. In this case, each part comprises a diode and a transistor, each of which is suitable for driving the gate of only the transistor on the opposite side of the first or second part, which contains a diode which is not used immediately.
【図１】従来技術の全波整流器の回路構成図である。FIG. 1 is a circuit configuration diagram of a conventional full-wave rectifier.
【図２】図１中の回路構成を示すＣＭＯＳチップの一部
の断面図である。FIG. 2 is a partial cross-sectional view of a CMOS chip showing the circuit configuration in FIG.
【図３】本考案に従う全波整流器の回路構成図である。FIG. 3 is a circuit configuration diagram of a full-wave rectifier according to the present invention.
【図４】図３の回路構成を示すＣＭＯＳチップの一部の
断面図である。FIG. 4 is a cross-sectional view of a part of a CMOS chip showing the circuit configuration of FIG.
第１の入力端子・・・・・８５、 第２の入力端子・・・・・８３、負荷・・・・・９０、 第１の出力端子・・・・・８４、 第２の出力端子・・・・・８２、 第１のダイオード・・・・・７２、 第２のダイオード・・・・・７１、 第１のトランジスタ・・・・・７３、 第２のトランジスタ・・・・・７４、 第１の伝導形・・・・・Ｎ、第２の伝導形・・・・・Ｐ、 第１のタブ・・・・・１０２、第２のタブ・・・・・１０１、 表面領域・・・・・１０６−１０７；１０４−１０５、 領域・・・・・７１、７２。 First input terminal ... 85, Second input terminal ... 83, Load ... 90, First output terminal ... 84, Second output terminal ... 82, first diode ... 72, second diode ... 71, first transistor ... 73, second transistor ... 74, First conductivity type N, second conductivity type P, first tab 102, second tab 101, surface region ... ... 106-107; 104-105, areas ... 71, 72.
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【手続補正書】[Procedure amendment]
【提出日】平成５年８月４日[Submission date] August 4, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】実用新案登録請求の範囲[Name of item to be amended] Scope of utility model registration request
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【実用新案登録請求の範囲】[Scope of utility model registration request]
Claims (2)
８５）及び第２（たとえば８３）の入力端子と、負荷
（たとえば９０）への整流された出力を供給するための
第１（たとえば８４）及び第２（たとえば８２）の出力
端子と、第１（たとえば７２）及び第２（たとえば７
１）のダイオードと、第１（たとえば７３）及び第２
（たとえば７４）のトランジスタと、前記第１（たとえ
ば８５）の入力端子から、前記第１（たとえば７３）の
トランジスタを経て、前記第１（たとえば８４）の出力
端子へ延びる第１の導電路と、前記第２（たとえば８
３）の入力端子から前記第１（たとえば７２）のダイオ
ードを経て、前記第２（たとえば８２）出力端子へ延び
る第２の導電路と、前記第２（たとえば８３）の入力端
子から前記第２（たとえば７４）のトランジスタを通っ
て、前記第１（たとえば８４）の出力端子まで延びる第
３の導電路と、前記第１（たとえば８５）の入力端子か
ら、前記第２（たとえば７１）のダイオードを通って、
前記第２（たとえば８２）の出力端子に延びる第４の導
電路とを含み、前記第１のトランジスタ（たとえば７
３）のゲートは前記第２（たとえば８３）の入力端子に
接続され、第２（たとえば７４）のトランジスタのゲー
トは、第１（たとえば８５）の入力端子に接続され、前
記第１及び第２のダイオードはＡＣ信号の相対する位相
中、導電性となるような極性であることを特徴とする相
補型金属−酸化物半導体デバイス。1. A first (eg 85) and second (eg 83) input terminal for connection to an AC source and a first (for providing rectified output to a load (eg 90)). For example 84) and second (eg 82) output terminals and first (eg 72) and second (eg 7) output terminals.
1) diode and first (eg 73) and second diode
A (eg, 74) transistor and a first conductive path extending from the first (eg, 85) input terminal, through the first (eg, 73) transistor, to the first (eg, 84) output terminal. , The second (eg 8
3) a second conductive path extending from the input terminal of 3) to the second (eg 82) output terminal through the first (eg 72) diode, and the second (eg 83) input terminal to the second A third conductive path extending through the (eg, 74) transistor to the first (eg, 84) output terminal and the second (eg, 71) diode from the first (eg, 85) input terminal. Through
A fourth conductive path extending to the second (eg, 82) output terminal, and the first transistor (eg, 7).
The gate of 3) is connected to the second (eg 83) input terminal, the gate of the second (eg 74) transistor is connected to the first (eg 85) input terminal, and the first and second The complementary metal-oxide semiconductor device is characterized in that the diode is polarized so that it becomes conductive during the opposite phases of the AC signal.
おいて、前記デバイスは第１（たとえばＮ）の伝導形の
半導体基板を含み前記基板は第２（たとえばＰ）の伝導
形の第１（たとえば１０２）及び第２（たとえば１０
１）のタブを含み、前記第１及び第２のタブの各々は前
記第１（たとえば７３）及び第２（たとえば７４）のト
ランジスタをそれぞれ間に規定する第１（たとえばＮ）
の伝導形の空間的に分離された表面領域（たとえば、そ
れぞれ１０６−１０７および１０４−１０５）を含み、
前記基板はまた後側をあわせて相互接続された前記第１
（たとえば７２）及び第２（たとえば７１）のダイオー
ドを規定する第２（たとえばＰ）の伝導形の空間的に分
離された領域（たとえば７１、７２）を含むことを特徴
とする相補型金属−酸化物半導体デバイス。2. A semiconductor device according to claim 1, wherein the device comprises a semiconductor substrate of a first (eg N) conductivity type and the substrate is a first (eg P) conductivity type. 102) and the second (eg 10)
1) tabs, each of the first and second tabs defining a first (eg 73) and a second (eg 74) transistor therebetween, respectively (first (eg N)).
Of spatially separated surface regions of conductive type (eg, 106-107 and 104-105, respectively),
The substrates are also interconnected back to back with the first
A complementary metal, characterized in that it comprises (eg 72) and a second (eg P) conductivity type spatially separated region (eg 71, 72) defining a second (eg 71) diode. Oxide semiconductor device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/521,059 USH64H (en) | 1983-08-08 | 1983-08-08 | Full-wave rectifier for CMOS IC chip |
| US521059 | 1983-08-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0686355U true JPH0686355U (en) | 1994-12-13 |
Family
ID=24075163
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59165045A Pending JPS6057961A (en) | 1983-08-08 | 1984-08-08 | Complementary metal-oxide semiconductor device |
| JP036605U Pending JPH0686355U (en) | 1983-08-08 | 1993-07-05 | Complementary metal-oxide semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59165045A Pending JPS6057961A (en) | 1983-08-08 | 1984-08-08 | Complementary metal-oxide semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | USH64H (en) |
| JP (2) | JPS6057961A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006115579A (en) * | 2004-10-13 | 2006-04-27 | Renesas Technology Corp | Semiconductor integrated circuit device, noncontact electronic equipment, and portable information terminal |
| JP2009506734A (en) * | 2005-08-23 | 2009-02-12 | フリボ モバイル パワー ゲーエムベーハー | Switching mode power supply input circuit |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63300802A (en) * | 1987-05-29 | 1988-12-08 | Yamazaki Mazak Corp | Opposed-spindle lathe |
| JP2704874B2 (en) * | 1987-07-24 | 1998-01-26 | ヤマザキマザック株式会社 | Multi-task machine tools |
| WO1989010223A1 (en) * | 1988-04-19 | 1989-11-02 | Nakamura Tome Precision Ind. Co., Ltd. | Two opposed main shaft type cnc lathe |
| JPH0683921B2 (en) * | 1988-04-19 | 1994-10-26 | 中村留精密工業株式会社 | 2-spindle opposed type CNC lathe |
| JPH0785861B2 (en) * | 1990-10-08 | 1995-09-20 | 日立精機株式会社 | Numerically controlled lathe and its operating method |
| US6580150B1 (en) | 2000-11-13 | 2003-06-17 | Vram Technologies, Llc | Vertical junction field effect semiconductor diodes |
| US6738238B2 (en) * | 2001-07-20 | 2004-05-18 | Siemens Building Technologies, Inc. | Fire detection system including an automatic polarity sensing power and signal interface |
| US20120126334A1 (en) * | 2010-11-24 | 2012-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Breakdown voltage improvement with a floating substrate |
| TWI545882B (en) * | 2015-03-20 | 2016-08-11 | 漢磊科技股份有限公司 | Two chips integrtated bridge rectifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113262A (en) * | 1980-12-30 | 1982-07-14 | Seiko Epson Corp | Voltage dividing system for semiconductor integrated circuit |
| JPS57119674A (en) * | 1980-11-26 | 1982-07-26 | Itt | Monolithic integrated rectifying bridge |
-
1983
- 1983-08-08 US US06/521,059 patent/USH64H/en not_active Abandoned
-
1984
- 1984-08-08 JP JP59165045A patent/JPS6057961A/en active Pending
-
1993
- 1993-07-05 JP JP036605U patent/JPH0686355U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57119674A (en) * | 1980-11-26 | 1982-07-26 | Itt | Monolithic integrated rectifying bridge |
| JPS57113262A (en) * | 1980-12-30 | 1982-07-14 | Seiko Epson Corp | Voltage dividing system for semiconductor integrated circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006115579A (en) * | 2004-10-13 | 2006-04-27 | Renesas Technology Corp | Semiconductor integrated circuit device, noncontact electronic equipment, and portable information terminal |
| JP4521598B2 (en) * | 2004-10-13 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device, non-contact electronic device, and portable information terminal |
| JP2009506734A (en) * | 2005-08-23 | 2009-02-12 | フリボ モバイル パワー ゲーエムベーハー | Switching mode power supply input circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| USH64H (en) | 1986-05-06 |
| JPS6057961A (en) | 1985-04-03 |
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