TWI545882B - Two chips integrtated bridge rectifier - Google Patents
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Description
本發明是有關於一種橋式整流器(bridge rectifier),且特別是有關於一種被整合於二個晶片的橋式整流器。 This invention relates to a bridge rectifier, and more particularly to a bridge rectifier integrated into two wafers.
傳統的橋式整流器是將四個PN二極體晶片以圖1所示方式耦接而成,用來進行將交流電轉為直流電的操作。 A conventional bridge rectifier is formed by coupling four PN diode chips in the manner shown in FIG. 1 for performing an operation of converting alternating current into direct current.
請參照圖1,當輸入(In)端給予正交流電,電流經由二極體16至輸出端,訊號為正,並經由二極體12、14間輸出(Out)地端經二極體14回流至輸入地端;當輸入端給予負交流電,電流則經由二極體18流至輸出端,輸出端訊號亦為正,並經由二極體12、14間輸出地端經二極體12回流至輸入端。 Referring to FIG. 1, when the input (In) terminal is given positive alternating current, the current passes through the diode 16 to the output terminal, the signal is positive, and the output ends through the diodes 12 and 14 are returned through the diode 14. To the input ground; when the input terminal is given negative AC power, the current flows through the diode 18 to the output terminal, the output signal is also positive, and the output terminal between the diodes 12 and 14 is returned to the diode 12 through the diode 12 Input.
如上所述,橋式整流即是在交流電訊號給予負電壓時將其轉為正電壓,藉以達到整流為正正弦(sin波)波型電壓的功能。 As described above, bridge rectification is a function of converting a positive voltage into a positive sinusoidal (sin wave) mode voltage when an alternating current signal is applied to a negative voltage.
然而,先前技術之橋式整流器含有四個PN二極體晶片,所以其電路設計頗為複雜。 However, the prior art bridge rectifier contains four PN diode chips, so the circuit design is quite complicated.
本發明提供一種二晶片整合橋式整流器,其是將四個二極體中的兩個整合為一個對稱式PIN二極體位於一晶片中,並將另兩個二極體整合進控制電路的CMOS製程而與控制電路共存於另一晶片中而得。 The present invention provides a two-wafer integrated bridge rectifier in which two of the four diodes are integrated into one symmetrical PIN diode in one wafer, and the other two diodes are integrated into the control circuit. The CMOS process is obtained by coexisting with the control circuit in another wafer.
本發明的二晶片整合橋式整流器其等效電路包括第一至第四二極體,其中第一二極體的陽極與第二二極體的陽極耦接至輸出地端,第一二極體的陰極與第三二極體的陽極耦接至輸入端,第二二極體的陰極與第四二極體的陽極耦接至輸入地端,且第三二極體的陰極與第四二極體的陰極耦接至輸出端。該橋式整流器包括:整合了第三與第四二極體的一對稱式PIN二極體(P-intrinsic-N diode),位於第一晶片中,其中屬於第三二極體的部分的結構與屬於第四二極體的部分的結構對稱;以及第一二極體與第二二極體的一等效元件,該等效元件被整合進一控制電路的互補式金氧半導體(CMOS)製程,而與所述控制電路共存於第二晶片中。 The equivalent circuit of the two-chip integrated bridge rectifier of the present invention includes first to fourth diodes, wherein the anode of the first diode and the anode of the second diode are coupled to the output ground, the first two poles The cathode of the body and the anode of the third diode are coupled to the input end, the cathode of the second diode and the anode of the fourth diode are coupled to the input ground, and the cathode of the third diode and the fourth The cathode of the diode is coupled to the output. The bridge rectifier includes: a symmetric PIN diode (P-intrinsic-N diode) integrated with the third and fourth diodes, and is located in the first wafer, wherein the structure belonging to the portion of the third diode Symmetrical with the structure of the portion belonging to the fourth diode; and an equivalent component of the first diode and the second diode, the equivalent component being integrated into a complementary metal oxide semiconductor (CMOS) process of a control circuit And coexisting with the control circuit in the second wafer.
於一實施例中,所述對稱式PIN二極體包括:第三二極體與第四二極體的共陰極、與所述共陰極電性連接的至少一N摻雜層、第三二極體與第四二極體各自的陽極、分別與所述二陽極電性連接的二個P摻雜層,以及各P摻雜層與N摻雜層之間的本質層(intrinsic layer)。在一個例子中,所述N摻雜層包括一濃摻雜N基底且配置於所述共陰極上,所述本質層包括N型淡摻雜層且配置於所述濃摻雜N基底上,且所述二個P摻雜層包括位於所 述N型淡摻雜層中的二個P井。此對稱式PIN二極體可更包括二個以上的護環,位於所述N型淡摻雜層中,各自環繞所述二個P井之一。 In one embodiment, the symmetric PIN diode includes: a common cathode of the third diode and the fourth diode, at least one N-doped layer electrically connected to the common cathode, and a third An anode of each of the pole body and the fourth diode, two P-doped layers electrically connected to the two anodes, and an intrinsic layer between each of the P-doped layer and the N-doped layer. In one example, the N-doped layer includes a heavily doped N substrate disposed on the common cathode, the intrinsic layer including an N-type lightly doped layer and disposed on the heavily doped N substrate, And the two P doped layers comprise Two P wells in the N-type lightly doped layer. The symmetrical PIN diode may further comprise two or more guard rings located in the N-type lightly doped layer, each surrounding one of the two P wells.
於一實施例中,所述等效元件包括一對稱結構,其中屬於第一二極體的部分的結構與屬於第二二極體的部分的結構對稱。所述對稱結構具有第一二極體與第二二極體的共陽極、與所述共陽極電性連接的P摻雜層、第一二極體與第二二極體各自的陰極,以及分別與所述二個陰極電性連接且與所述P摻雜層電性連接的二個N摻雜層。 In one embodiment, the equivalent element comprises a symmetrical structure in which the structure of the portion belonging to the first diode is symmetrical with the structure of the portion belonging to the second diode. The symmetrical structure has a common anode of a first diode and a second diode, a P-doped layer electrically connected to the common anode, a cathode of each of the first diode and the second diode, and Two N-doped layers electrically connected to the two cathodes and electrically connected to the P-doped layer.
於一實施例中,所述對稱結構更包括與所述共陽極電性連接、分別屬於第一二極體與第二二極體的二個閘極,而成為一對稱式金氧半結構。此對稱式金氧半結構可包括一對稱式的橫向擴散金氧半(LDMOS)結構,其包括:一P基底;作為所述P摻雜層的一P井,位於所述P基底中;二個第一N井,位於所述P井兩側的P基底中,分別屬於第一二極體與第二二極體,且摻雜濃度低於所述P井;二場氧化層,分別位於所述二個第一N井上;所述二個閘極,各自位於所述二個場氧化層(Field oxide layer)之一、所述二個第一N井之一及所述P井上;作為所述二個N摻雜層的二個第二N井,分別位於所述二個第一N井的外側,其分別屬於第一二極體與第二二極體,且摻雜濃度高於所述二個第一N井;所述共陽極,與所述P井及所述二個閘極電性連接;以及第一二極體與第二二極體各自的陰極。 In one embodiment, the symmetrical structure further includes two gates electrically connected to the common anode and belonging to the first diode and the second diode, respectively, to form a symmetrical metal oxide half structure. The symmetrical metal oxide half structure may comprise a symmetric laterally diffused gold oxide half (LDMOS) structure comprising: a P substrate; a P well as the P doped layer, located in the P substrate; The first N wells are located in the P base on both sides of the P well, belonging to the first diode and the second diode respectively, and the doping concentration is lower than the P well; the two field oxide layers are respectively located The two first N wells; the two gates are respectively located in one of the two field oxide layers, one of the two first N wells and the P well; Two second N wells of the two N-doped layers are respectively located outside the two first N wells, and belong to the first diode and the second diode respectively, and the doping concentration is higher than The two first N wells; the common anode is electrically connected to the P well and the two gates; and the cathodes of the first diode and the second diode.
於另一實施例中,所述對稱結構不包括該互補式金氧半導體製程中所形成的閘導電層。此對稱結構可包括:一P基底;作為所述P摻雜層的一P井,位於所述P基底中;二個第一N井,位於所述P井兩側的P基底中,分別屬於第一二極體與第二二極體,且摻雜濃度低於所述P井;二場氧化層,分別位於所述二個第一N井上;作為所述二個N摻雜層的二第二N井,分別位於所述二個第一N井的外側,其分別屬於第一二極體與第二二極體,且摻雜濃度高於所述二個第一N井;所述共陽極,與所述P井電性連接;以及第一二極體與第二二極體各自的陰極。 In another embodiment, the symmetrical structure does not include the gate conductive layer formed in the complementary MOS process. The symmetrical structure may include: a P substrate; a P well as the P doped layer, located in the P substrate; and two first N wells located in the P substrate on both sides of the P well, respectively a first diode and a second diode, and a doping concentration lower than the P well; two field oxide layers respectively located on the two first N wells; and two as the two N doping layers a second N well, respectively located outside the two first N wells, belonging to the first diode and the second diode, respectively, and having a higher doping concentration than the two first N wells; a common anode electrically connected to the P well; and a cathode of each of the first diode and the second diode.
由於本發明將橋式整流之四個二極體中的兩個整合為一個對稱式PIN二極體,並將另兩個整合進控制電路的CMOS製程,所以只要用兩個晶片即可組成橋式整流器,而得以簡化電路設計。 Since the present invention integrates two of the four diodes of the bridge rectification into one symmetrical PIN diode and integrates the other two into the CMOS process of the control circuit, the bridge can be formed by using only two wafers. Rectifiers simplify circuit design.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
12‧‧‧第一二極體 12‧‧‧First Diode
14‧‧‧第二二極體 14‧‧‧Secondary diode
16‧‧‧第三二極體 16‧‧‧ Third Dipole
18‧‧‧第四二極體 18‧‧‧ fourth diode
19‧‧‧控制電路 19‧‧‧Control circuit
20‧‧‧對稱式PIN二極體 20‧‧‧Symmetric PIN diode
22‧‧‧第一晶片 22‧‧‧First chip
24‧‧‧第二晶片 24‧‧‧second chip
300‧‧‧濃摻雜N基底 300‧‧‧Concentrated doped N substrate
302‧‧‧N型淡摻雜層 302‧‧‧N type doped layer
304‧‧‧P井 304‧‧‧P well
306‧‧‧護環 306‧‧‧ guard ring
308‧‧‧P型濃摻雜接觸區 308‧‧‧P type concentrated doping contact area
310‧‧‧介電層 310‧‧‧Dielectric layer
312‧‧‧陽極 312‧‧‧Anode
314‧‧‧共陰極 314‧‧‧Common cathode
400‧‧‧P基底 400‧‧‧P base
402‧‧‧N型埋入區 402‧‧‧N type buried area
404‧‧‧第一N井 404‧‧‧First N Well
406‧‧‧場氧化層 406‧‧ ‧ field oxide layer
408‧‧‧第二N井 408‧‧‧Second N well
410‧‧‧P井 410‧‧‧P well
412‧‧‧N型濃摻雜接觸區 412‧‧‧N type concentrated doping contact area
414‧‧‧P型濃摻雜接觸區 414‧‧‧P type concentrated doping contact area
416‧‧‧閘極 416‧‧‧ gate
418‧‧‧介電層 418‧‧‧ dielectric layer
420‧‧‧陰極 420‧‧‧ cathode
422‧‧‧共陽極 422‧‧‧Common anode
圖1是習知的橋式整流器的電路簡圖。 1 is a circuit diagram of a conventional bridge rectifier.
圖2是本發明一實施例的二晶片整合橋式整流器的示意圖。 2 is a schematic diagram of a two-wafer integrated bridge rectifier in accordance with an embodiment of the present invention.
圖3是本發明實施例的二晶片整合橋式整流器中,整合了第三二極體與第四二極體的對稱式PIN二極體的一例的剖面圖。 3 is a cross-sectional view showing an example of a symmetrical PIN diode in which a third diode and a fourth diode are integrated in a two-wafer integrated bridge rectifier according to an embodiment of the present invention.
圖4是本發明實施例的二晶片整合橋式整流器中,被整合進控 制電路的CMOS製程之第一與第二二極體的等效元件的剖面圖。 4 is a two-wafer integrated bridge rectifier according to an embodiment of the present invention, which is integrated into the control A cross-sectional view of an equivalent component of the first and second diodes of the CMOS process of the circuit.
圖5是本發明另一實施例的二晶片整合橋式整流器中,被整合進控制電路的CMOS製程之第一與第二二極體的等效元件的剖面圖。 5 is a cross-sectional view showing an equivalent element of a first and a second diode of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to another embodiment of the present invention.
圖2是本發明一實施例的二晶片整合橋式整流器的示意圖。 2 is a schematic diagram of a two-wafer integrated bridge rectifier in accordance with an embodiment of the present invention.
請參照圖2,本實施例的二晶片整合橋式整流器其等效電路包括第一至第四二極體12、14、16與18,其中第一二極體12的陽極與第二二極體14的陽極耦接至輸出地端,第一二極體12的陰極與第三二極體16的陽極耦接至輸入端,第二二極體14的陰極與第四二極體18的陽極耦接至輸入地端,且第三二極體16的陰極與第四二極體18的陰極耦接至輸出端。此橋式整流器包括:整合了第三二極體16與第四二極體18的對稱式PIN二極體20,以及第一二極體12與第二二極體14的等效元件。對稱式PIN二極體20位於第一晶片22中,其中屬於第三二極體16的部分的結構與屬於第四二極體18的部分的結構對稱,如圖3所示。上述等效元件被整合進一控制電路19的CMOS製程,而與所述控制電路共存於第二晶片24中。 Referring to FIG. 2, the equivalent circuit of the two-wafer integrated bridge rectifier of the present embodiment includes first to fourth diodes 12, 14, 16, and 18, wherein the anode and the second diode of the first diode 12 are The anode of the body 14 is coupled to the output ground, the cathode of the first diode 12 and the anode of the third diode 16 are coupled to the input end, and the cathode of the second diode 14 and the cathode of the second diode 18 The anode is coupled to the input ground, and the cathode of the third diode 16 and the cathode of the fourth diode 18 are coupled to the output. The bridge rectifier includes a symmetrical PIN diode 20 in which the third diode 16 and the fourth diode 18 are integrated, and an equivalent component of the first diode 12 and the second diode 14. The symmetrical PIN diode 20 is located in the first wafer 22, wherein the structure of the portion belonging to the third diode 16 is symmetrical with the structure of the portion belonging to the fourth diode 18, as shown in FIG. The above equivalent elements are integrated into a CMOS process of a control circuit 19, and coexist in the second wafer 24 with the control circuit.
圖3是本發明實施例的二晶片整合橋式整流器中,整合了第三二極體16與第四二極體18的對稱式PIN二極體20的一例 的剖面圖。 3 is a diagram showing an example of a symmetrical PIN diode 20 in which a third diode 16 and a fourth diode 18 are integrated in a two-wafer integrated bridge rectifier according to an embodiment of the present invention. Sectional view.
請參照圖3,對稱式PIN二極體20包括:共陰極314、濃摻雜N基底300、作為本質層的N型淡摻雜層302、二個P井304、各P井304的P型濃摻雜接觸區308、介電層310,以及電性連接此二接觸區308的陽極312。在此對稱式PIN二極體20中,屬於第三二極體16的部分的結構與屬於第四二極體18的部分的結構對稱。 Referring to FIG. 3, the symmetric PIN diode 20 includes a common cathode 314, a heavily doped N substrate 300, an N-type lightly doped layer 302 as an intrinsic layer, two P wells 304, and a P-type of each P well 304. The doped contact region 308, the dielectric layer 310, and the anode 312 electrically connected to the two contact regions 308. In this symmetric PIN diode 20, the structure of the portion belonging to the third diode 16 is symmetrical with the structure of the portion belonging to the fourth diode 18.
其中,濃摻雜N基底300配置於共陰極314上,其例如為一矽基底。N型淡摻雜層302配置於濃摻雜N基底300上,例如為一N淡摻雜磊晶層,其摻質濃度較低。二個P井304位於N型淡摻雜層302中,且分別屬於第三二極體16與第四二極體18。介電層310覆蓋N型淡摻雜層302及P井304。二個陽極312分別經由二接觸區308電性連接二P井304,而分別作為第三二極體16的陽極與第四二極體18的陽極。此對稱式PIN二極體20可更包括各自環繞所述二個P井304之一的兩個P型的護環(guard ring)306,用以平均分散施加之高電壓。 The heavily doped N substrate 300 is disposed on the common cathode 314, which is, for example, a germanium substrate. The N-type lightly doped layer 302 is disposed on the heavily doped N substrate 300, such as an N lightly doped epitaxial layer, which has a low dopant concentration. Two P wells 304 are located in the N-type doped layer 302 and belong to the third diode 16 and the fourth diode 18, respectively. Dielectric layer 310 covers N-type lightly doped layer 302 and P well 304. The two anodes 312 are electrically connected to the two P wells 304 via the two contact regions 308, respectively, and serve as anodes of the third diode 16 and anodes of the fourth diode 18, respectively. The symmetrical PIN diode 20 can further include two P-type guard rings 306 each surrounding one of the two P-wells 304 for evenly distributing the applied high voltage.
在此須特別說明的是,上述的對稱式PIN二極體20只是本發明可使用的對稱式PIN二極體的一例而已,其他具有第三二極體與第四二極體的共陰極、與該共陰極連接的至少一N摻雜層、第三二極體與第四二極體各自的陽極、分別與該二陽極連接的二個P摻雜層,以及各該P摻雜層與該N摻雜層之間的本質層的PIN二極體亦可使用。 It should be particularly noted that the symmetric PIN diode 20 described above is only one example of a symmetric PIN diode that can be used in the present invention, and other common cathodes having a third diode and a fourth diode. At least one N-doped layer connected to the common cathode, an anode of each of the third diode and the fourth diode, two P-doped layers respectively connected to the two anodes, and each of the P-doped layers A PIN diode of the intrinsic layer between the N-doped layers can also be used.
圖4是本發明一實施例的二晶片整合橋式整流器中,被整合進控制電路的CMOS製程之第一二極體12與第二二極體14的等效元件的剖面圖。 4 is a cross-sectional view showing an equivalent element of a first diode 12 and a second diode 14 of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to an embodiment of the present invention.
請參照圖4,所述等效元件有一對稱式金氧半結構,其中屬於第一二極體12的部分的結構與屬於第二二極體14的部分的結構對稱。被整合進同一CMOS製程的控制電路亦具有相同材質的金氧半結構。上述對稱式金氧半結構例如為一對稱式LDMOS結構,其屬於一種高壓元件,包括:P基底400、二個N型埋入區402、二個第一N井404、二個場氧化層406、二個第二N井408、P井410、第二N井408的N型濃摻雜接觸區412、P井410的P型濃摻雜接觸區414、二個閘極416、介電層418、二個陰極420及共陽極422。此對稱式LDMOS結構及被整合進同一CMOS製程的控制電路的CMOS元件例如為線寬1微米的700V高壓元件。 Referring to FIG. 4, the equivalent element has a symmetrical metal oxide half structure in which the structure of the portion belonging to the first diode 12 is symmetrical with the structure of the portion belonging to the second diode 14. The control circuit integrated into the same CMOS process also has a gold oxide half structure of the same material. The symmetrical gold-oxygen half structure is, for example, a symmetric LDMOS structure, belonging to a high voltage component, comprising: a P substrate 400, two N-type buried regions 402, two first N wells 404, and two field oxide layers 406. Two second N wells 408, a P well 410, a second N well 408, an N-type heavily doped contact region 412, a P-well 410 P-type heavily doped contact region 414, two gates 416, a dielectric layer 418, two cathodes 420 and a common anode 422. The symmetrical LDMOS structure and the CMOS components integrated into the control circuit of the same CMOS process are, for example, 700V high voltage components having a line width of 1 micron.
在上述結構中,P井410位於P基底400中、上述結構的中央。所述二個第一N井404分別位於P井410兩側的P基底400中、所述二個場氧化層406之下,分別屬於第一二極體12與第二二極體14,且摻雜濃度低於P井410,而作為高壓元件的耐壓區。所述二個閘極416各自位於所述二個場氧化層406之一、所述二個第一N井404之一及P井410上。所述二個第二N井408分別位於所述二個第一N井404外側的P基底400中,其分別屬於第一二極體12與第二二極體14,且摻雜濃度高於第一N井404。所述二個N型埋入區402各自位於相鄰的一對第一N井404與第二 N井408之下的P基底400中。第二N井408的N型濃摻雜接觸區412為N型濃摻雜,P井410的P型濃摻雜接觸區414為P型濃摻雜。介電層418覆蓋上述各部分。所述二個陰極420各自穿過介電層418而連接所述二個第二N井408之一的N型濃摻雜接觸區412。共陽極422穿過介電層418而與P井410的P型濃摻雜接觸區414及各閘極416連接。 In the above structure, the P well 410 is located in the P substrate 400 at the center of the above structure. The two first N wells 404 are respectively located in the P substrate 400 on both sides of the P well 410, below the two field oxide layers 406, belonging to the first diode 12 and the second diode 14, respectively. The doping concentration is lower than that of the P well 410 and serves as a withstand voltage region of the high voltage component. The two gates 416 are each located on one of the two field oxide layers 406, one of the two first N wells 404, and the P well 410. The two second N wells 408 are respectively located in the P substrate 400 outside the two first N wells 404, which belong to the first diode 12 and the second diode 14, respectively, and have a higher doping concentration. First N well 404. The two N-type buried regions 402 are each located adjacent to a pair of first N wells 404 and second In the P substrate 400 below the N well 408. The N-type heavily doped contact region 412 of the second N well 408 is N-type heavily doped, and the P-type heavily doped contact region 414 of the P-well 410 is P-type heavily doped. Dielectric layer 418 covers the various portions described above. The two cathodes 420 each pass through a dielectric layer 418 to connect the N-type heavily doped contact regions 412 of one of the two second N-wells 408. The common anode 422 passes through the dielectric layer 418 to connect with the P-type heavily doped contact region 414 of the P-well 410 and the gates 416.
圖5是本發明另一實施例的二晶片整合橋式整流器中,被整合進控制電路的CMOS製程之第一二極體12與第二二極體14的等效元件的剖面圖。 5 is a cross-sectional view showing an equivalent element of a first diode 12 and a second diode 14 of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to another embodiment of the present invention.
請參照圖5,該另一實施例的所述等效元件與前一實施例(圖4)的差異在少了二個閘極416以及共陽極422與各閘極416之間的接觸窗。也就是說,該等效元件同樣有一對稱結構,但不包括在整合了控制電路、第一二極體12與第二二極體14的CMOS製程中所形成的閘導電層。 Referring to FIG. 5, the difference between the equivalent component of the other embodiment and the previous embodiment (FIG. 4) is that there are two gates 416 and a contact window between the common anode 422 and each gate 416. That is to say, the equivalent element also has a symmetrical structure, but does not include the gate conductive layer formed in the CMOS process in which the control circuit, the first diode 12 and the second diode 14 are integrated.
在此須特別說明的是,上述的有閘極對稱式LDMOS結構及無閘極對稱結構只是本發明可使用的第一第二二極體的等效元件的二個例子而已,其他與控制電路的CMOS製程相容且具有第一二與第二二極體的共陽極、與該共陽極連接的P摻雜層、第一與第二二極體各自的陰極,以及分別與該二陰極連接且與該P摻雜層連接的二個N摻雜層的結構亦可使用。 It should be particularly noted that the above-described gate-symmetrical LDMOS structure and the gateless symmetrical structure are only two examples of equivalent components of the first second diode that can be used in the present invention, and other control circuits. CMOS process compatible with a common anode of the first two and second diodes, a P-doped layer connected to the common anode, a cathode of each of the first and second diodes, and respectively connected to the two cathodes And the structure of the two N-doped layers connected to the P-doped layer can also be used.
綜上所述,由於本發明將橋式整流之四個二極體中的兩個整合為一個對稱式PIN二極體,並將另兩個整合進控制電路的 CMOS製程,所以只要用兩個晶片即可組成橋式整流器,而得以簡化電路設計。另外,整合進控制電路的CMOS製程的兩個二極體的等效元件可包括或不包括該CMOS製程中形成的閘導電層。 In summary, the present invention integrates two of the four diodes of the bridge rectification into one symmetrical PIN diode, and integrates the other two into the control circuit. CMOS process, so as long as two wafers can be used to form a bridge rectifier, which simplifies the circuit design. In addition, the equivalent elements of the two diodes of the CMOS process integrated into the control circuit may or may not include the gate conductive layer formed in the CMOS process.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
12、14、16、18‧‧‧二極體 12, 14, 16, 18‧ ‧ diodes
19‧‧‧控制電路 19‧‧‧Control circuit
20‧‧‧對稱式PIN二極體 20‧‧‧Symmetric PIN diode
22‧‧‧第一晶片 22‧‧‧First chip
24‧‧‧第二晶片 24‧‧‧second chip
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US7795987B2 (en) * | 2007-06-16 | 2010-09-14 | Alpha & Omega Semiconductor, Ltd. | Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS |
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