CN106158855A - Two-chip integrated bridge rectifier - Google Patents
Two-chip integrated bridge rectifier Download PDFInfo
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- CN106158855A CN106158855A CN201510204537.4A CN201510204537A CN106158855A CN 106158855 A CN106158855 A CN 106158855A CN 201510204537 A CN201510204537 A CN 201510204537A CN 106158855 A CN106158855 A CN 106158855A
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- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 26
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 4
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000035755 proliferation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The invention provides a two-chip integrated bridge rectifier, which is obtained by integrating two of four diodes for bridge rectification into a symmetrical PIN diode positioned in one chip, and integrating the other two diodes into the CMOS process of a control circuit and coexisting with the control circuit in the other chip. The two-chip integrated bridge rectifier provided by the invention can simplify the circuit design.
Description
Technical field
The invention relates to a kind of bridge rectifier (bridge rectifier), and in particular to one
Plant two integrated chip bridge rectifiers.
Background technology
Traditional bridge rectifier is to couple four PN diode chip for backlight unit in the manner shown in figure 1 to form,
It is used for carrying out transferring alternating current to galvanic operation.
Fig. 1 is the electrical schematic diagram of existing bridge rectifier.Refer to Fig. 1, when input (In) end gives
Positive alternating current, electric current passes through the 3rd diode 16 to outfan, and signal is just, and by the first diode
12, hold and be back to input ground end through the second diode 14 with exporting (Out) between the second diode 14；When
Input gives negative alternating current, and electric current then flow to outfan by the 4th diode 18, and output end signal is also
For just, and by output ground end between first diode the 12, second diode 14 through the first diode 12 times
It flow to input.
As it has been described above, bridge rectifier is i.e. to be transferred to positive voltage when ac signal gives negative voltage,
Use the function reaching rectification for sinusoidal (sin ripple) wave mode voltage.
But, the bridge rectifier of prior art contains four PN diode chip for backlight unit, so its circuit sets
Meter is rather complicated.
Summary of the invention
The present invention provides a kind of two integrated chip bridge rectifiers, and it is by two collection in four diodes
Become a symmetrical expression PIN diode to be positioned in a chip, and be integrated into another two diode controlling electricity
The CMOS processing procedure on road and coexist in control circuit and another chip obtain.
Two its equivalent circuits of integrated chip bridge rectifier of the present invention include first to fourth diode, its
In the anode of the first diode and the anode of the second diode hold with being coupled to output, the moon of the first diode
Pole is coupled to input with the anode of the 3rd diode, the negative electrode of the second diode and the sun of the 4th diode
Pole is coupled to input ground end, and the negative electrode of the negative electrode of the 3rd diode and the 4th diode is coupled to outfan.
This bridge rectifier includes: be integrated with a symmetrical expression PIN diode of the 3rd and the 4th diode
(P-intrinsic-N diode), is positioned in the first chip, wherein belongs to the structure of the part of the 3rd diode
Symmetrical configuration with the part belonging to the 4th diode；And first diode and the first-class of the second diode
Effect element, this equivalence element is integrated into CMOS (CMOS) processing procedure of a control circuit,
And coexist in the second chip with described control circuit.
In one embodiment, described symmetrical expression PIN diode includes: the 3rd diode and the 4th diode
Common cathode and described common cathode be electrically connected with at least one N doped layer, the 3rd diode and the four or two
Pole is managed respective anode, two the P doped layers being electrically connected with described two anodes respectively, and each P and is mixed
Intrinsic layer (intrinsic layer) between diamicton and N doped layer.In one example, described N mixes
Diamicton includes a dense doping N substrate and is configured on described common cathode, and described intrinsic layer includes that N-type is light and mixes
Diamicton and being configured in described dense doping N substrate, and described two P doped layers include being positioned at described N-type
Two P wells in light doped layer.This symmetrical expression PIN diode can also include the retaining ring of more than two, position
In the light doped layer of described N-type, each around one of described two P wells.
In one embodiment, described equivalence element includes a symmetrical structure, wherein belongs to the first diode
The structure of part and the symmetrical configuration of the part belonging to the second diode.Described symmetrical structure has the one or two
The common-anode with the second diode and the P doped layer of described common-anode electric connection, the one or two pole are managed in pole
Pipe and the second respective negative electrode of diode, and be electrically connected with described two negative electrodes respectively and with described P
Two N doped layers that doped layer is electrically connected with.
In one embodiment, described symmetrical structure also includes being electrically connected with described common-anode, being belonging respectively to
First diode and two grids of the second diode, and become a pair title formula gold oxygen half structure.This is symmetrical
Formula gold oxygen half structure can include lateral diffusion metal-oxide half (LDMOS) structure of a symmetrical expression, comprising:
One P substrate；As a P well of described P doped layer, it is positioned in described P substrate；Two N wells,
It is positioned in the P substrate of described P well both sides, is belonging respectively to the first diode and the second diode, and doping
Concentration is less than described P well；Two field oxides, lay respectively at described two N aboveground；Described two
Grid, is each located on one of described two field oxides (Field oxide layer), described two N
One of well and described P are aboveground；As two the 2nd N wells of described two N doped layers, lay respectively at institute
Stating the outside of two N wells, it is belonging respectively to the first diode and the second diode, and doping content
Higher than described two N wells；Described common-anode, is electrically connected with described P well and described two grids；
And first diode and the respective negative electrode of the second diode.
In another embodiment, institute's shape during described symmetrical structure does not include this CMOS processing procedure
The grid conductive layer become.This symmetrical structure comprises the steps that a P substrate；As a P well of described P doped layer,
It is positioned in described P substrate；Two N wells, are positioned in the P substrate of described P well both sides, belong to respectively
In the first diode and the second diode, and doping content is less than described P well；Two field oxides, respectively
It is positioned at described two N aboveground；As 2 the 2nd N wells of described two N doped layers, lay respectively at
The outside of described two N wells, it is belonging respectively to the first diode and the second diode, and it is dense to adulterate
Degree is higher than described two N wells；Described common-anode, is electrically connected with described P well；And the one or two
Pole pipe and the second respective negative electrode of diode.
Owing to two in the four of bridge rectifier diodes are integrated into a symmetrical expression PIN bis-by the present invention
Pole is managed, and another two is integrated into the CMOS processing procedure of control circuit, as long as so with two chips
Composition bridge rectifier, and it is simplified circuit design.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is the electrical schematic diagram of existing bridge rectifier；
Fig. 2 is the schematic diagram of the two integrated chip bridge rectifiers of one embodiment of the invention；
Fig. 3 is in the two integrated chip bridge rectifiers of one embodiment of the invention, is integrated with the 3rd diode
16 and the 4th profile of an example of symmetrical expression PIN diode 20 of diode 18；
Fig. 4 is in the two integrated chip bridge rectifiers of one embodiment of the invention, is integrated into control circuit
The first diode 12 of CMOS processing procedure and the profile of equivalence element of the second diode 14；
Fig. 5 is in the two integrated chip bridge rectifiers of another embodiment of the present invention, is integrated into control electricity
First diode 12 of the CMOS processing procedure on road and the profile of the equivalence element of the second diode 14.
Description of reference numerals:
12: the first diodes；
14: the second diodes；
16: the three diodes；
18: the four diodes；
19: control circuit；
20: symmetrical expression PIN diode；
22: the first chips；
24: the second chips；
300: dense doping N substrate；
The light doped layer of 302:N type；
304:P well；
306: retaining ring；
308:P type dense doping contact area；
310: dielectric layer；
312: anode；
314: common cathode；
400:P substrate；
402:N type embedment district；
404: the one N wells；
406: field oxide；
408: the two N wells；
410:P well；
412:N type dense doping contact area；
414:P type dense doping contact area；
416: grid；
418: dielectric layer；
420: negative electrode；
422: common-anode.
Detailed description of the invention
Fig. 2 is the schematic diagram of the two integrated chip bridge rectifiers of one embodiment of the invention.
Refer to Fig. 2, two its equivalent circuits of integrated chip bridge rectifier of the present embodiment include first to
4th diode 12,14,16 and 18, the wherein anode of the first diode 12 and the second diode 14
Anode be coupled to output hold, the negative electrode of the first diode 12 and the anode of the 3rd diode 16 couple
It is coupled to input ground end to input, the negative electrode of the second diode 14 and the anode of the 4th diode 18,
And the 3rd diode 16 negative electrode and the negative electrode of the 4th diode 18 be coupled to outfan.This bridge rectifier
Device includes: be integrated with the 3rd diode 16 and the symmetrical expression PIN diode 20 of the 4th diode 18, with
And first diode 12 and the equivalence element of the second diode 14.Symmetrical expression PIN diode 20 is positioned at
In one chip 22, wherein belong to the 3rd diode 16 part structure with belong to the 4th diode 18
The symmetrical configuration of part, as shown in Figure 3.Above-mentioned equivalence element is integrated into the CMOS of a control circuit 19
Processing procedure, and coexist in the second chip 24 with described control circuit.
Fig. 3 is in the two integrated chip bridge rectifiers of one embodiment of the invention, is integrated with the 3rd diode
16 and the 4th profile of an example of symmetrical expression PIN diode 20 of diode 18.
Refer to Fig. 3, symmetrical expression PIN diode 20 includes: common cathode 314, dense doping N substrate 300,
302, two P wells 304 of the light doped layer of N-type, the dense doping of p-type of each P well 304 as intrinsic layer
Contact area 308, dielectric layer 310, and it is electrically connected with the anode of this two p-type dense doping contact area 308
312.In this symmetrical expression PIN diode 20, belong to the 3rd diode 16 part structure with belong to
The symmetrical configuration of the part of the 4th diode 18.
Wherein, dense doping N substrate 300 is configured on common cathode 314, its for example, one silicon base.N
The light doped layer of type 302 is configured in dense doping N substrate 300, for example, one N light doping epitaxial layer, its
Dopant concentration is relatively low.Two P wells 304 are positioned in the light doped layer of N-type 302, and are belonging respectively to the three or two
Pole pipe 16 and the 4th diode 18.Dielectric layer 310 covers the light doped layer of N-type 302 and P well 304.
Two anodes 312 are electrically connected with two P wells 304 by two p-types dense doping contact area 308 respectively, and divide
Not as anode and the anode of the 4th diode 18 of the 3rd diode 16.This symmetrical expression PIN diode
20 retaining rings (guard ring) that can also include respective two p-types around one of described two P wells 304
306, the high voltage applied in order to average dispersion.
Should be specified at this, the above-mentioned symmetrical expression PIN diode 20 simply present invention is spendable
One example of symmetrical expression PIN diode, other have the 3rd diode and the common cathode of the 4th diode,
At least one N doped layer, the 3rd diode and the 4th respective anode of diode that are connected with this common cathode,
Two the P doped layers being connected with this two anode respectively, and respectively between this P doped layer and this N doped layer
The PIN diode of intrinsic layer be used as.
Fig. 4 is in the two integrated chip bridge rectifiers of one embodiment of the invention, is integrated into control circuit
The first diode 12 of CMOS processing procedure and the profile of equivalence element of the second diode 14.
Refer to Fig. 4, described equivalence element has a symmetrical expression gold oxygen half structure, wherein belongs to the one or two pole
The symmetrical configuration of the structure of the part of pipe 12 and the part belonging to the second diode 14.It is integrated into same
The control circuit of CMOS processing procedure also has the golden oxygen half structure of identical material.Above-mentioned symmetrical expression gold oxygen half hitch
Structure for example, one symmetrical expression LDMOS structure, it belongs to a kind of high voltage device, including: P substrate 400,
Two N-type embedment district 402, two N wells, 406, two the 2nd N of 404, two field oxides
Well 408, the N-type dense doping contact area 412 of P well the 410, the 2nd N well 408, the p-type of P well 410
414, two, dense doping contact area grid 416,418, two negative electrodes 420 of dielectric layer and common-anode 422.
This symmetrical expression LDMOS structure and be integrated into the cmos element of control circuit of same CMOS processing procedure
The for example, 700V high voltage device of live width 1 micron.
In said structure, P well 410 is positioned in P substrate 400, the central authorities of said structure.Described two
An individual N well 404 lays respectively in the P substrate 400 of P well 410 both sides, described two field oxides
Under 406, it is belonging respectively to the first diode 12 and the second diode 14, and doping content is less than P well
410, and as the resistance to nip of high voltage device.Described two grids 416 are each located on the oxidation of described two fields
On one of layer one of 406, described two N wells 404 and P well 410.Described two the 2nd N wells
408 lay respectively in the P substrate 400 outside described two N wells 404, and it is belonging respectively to first
Diode 12 and the second diode 14, and doping content is higher than a N well 404.Described two N-types
Embedment district 402 is each located on the P substrate under adjacent pair the oneth N well 404 and the 2nd N well 408
In 400.The N-type dense doping contact area 412 of the 2nd N well 408 is the dense doping of N-type, P well 410
P-type dense doping contact area 414 is the dense doping of p-type.Dielectric layer 418 covers each part mentioned above.Described two
The N-type that individual negative electrode 420 each connects one of described two the 2nd N wells 408 through dielectric layer 418 is dense
Doping contact area 412.Through dielectric layer 418, dense doping connects common-anode 422 with the p-type of P well 410
Touch district 414 and each grid 416 connects.
Fig. 5 is in the two integrated chip bridge rectifiers of another embodiment of the present invention, is integrated into control electricity
First diode 12 of the CMOS processing procedure on road and the profile of the equivalence element of the second diode 14.
Refer to Fig. 5, the described equivalence element of this another embodiment and the difference of previous embodiment (Fig. 4)
At the contact hole lacked between two grids 416 and common-anode 422 and each grid 416.It is to say,
This equivalence element has a symmetrical structure equally, but not included in being integrated with control circuit, the first diode 12
The grid conductive layer formed in CMOS processing procedure with the second diode 14.
Should be specified at this, above-mentioned has grid symmetrical expression LDMOS structure and non-grid symmetrical
Structure is two examples of the equivalence element of spendable the one the second diodes of the present invention, other
Compatible with the CMOS processing procedure of control circuit and have the one or two with the common-anode of the second diode and this is common
Anode connect P doped layer, the respective negative electrode of first and second diode, and respectively with this two negative electrode
The structure of two the N doped layers connecting and being connected with this P doped layer is used as.
In sum, due to the present invention two in the four of bridge rectifier diodes are integrated into one right
Title formula PIN diode, and another two is integrated into the CMOS processing procedure of control circuit, as long as so with two
Individual chip can form bridge rectifier, and is simplified circuit design.It addition, be integrated into control circuit
The equivalence element of two diodes of CMOS processing procedure can include or not include this CMOS processing procedure is formed
Grid conductive layer.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a two integrated chip bridge rectifier, its equivalent circuit includes first to fourth diode, its
Being characterised by, the anode of the first diode and the anode of the second diode are held with being coupled to an output, and first
The negative electrode of diode and the anode of the 3rd diode are coupled to an input, the negative electrode of the second diode and
The anode of four diodes is coupled to an input ground end, and the negative electrode of the 3rd diode and the moon of the 4th diode
Pole is coupled to an outfan, and described bridge rectifier includes:
It is integrated with a symmetrical expression PIN diode of the 3rd diode and the 4th diode, is positioned at the first chip
In, wherein belong to the symmetrical configuration of structure and the part belonging to the 4th diode of the part of the 3rd diode；
And
First diode and an equivalence element of the second diode, described equivalence element is integrated into a control
One CMOS processing procedure of circuit, and coexist in the second chip with described control circuit.
Two integrated chip bridge rectifiers the most according to claim 1, it is characterised in that described right
Title formula PIN diode includes: the 3rd diode and the common cathode of the 4th diode and described common cathode electricity
Property connect at least one N doped layer, the 3rd diode and the 4th respective anode of diode, respectively with institute
State two P doped layers that two anodes are electrically connected with, and each described P doped layer and described N doped layer it
Between intrinsic layer.
Two integrated chip bridge rectifiers the most according to claim 2, it is characterised in that described
In symmetrical expression PIN diode,
Described N doped layer includes a dense doping N substrate, is configured on described common cathode；
Described intrinsic layer includes the light doped layer of N-type, is configured in described dense doping N substrate；And
Described two P doped layers include two the P wells being positioned in the light doped layer of described N-type.
Two integrated chip bridge rectifiers the most according to claim 3, it is characterised in that symmetrical expression
PIN diode also includes: the retaining ring of more than two, is positioned in the light doped layer of described N-type, and each ring
Around one of described two P wells.
Two integrated chip bridge rectifiers the most according to claim 1, it is characterised in that described etc.
Effect element include a symmetrical structure, wherein belong to the first diode part structure with belong to the two or two pole
The symmetrical configuration of the part of pipe.
Two integrated chip bridge rectifiers the most according to claim 5, it is characterised in that described right
Structure is claimed to have the first diode and the common-anode of the second diode and the P of described common-anode electric connection
Doped layer, the first diode and the respective negative electrode of the second diode, and electrical with described two negative electrodes respectively
Two the N doped layers connected and be electrically connected with described P doped layer.
Two integrated chip bridge rectifiers the most according to claim 6, it is characterised in that described right
Claim structure also to include with described common-anode to be electrically connected with, be belonging respectively to the first diode and the second diode
Two grids, and become a pair title formula gold oxygen half structure.
Two integrated chip bridge rectifiers the most according to claim 7, it is characterised in that described right
Title formula gold oxygen half structure includes a symmetrical expression lateral diffusion metal-oxide half structure, described symmetrical expression horizontal proliferation gold
Oxygen half structure includes:
One P substrate；
As a P well of described P doped layer, it is positioned in described P substrate；
Two N wells, are positioned in the described P substrate of described P well both sides, are belonging respectively to the one or two pole
Pipe and the second diode, and doping content is less than described P well；
Two field oxides, lay respectively at described two N aboveground；
Described two grids, be each located on one of described two field oxides, described two N wells it
One and described P is aboveground；
As two the 2nd N wells of described two N doped layers, lay respectively at described two N wells
Outside, it is belonging respectively to the first diode and the second diode, and doping content is higher than described two first
N well；
Described common-anode, is electrically connected with described P well and described two grids；And
First diode and the respective negative electrode of the second diode.
Two integrated chip bridge rectifiers the most according to claim 6, it is characterised in that described right
Title structure does not include the grid conductive layer formed in described CMOS processing procedure.
Two integrated chip bridge rectifiers the most according to claim 9, it is characterised in that described
Symmetrical structure includes:
One P substrate；
As a P well of described P doped layer, it is positioned in described P substrate；
Two N wells, are positioned in the described P substrate of described P well both sides, are belonging respectively to the one or two pole
Pipe and the second diode, and doping content is less than described P well；
Two field oxides, lay respectively at described two N aboveground；
As two the 2nd N wells of described two N doped layers, lay respectively at described two N wells
Outside, it is belonging respectively to the first diode and the second diode, and doping content is higher than described two first
N well；
Described common-anode, is electrically connected with described P well；And
First diode and the respective negative electrode of the second diode；
Two N-type embedment districts, lay respectively at a pair adjacent N well and the 2nd N well and another are to phase
Under an adjacent N well and the 2nd N well.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104108987 | 2015-03-20 | ||
| TW104108987A TWI545882B (en) | 2015-03-20 | 2015-03-20 | Two chips integrtated bridge rectifier |
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| Publication Number | Publication Date |
|---|---|
| CN106158855A true CN106158855A (en) | 2016-11-23 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510204537.4A Pending CN106158855A (en) | 2015-03-20 | 2015-04-27 | Two-chip integrated bridge rectifier |
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| CN (1) | CN106158855A (en) |
| TW (1) | TWI545882B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6057961A (en) * | 1983-08-08 | 1985-04-03 | アメリカン テレフオン アンド テレグラフ カムパニ− | Complementary metal-oxide semiconductor device |
| EP1808900A2 (en) * | 1995-06-02 | 2007-07-18 | SILICONIX Incorporated | Multiple phase motor driver with bidirectional blocking accumulation-mode trench power mosfets |
| CN101617382A (en) * | 2007-06-16 | 2009-12-30 | 万国半导体股份有限公司 | In symmetry that is integrated with the transient voltage inhibitor and asymmetric electromagnetic interface filter, obtain the method for linear capacitance |
| CN101901806A (en) * | 2009-05-26 | 2010-12-01 | 奇高电子股份有限公司 | AC-DC conversion integrated element and integrated circuit using same |
-
2015
- 2015-03-20 TW TW104108987A patent/TWI545882B/en not_active IP Right Cessation
- 2015-04-27 CN CN201510204537.4A patent/CN106158855A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6057961A (en) * | 1983-08-08 | 1985-04-03 | アメリカン テレフオン アンド テレグラフ カムパニ− | Complementary metal-oxide semiconductor device |
| EP1808900A2 (en) * | 1995-06-02 | 2007-07-18 | SILICONIX Incorporated | Multiple phase motor driver with bidirectional blocking accumulation-mode trench power mosfets |
| CN101617382A (en) * | 2007-06-16 | 2009-12-30 | 万国半导体股份有限公司 | In symmetry that is integrated with the transient voltage inhibitor and asymmetric electromagnetic interface filter, obtain the method for linear capacitance |
| CN101901806A (en) * | 2009-05-26 | 2010-12-01 | 奇高电子股份有限公司 | AC-DC conversion integrated element and integrated circuit using same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI545882B (en) | 2016-08-11 |
| TW201635690A (en) | 2016-10-01 |
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