CN116113309B

CN116113309B - Low-offset Hall device adopting double protection rings and application method thereof

Info

Publication number: CN116113309B
Application number: CN202310388847.0A
Authority: CN
Inventors: 徐跃; 刘源
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2023-04-13
Filing date: 2023-04-13
Publication date: 2023-07-25
Anticipated expiration: 2043-04-13
Also published as: CN116113309A

Abstract

The invention discloses a low-offset Hall device adopting double protection rings and a use method thereof, wherein the low-offset Hall device adopting double protection rings comprises a transverse layer group, the transverse layer group comprises a P-type substrate, an N+ buried layer arranged in the central area of the P-type substrate and a P-buried layer arranged in the central area of the top of the N+ buried layer, an N well active area is arranged above the P-buried layer, and the N+ buried layer and the P-buried layer form the transverse protection rings; the side wall layer group comprises a P-type epitaxial layer arranged outside the N-well active region, a high-voltage N-well connected with the top of the N+ buried layer is arranged in the P-type epitaxial layer, a high-voltage P-well connected with the top of the P-type substrate is arranged in the P-type epitaxial layer, the high-voltage P-well is arranged outside the high-voltage N-well, and the P-type epitaxial layer and the N+ buried layer form a longitudinal protection ring; the Hall device has low offset, high sensitivity and strong anti-interference capability.

Description

Low-offset Hall device adopting double protection rings and application method thereof

Technical Field

The invention relates to the technical field of sensors, in particular to a low-offset Hall device adopting double protection rings and a use method thereof.

Background

In recent years, a hall sensor has become a mainstream magnetic sensor because of advantages such as low cost, low power consumption, high integration level and the like. The device can detect alternating current and direct current magnetic fields and generate output electric signals proportional to the magnetic field intensity, and is widely used in the fields of automobile control, battery chargers, brushless direct current motors, power meters, photovoltaic inverters and the like. Currently, hall sensors are developing towards high linearity, high precision and broadband, and higher requirements are being put on the high sensitivity and low offset characteristics of hall devices.

Silicon-based hall devices are most widely studied and used by virtue of low cost, high temperature stability, and good compatibility with standard CMOS processes. However, the integrated CMOS Hall device adopts the N well with higher doping concentration as an active region, so that the influence of ionized impurity scattering on carrier movement is increased, the mobility of the Hall device is reduced, and the sensitivity of the Hall device is lower. On the other hand, the output offset of the Hall device is very large due to uneven impurity concentration distribution of the N well, packaging stress and alignment error of a mask plate between a device contact hole and the N well in the CMOS process, and the offset voltage can reach several millivolts to tens of millivolts, so that weak Hall signals are submerged. In addition, the traditional Hall device generally only adopts a P-well ring to isolate an active region, and cannot overcome the interference of high-frequency signals and substrate noise in a circuit, so that the anti-interference capability of the Hall device is relatively poor, and the silicon-based Hall device cannot meet the working requirements of low magnetic field and high resolution, so that the critical technical problems of reducing the disorder of the Hall device, improving the sensitivity and the signal to noise ratio are urgently needed to be solved by the silicon-based Hall sensor.

Disclosure of Invention

This section is intended to summarize some aspects of embodiments of the invention and to briefly introduce some preferred embodiments, which may be simplified or omitted from the present section and description abstract and title of the application to avoid obscuring the objects of this section, description abstract and title, and which is not intended to limit the scope of this invention.

The present invention has been made in view of the above and/or problems occurring in the prior art.

Therefore, the technical problems to be solved by the invention are the problems of large mismatch, low sensitivity, poor noise resistance and poor interference resistance of the Hall device in the existing CMOS process.

In order to solve the technical problems, the invention provides the following technical scheme: a low offset Hall device using double guard rings comprises,

the lateral layer group comprises a P-type substrate, an N+ buried layer arranged in the central area of the P-type substrate and a P-buried layer arranged in the central area of the top of the N+ buried layer, an N well active region is arranged above the P-buried layer, and the N+ buried layer and the P-buried layer form a lateral protection ring;

the side wall layer group comprises a P-type epitaxial layer arranged outside the N-well active region, a high-voltage N-well connected with the top of the N+ buried layer is arranged in the P-type epitaxial layer, a high-voltage P-well connected with the top of the P-type substrate is arranged in the P-type epitaxial layer, the high-voltage P-well is arranged outside the high-voltage N-well, and the P-type epitaxial layer and the high-voltage N-well form a longitudinal protection ring.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: the side wall layer group is of a symmetrical structure and is symmetrical about a first symmetrical axis; the N well active region is of a symmetrical structure and symmetrical about a second symmetry axis, and the first symmetry axis and the second symmetry axis are coincident.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: the edge of the N well active region is uniformly distributed with first N+ regions, the first N+ regions are symmetrical about a second symmetry axis, and the first N+ regions are placed parallel to the edge of the N well active region.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: and the four first N+ regions are provided with metal to form four bias electrodes.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: a second N+ region is arranged in the N well active region at the center of the adjacent first N+ region, the second N+ region is symmetrical about a second symmetry axis, and the second N+ region is placed parallel to the edge of the N well active region;

the first n+ region is larger in size than the second n+ region.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: the four second N+ regions are provided with metal to form four output electrodes;

the two output electrodes on opposite angles are short-circuited through a metal connecting wire.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: and a third N+ region is arranged on the surface of the high-voltage N well, and metal is arranged on the third N+ region to form a first contact electrode.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: a first P+ region is covered on the non-electrode part above the N well active region;

and a second P+ region is arranged on the surface of the high-voltage P well, and metal is arranged on the second P+ region to form a second contact electrode.

As a preferable scheme of the low offset hall device adopting the double protection rings, the invention comprises the following steps: and isolation shallow grooves are arranged between the first N+ region and the third N+ region, between the first N+ region and the first P+ region, and between the third N+ region and the second P+ region.

The invention also discloses a use method of the low-offset Hall device adopting the double protection rings, which comprises the following steps:

inputting current or voltage bias signals with equal magnitudes and opposite directions to two opposite bias electrodes;

the other two opposite bias electrodes are grounded;

the Hall current or Hall voltage signal is output between the output electrodes;

the first contact electrode is connected with a high level; the second contact electrode is grounded.

The invention has the beneficial effects that: the Hall device has low offset, high sensitivity and strong anti-interference capability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic top view of a low offset Hall device employing dual guard rings according to one embodiment of the present invention;

FIG. 2 is a schematic diagram showing the relative positions of the N-well active region and the outer profile of a low offset Hall device using dual guard rings according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a low offset Hall device using dual guard rings according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a dual guard ring structure of a low offset Hall device using dual guard rings according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an operational bias structure of a low offset Hall device employing dual guard rings according to an embodiment of the present invention;

fig. 6 is a graph showing the output offset contrast obtained by three-dimensional simulation of the structure of the cross-shaped hall device according to the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration only, and in which is shown by way of illustration only, and in which the scope of the invention is not limited for ease of illustration. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Further still, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Example 1

Referring to fig. 1 and 3, a schematic top view and a schematic cross-sectional structure of a low-offset hall device using a double guard ring according to an embodiment of the present invention are provided, where the embodiment provides a low-offset hall device using a double guard ring, including,

the device comprises a transverse layer group 100, wherein the transverse layer group 100 comprises a P-type substrate 101, an N+ buried layer 102 arranged in the central area of the P-type substrate 101 and a P-buried layer 103 arranged in the central area of the top of the N+ buried layer 102, an N well active region 104 is arranged above the P-buried layer 103, and the N+ buried layer 102 and the P-buried layer 103 form a transverse protection ring;

the n+ buried layer 102 is located above the center of the P-type substrate 101, and the n+ buried layer 102 is partially embedded in the P-type substrate 101.

In particular, the P-type substrate 101 may be a semiconductor silicon material,

the side wall layer group 200, the side wall layer group 200 comprises a P-type epitaxial layer 201 arranged outside the N-well active region 104, a high-voltage N-well 202 connected with the top of the N+ buried layer 102 is arranged in the P-type epitaxial layer 201, a high-voltage P-well 203 connected with the top of the P-type substrate 101 is arranged in the P-type epitaxial layer 201, the high-voltage P-well 203 is arranged outside the high-voltage N-well 202, and the P-type epitaxial layer 201 and the high-voltage N-well 202 form a longitudinal protection ring.

A P-type epitaxial layer 201 with a certain thickness is arranged between the high-voltage P-well 203 and the high-voltage N-well 202 at intervals.

The double guard rings according to the present invention are a longitudinal guard ring and a transverse guard ring, respectively, and refer to fig. 4. The lateral guard ring is a PN junction formed between the n+ buried layer 102 and the P-buried layer 103. The longitudinal guard ring is a PN junction formed between the high voltage N-well 202 and the P-type epitaxial layer 201.

Further, referring to fig. 2, the side wall layer 200 is symmetrical about the first symmetry axis Y1; the N-well active region 104 has a symmetrical structure, and is symmetrical about a second symmetry axis Y2, where the first symmetry axis Y1 and the second symmetry axis Y2 coincide.

Specifically, referring to fig. 2 (a), square side-wall layer set 200 is symmetrical about a first symmetry axis Y1, corner-cut square N-well active region 104 is symmetrical about a second symmetry axis Y2, the first n+ regions 104a are uniformly distributed at the edge of N-well active region 104, symmetrical about a second symmetry axis Y2, the second n+ regions 104b are uniformly distributed at the edge of N-well active region 104, symmetrical about a second symmetry axis Y2, and the first n+ regions 104a and the second n+ regions 104b are disposed parallel to the edge of N-well active region 104. The second n+ regions 104b are distributed over the N-well active regions 104 in the centers of adjacent two first n+ regions.

Referring to fig. 2 (b), the regular octagonal sidewall layer 200 is symmetrical about a first symmetry axis Y1, the corner cut diamond-shaped N-well active region 104 is symmetrical about a second symmetry axis Y2, the first n+ regions 104a are uniformly distributed at the edges of the N-well active region 104, symmetrical about a second symmetry axis Y2, the second n+ regions 104b are uniformly distributed at the edges of the N-well active region 104, symmetrical about a second symmetry axis Y2, and the first n+ regions 104a and the second n+ regions 104b are disposed parallel to the edges of the N-well active region 104. The second n+ regions 104b are distributed over the N-well active regions 104 in the centers of adjacent two first n+ regions.

Referring to fig. 2 (c), square sidewall stack 200 is symmetrical about a first symmetry axis Y1, the truncated diamond-shaped N-well active region 104 is symmetrical about a second symmetry axis Y2, the first n+ regions 104a are uniformly distributed at the edges of the N-well active region 104, symmetrical about the second symmetry axis Y2, the second n+ regions 104b are uniformly distributed at the edges of the N-well active region 104, symmetrical about the second symmetry axis Y2, and the first n+ regions 104a and the second n+ regions 104b are disposed parallel to the edges of the N-well active region 104. The second n+ regions 104b are distributed over the N-well active regions 104 in the centers of adjacent two first n+ regions.

Referring to fig. 2 (d), the circular sidewall layer 200 is symmetrical about a first symmetry axis Y1, the truncated diamond-shaped N-well active region 104 is symmetrical about a second symmetry axis Y2, the first n+ regions 104a are uniformly distributed at the edges of the N-well active region 104, symmetrical about the second symmetry axis Y2, the second n+ regions 104b are uniformly distributed at the edges of the N-well active region 104, symmetrical about the second symmetry axis Y2, and the first n+ regions 104a and the second n+ regions 104b are disposed parallel to the edges of the N-well active region 104. The second n+ regions 104b are distributed over the N-well active regions 104 in the centers of adjacent two first n+ regions.

The edges of the N-well active region 104 are uniformly distributed with the first n+ regions 104a, the first n+ regions 104a are symmetrical about the second symmetry axis Y2, and the first n+ regions 104a are disposed parallel to the edges of the N-well active region 104.

Metal is disposed on each of the four first n+ regions 104a, forming four bias electrodes A, B, C and D.

A second n+ region 104b is arranged in the N-well active region at the center of the adjacent first n+ region 104a, the second n+ region 104b is symmetrical about a second symmetry axis Y2, and the second n+ region 104b is placed parallel to the edge of the N-well active region 104;

the first n+ region 104a is larger in size than the second n+ region 104b.

The two first n+ regions 104a of the diagonal are at the same distance from the second n+ region 104b therebetween.

The four second n+ regions 104b are all provided with metal, forming four output electrodes E, F, G and H;

the two opposite output electrodes E and H and F and G are shorted by metal wiring.

The surface of the high-voltage N well 202 is provided with a third n+ region 104c, and the third n+ region 104c is provided with metal, so as to form a first contact electrode J.

The non-electrode portion above the N-well active region 104 is covered with a first p+ region 104d.

The surface of the high-voltage P well 203 is provided with a second P+ region 203a, and the second P+ region 203a is provided with metal to form a second contact electrode K.

An isolation shallow trench 300 is provided between the first n+ region 104a and the third n+ region 104c, between the first n+ region 104a and the first p+ region 104d, and between the third n+ region 104c and the second p+ region 203a.

Further, the role of the hierarchy used will be described in detail,

the P-buried layer 103 can control the doping distribution, and form a more uniform PN junction, namely a transverse PN junction, with the N+ buried layer 102, so that the impurity concentration distribution at the bottom of the N-well active region 104 is improved, the symmetry of the Hall device is improved, and the output offset is reduced.

The built-in electric field formed by the transverse PN junction can reduce current loss at the bottom of the N-well active region 104 and reduce external noise interference when the device works.

A depletion layer is formed between the first p+ region 104d and the N-well 104, thereby increasing the current transport path, avoiding the short circuit effect, and also reducing the N-well thickness to increase its current dependent sensitivity. The first p+ region 104d may also form a PMOS transistor, which is a "buried channel" device, so that the flicker noise and the surface loss of the current of the device can be effectively reduced, and the hall voltage can be increased.

A PN junction is formed between the high-voltage N well 202 and the P-type epitaxial layer 201, namely the longitudinal protection ring, so that the transverse leakage current and 1/f noise are effectively reduced.

According to the invention, the N+ buried layer 102 and the P-buried layer 103 are adopted to form a transverse PN junction as a protection ring, so that the PN junction between the original P-type epitaxial layer and the N-well active region is replaced, the impurity concentration distribution of the N-well active region 104 is effectively improved, the output imbalance of the Hall device caused by Gaussian distribution of the impurity concentration of the N-well active region 104 is reduced, the formed PN junction depletion layer is wider, the anti-interference capability of the Hall device is further improved, and the bottom leakage current is reduced.

The high-voltage N well 202 is in contact with the N+ buried layer 102, the first contact electrode J at the top of the high-voltage N well 202 is connected with a high level, so that the N+ buried layer 102 is connected with a high level, a transverse PN junction between the N+ buried layer 102 and the P-buried layer 103 is reversely biased, a transverse PN junction depletion layer is further widened, the anti-interference capability of the Hall device is stronger, the offset is smaller, meanwhile, the effective depth of the N well active region 104 is reduced, and the sensitivity of the Hall device is improved. The high-voltage N well 202 can also form a longitudinal PN junction with the P-type epitaxial layer 201, so that the transverse leakage current and noise of the Hall device are further reduced, and double protection is achieved on the Hall device.

Example 2

Referring to fig. 5 and 6, the present embodiment further proposes a method for using the low offset hall device with a double protection ring, where the method includes:

in the proposed bias electrode A, B, C, D of the hall device, two opposite bias electrodes input equal-sized and opposite-direction current or voltage bias signals, and the other two opposite bias electrodes are grounded, for example, bias electrodes B and D are grounded when equal-sized and opposite-direction current or voltage bias signals are input in bias electrodes a and C; the Hall current or Hall voltage signal is output between two shorted output electrodes E (or H) and F (or G) of the Hall device; the first contact electrode J is connected with a high level; the proposed second contact electrode K is grounded.

Further, the substrate material of the proposed hall device is not limited to silicon (Si) semiconductor, but various semiconductor materials such as silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), and indium gallium arsenide (InGaAs) may be used as the substrate.

Further, the N-well active region 104 of the proposed hall device may also be designed in octagon, diamond and circular structures.

The process steps for manufacturing the low-offset Hall device structure provided by the invention are as follows:

in step S1, an n+ buried layer 102 is first formed in a central region on a P-type substrate 101.

In step S2, a P-type epitaxial layer 201 is grown on the P-type substrate 101, and an isolation shallow trench 300 is formed on top of the P-type epitaxial layer 201.

And S3, forming a P-buried layer 103 in the epitaxial layer above the N+ buried layer 102, wherein the bottom of the P-buried layer 103 is connected with the top of the N+ buried layer 102.

In step S4, the N-well active region 104 is implanted into the P-type epitaxial layer 201 on the P-buried layer 103.

In step S5, a high-voltage N-well 202 is formed in the P-type epitaxial layer 201 around the N-well active region 104, and the bottom of the high-voltage N-well is connected to the top of the n+ buried layer 102.

In step S6, a high voltage P-well 203 is formed in the P-type epitaxial layer 201 around the high voltage N-well 202, and the bottom of the high voltage P-well 203 is connected to the P-type substrate 101.

In step S7, a first n+ region 104a and a second n+ region 104b are formed on top of the N-well active region 104, and a third n+ region 104c is formed on the surface of the high voltage N-well 202.

In step S8, a first p+ region 104d is formed on the surface of the N-well active region 104, and a second p+ region 203a is formed on the surface of the high-voltage P-well 203.

In step S9, a contact hole is formed in the P-type epitaxial layer 201 to form a metal interconnection line.

The proposed method of operating a hall device is further described with reference to the low offset hall device operating bias schematic of fig. 5:

when the hall bias electrodes A, C are biased by equal and opposite currents, and the other two bias electrodes B, D are connected to the ground and no external magnetic field is applied, the current density is the same near the four output electrodes E, F, G, H, and the output voltage is ideally 0, assuming that the overall concentration distribution of the N-well active region 104 is uniform.

Further, when a magnetic field is applied to the surface of the paper inwards, carriers are deflected by lorentz force, and simultaneously the four output electrodes are polarized, and under the actual condition, the impurity of the active region of the Hall device is unevenly distributed, so that the current density near the four output electrodes is asymmetric.

Further, the diagonal output electrodes E, H, F and G of the Hall device are short-circuited, so that current is forced to be uniformly distributed in the active region, offset caused by uneven resistivity, impurity concentration or uneven process stress is reduced, static offset signal elimination is realized, a current rotating technology is not needed, and parasitic capacitance of a front-end circuit is reduced.

Further, as the first contact electrode J is always connected with the high level and the second contact electrode K is always grounded, the transverse protection ring and the longitudinal protection ring can be reversely biased, leakage current and high-frequency signal interference in a circuit during working are reduced, and the anti-interference capability of the Hall device is enhanced.

Referring to fig. 6, a diagram is shown which is a comparative simulation of the output offset of the present invention and a conventional cross-shaped hall device structure.

Specifically, for the device structure shown in fig. 1 and fig. 2, according to the technological process parameters of the high-voltage BCD process, the electrical characteristics of the low-offset hall device structure are simulated by using a Silvaco TCAD simulation tool, so that the comparison of the output offset of the low-offset hall device shown in fig. 5 and the output offset of the hall device with the traditional four contact holes is obtained, the output offset of the low-offset hall device is always below 1mV under the bias current of 0-5mA, and the output offset of the traditional cross hall device reaches about 4.5mV under the bias current of 5mA, which indicates that the scheme of the low-offset hall device designed by the invention has feasibility.

It is important to note that the construction and arrangement of the present application as shown in a variety of different exemplary embodiments is illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present invention. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present inventions. Therefore, the invention is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.

Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the invention, or those not associated with practicing the invention).

It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims

1. A low offset hall device employing a double guard ring, characterized by: comprising the steps of (a) a step of,

the device comprises a transverse layer group (100), wherein the transverse layer group (100) comprises a P-type substrate (101), an N+ buried layer (102) arranged in the central area of the P-type substrate (101) and a P-buried layer (103) arranged in the central area of the top of the N+ buried layer (102), an N well active region (104) is arranged above the P-buried layer (103), and the N+ buried layer (102) and the P-buried layer (103) form a transverse protection ring;

the side wall layer group (200), side wall layer group (200) is including setting up in P type epitaxial layer (201) in the N well active region (104) outside, be provided with in P type epitaxial layer (201) with N+ buried layer (102) top be connected high-pressure N well (202), be provided with in P type epitaxial layer (201) with P type substrate (101) top be connected high-pressure P well (203), high-pressure P well (203) set up in high-pressure N well (202) outside, P type epitaxial layer (201) and high-pressure N well (202) form vertical guard ring.

2. The low offset hall device employing a double guard ring as claimed in claim 1, wherein: the side wall layer group (200) is of a symmetrical structure and is symmetrical about a first symmetry axis (Y1); the N-well active region (104) is of a symmetrical structure and symmetrical about a second symmetry axis (Y2), and the first symmetry axis (Y1) and the second symmetry axis (Y2) are overlapped.

3. The low offset hall device employing a double guard ring as claimed in claim 1 or 2, wherein: the edges of the N well active region (104) are uniformly distributed with first N+ regions (104 a), the first N+ regions (104 a) are symmetrical about a second symmetry axis (Y2), and the first N+ regions (104 a) are placed parallel to the edges of the N well active region (104).

4. The low offset hall device employing a double guard ring as claimed in claim 3, wherein: metal is disposed on each of the four first n+ regions (104 a) to form four bias electrodes A, B, C and D.

5. The low offset hall device employing a double guard ring as claimed in claim 4, wherein: a second N+ region (104 b) is arranged in the N well active region (104) at the center of the adjacent first N+ region (104 a), the second N+ region (104 b) is symmetrical about a second symmetry axis (Y2), and the second N+ region (104 b) is arranged parallel to the edge of the N well active region (104);

the first N+ region (104 a) is larger in size than the second N+ region (104 b).

6. The low offset hall device employing a double guard ring as claimed in claim 5, wherein: the four second N+ regions (104 b) are provided with metal, so that four output electrodes E, F, G and H are formed;

the two output electrodes E and H and F and G on opposite angles are short-circuited by metal wires.

7. The low offset hall device employing a double guard ring according to any one of claims 4 to 6, wherein: the surface of the high-voltage N well (202) is provided with a third N+ region (104 c), and the third N+ region (104 c) is provided with metal to form a first contact electrode J.

8. The low offset hall device employing a double guard ring as claimed in claim 7, wherein: a non-electrode part above the N well active region (104) is covered with a first P+ region (104 d);

the surface of the high-voltage P well (203) is provided with a second P+ region (203 a), and the second P+ region (203 a) is provided with metal to form a second contact electrode K.

9. The low offset hall device employing a double guard ring as claimed in claim 8, wherein: an isolation shallow trench (300) is arranged between the first N+ region (104 a) and the third N+ region (104 c), and between the first N+ region (104 a) and the first P+ region (104 d), and between the third N+ region (104 c) and the second P+ region (203 a).

10. A method of using a low offset hall device employing a double guard ring as claimed in any one of claims 1 to 9:

inputting current or voltage bias signals with equal magnitudes and opposite directions to two opposite bias electrodes A and C;

the other two opposite bias electrodes B and D are grounded;

a Hall current or Hall voltage signal is output between the output electrodes E and F;

the first contact electrode J is connected with a high level; the second contact electrode K is grounded.