JPS596065B2 - Hand tie souchi - Google Patents
Hand tie souchiInfo
- Publication number
- JPS596065B2 JPS596065B2 JP50072008A JP7200875A JPS596065B2 JP S596065 B2 JPS596065 B2 JP S596065B2 JP 50072008 A JP50072008 A JP 50072008A JP 7200875 A JP7200875 A JP 7200875A JP S596065 B2 JPS596065 B2 JP S596065B2
- Authority
- JP
- Japan
- Prior art keywords
- well
- region
- field effect
- mis
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 11
- 230000000295 complement effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置に関し、特に相補型の金属一絶縁
膜一半導体構造（以下Ｃ−ＭＩＳと略記する）を有する
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a complementary metal-insulating film-semiconductor structure (hereinafter abbreviated as C-MIS).
インバータとして、ＰチャンネルとＮチャンネルのエン
ハンスメント型ＭＩＳ電界効果トランジスタを組合せた
Ｃ−ＭＩＳ構造が使われる。このＣ−ＭＩＳを使用した
インバータは、一般的に第１図のような構造を有してい
る。すなわち、Ｎ−型のシリコン（Ｓｉ）半導体基板１
上にＰ型のドレイン領域２とソース領域３を設けるとと
もに、薄い酸化膜４をドレイン領域２とソース領域３間
のシリコン（Ｓｉ）半導体基板１上に設け、その上にゲ
ート電極５を設けてＰチャンネル型のＭＩＳトランジス
タを構成し、一方前記シリコン（Ｓｉ）半導体基板１に
設けたＰ−−ウェル６には、Ｎ＋型のドレイン領域７と
ソース領域８とを設けるとともにこれら領域Ｔ、８に挾
まれたシリコン（Ｓｉ）半導体基板１上に薄い酸化膜９
を介してゲート電極１０を設けてＮチャンネル型のＭＩ
Ｓトランジスタを構成し、互いのゲート電極５、１０を
接続線１１で接続して入力端子Ｖｉｎとし、互いのドレ
イン領域２と７とを接続線１２で接続して出力端子ｖｏ
ｕｔとするとともに、ソース領域３をプラス電源＋ＶＤ
Ｄに接続し、ソース領域３をマイナス電源−Ｖｓｓに接
続する。そしてＮ−のシリコン半導体基板１をプラスの
電源＋ＶＤＤに接続するとともに、Ｐ−−ウェル６をマ
イナス電源−Ｖｓｓに接続する。このように構成された
Ｃ−ＭＩＳのインバータ回路において、出力端子ｖｏｕ
ｔに接続されたインターフェース回路の種類によつては
、出力側の波形に第２図のようなオーバーシュート部分
１３とアンダーシュート部分１４とが現われることがあ
る。A C-MIS structure in which P-channel and N-channel enhancement type MIS field effect transistors are combined is used as an inverter. An inverter using this C-MIS generally has a structure as shown in FIG. That is, an N-type silicon (Si) semiconductor substrate 1
A P-type drain region 2 and a source region 3 are provided thereon, a thin oxide film 4 is provided on the silicon (Si) semiconductor substrate 1 between the drain region 2 and the source region 3, and a gate electrode 5 is provided thereon. A P-channel type MIS transistor is constructed, and a P- well 6 provided in the silicon (Si) semiconductor substrate 1 is provided with an N+ type drain region 7 and a source region 8, and these regions T and 8 are provided with an N+ type drain region 7 and a source region 8. A thin oxide film 9 is formed on the sandwiched silicon (Si) semiconductor substrate 1.
A gate electrode 10 is provided through the N-channel MI
An S transistor is configured, and the gate electrodes 5 and 10 are connected by a connecting line 11 to form an input terminal Vin, and the drain regions 2 and 7 are connected by a connecting line 12 to form an output terminal vo.
ut, and the source region 3 is connected to the positive power supply +VD.
D, and the source region 3 is connected to the negative power supply -Vss. Then, the N- silicon semiconductor substrate 1 is connected to the positive power supply +VDD, and the P- well 6 is connected to the negative power supply -Vss. In the C-MIS inverter circuit configured in this way, the output terminal vou
Depending on the type of interface circuit connected to t, an overshoot portion 13 and an undershoot portion 14 as shown in FIG. 2 may appear in the output waveform.
オーバーシュートについてはさして問題が起らないが、
アンダーシュートが大きくなつて、その値がｐ−ウェル
６内のＮ＋領域、すなわちドレイン領域７とＰ−ウエル
６により構成されているＰＮ接合ダイオードの順方向立
上り電圧分より大きくなつた場合には、ドレイン領域７
からＰ−ウエル６内に小数キヤリアが注入されることに
なり、ドレイン領域７、Ｐ−ウエル６、Ｎ一型のシリコ
ン半導体基板１、ソース領域３により構成するＮＰＮＰ
構造がオンとなり、プラス電源＋ＶＤＤから出力端子Ｖ
Ｏｕｔに向つて大きな電流が流れ、Ｃ−ＭＩＳを破壊す
ることがある。本発明は上述の如き従米の欠点を改善し
た新規な発明であり、その目的は、出力端子の電位がＰ
−ーウエルの電位より低下してもＣ−ＭＩＳ中のサイリ
スタ構造部分がオンとならないようなＣＭＩＳ構造を得
ることにある。There is not much problem with overshoot, but
When the undershoot becomes large and its value becomes larger than the forward rising voltage of the N+ region in the p-well 6, that is, the PN junction diode constituted by the drain region 7 and the p-well 6, drain region 7
Therefore, fractional carriers are injected into the P-well 6, and the NPNP formed by the drain region 7, the P-well 6, the N-type silicon semiconductor substrate 1, and the source region 3 is injected into the P-well 6.
The structure is turned on, and the output terminal V from the positive power supply +VDD
A large current flows toward Out, which may destroy the C-MIS. The present invention is a novel invention that improves the above-mentioned drawbacks of conventional methods, and its purpose is to reduce the potential of the output terminal to P.
- To obtain a CMIS structure in which the thyristor structure part in the C-MIS does not turn on even if the potential drops below the well potential.
本発明は、Ｃ−ＭＩＳ電界効果トランジスタによつて構
成されたインバータにおいて、Ｎチヤンネル型ＭＩＳ電
界効果トランジスタが形成されているＰ−ウエルに隣接
してＰ−ウエルを形成し、このｐ−ウエルにＮ＋型領域
の抵抗領域を形成し、この抵抗領域をＣ−ＭＩＳ電界効
果トランジスタの出力側の抵抗としたものであり、以下
実施例について詳細に説明する。The present invention provides an inverter configured with C-MIS field effect transistors, in which a P-well is formed adjacent to a P-well in which an N-channel MIS field effect transistor is formed; An N+ type resistance region is formed, and this resistance region is used as a resistance on the output side of a C-MIS field effect transistor.Examples will be described in detail below.
第３図は本発明の一実施例の側断面図であり、第１図示
の従来装置と同一部分には同一の引出線番号を付し、そ
の詳細な説明は省略する。FIG. 3 is a side sectional view of one embodiment of the present invention, and the same parts as those of the conventional device shown in FIG.
さて第３図において、Ｎチヤンネル型のＭＩＳトランジ
スタが形成されているＰウエル６に隣接した部分に別の
ｐ−ーウエル２１を形成し、その中にＮ＋型領域からな
る抵抗領域２２を形成する。２３は二酸化シリコン（Ｓ
ｉＯ２）からなる絶縁膜で、これに窓をあけ、アルミニ
ウム配線２４を行なつて、Ｎチャンネル型のＭＩＳトラ
ンジスタのドレイン領域７と抵抗素子２２の一端を接続
するとともに、抵抗素子２２の他端にアルミニウムより
なる配線２５を形成して出力端子ＶＯｕｔとする。Now, in FIG. 3, another p-well 21 is formed in a portion adjacent to the p-well 6 in which the N-channel type MIS transistor is formed, and a resistance region 22 made of an N+ type region is formed therein. 23 is silicon dioxide (S
A window is opened in the insulating film made of iO2), and an aluminum wiring 24 is formed to connect the drain region 7 of the N-channel type MIS transistor to one end of the resistance element 22, and to connect the other end of the resistance element 22. A wiring 25 made of aluminum is formed to serve as an output terminal VOut.
なお、２６はチャンネルストツパ一領域である。このよ
うに、Ｎチヤンネル型のＭＯＳトランジスタのドレイン
回路に抵抗を挿入した場合、Ｎ＋型ドレイン領域７、Ｐ
−ーウエル６、Ｎ一型のシリコン（Ｓｉ）半導体基板１
、ｐ＋型ソース領域３からなるＮＰＮＰ構造のサイリス
タ部分は、等価的に第４図のような回路構成となつて丁
度ＮＰＮトランジスタＴｒｌにエミツタホロワ抵抗Ｒ２
２を挿入したことになる。したがつて、出力端子ＶＯｕ
ｔにアンダーシユートが現われてもトランジスタＴｒｌ
はオンせず、サイリスタ部分がオン状態となるのを防止
する。なお、抵抗素子２２の抵抗値としては、大きいも
のほど寄生サイリスタ効果の防止には役立つが、ＭＩＳ
トランジスタの出力イジピーダンスと比較してあまり大
きくなると、Ｃ一ＭＩＳのスイツチングスピードが低下
するので良くない。一例として出力インピーダンスが２
００〜３００〔Ω〕程度の場合、抵抗値として１０〔Ω
〕程度を選べばスイツチングスピードにほとんど影響を
与えずしかも寄生サイリスタ効果の防止に役立つ。今Ｎ
チヤンネル型のＭＩＳトランジスタのソース、ドレイン
拡散の表面抵抗を５〔Ω／口］とすれば、抵抗体のデイ
メンシヨンＬ／Ｗは２となる。Ｐチャンネル型のＭＩＳ
型トランジスタのソース、ドレイン拡散（表面抵抗〜１
５０〔Ω／口〕）領域では抵抗が大きくなりすぎて良く
ないので、上述のようにＰ−ーウエル２１を別に作り、
その中のＮ＋層を利用する。ところで、抵抗素子２２を
形成Ｐ−ーウエルをマイナス−Ｖｓｓと同電位にしてし
まうと、この抵抗素子そのものがまた寄生サイリスタ素
子の一部となつて都合が悪いので、このＰ−ーウエル２
１は抵抗素子２２と同電位にする。すなわち第３図に示
すようにＰ−ーウエル２１と抵抗素子２２の電極窓を共
通のものとし、電極２４，２５をＰ−ウエル上抵抗素子
２２の領域に共通に接触させるようにする。このように
すれば、寄生サイリスタ素子とはならず、またＮ一型の
シリコン（Ｓｉ）半導体基板１は＋ＶＤＤ電位であるの
で、ＰＮ接合の逆バイアスがかかり、アイソレートされ
る。またこの構造は出力電圧も＋ＤＤ＋ＶＦ（Ｐ−ウエ
ル２１と半導体基板１のＰＮ接合の順方向立上り電圧）
以上にはならないようにクランプしていることにもかな
り都合がよい。以上説明したように、本発明は、Ｃ−Ｍ
ＩＳ電界効果トランジスタの出力側に抵抗素子を接続し
たことにより、寄生サイリスタ効果を防止することがで
き、又ｐ−ウエル２１内のＮ＋型領域の抵抗領域２２を
形成し、ＮチャンネルＭＩＳ電界効果トランジスタのド
レイン領域７に一端を接続した電極２４の他端をＰ−ウ
エル２１と抵抗領域２２との一端に共通に接続し、それ
らの他端に共通に出力用電極２５を接続したことにより
、Ｐウエル２１と抵抗領域２２とを同一の電位とするこ
とができ、且つ半導体基板１に対してＰＮ接合の逆バイ
アスがかかることになるので、半導体基板１とは分離さ
れた構成となる。Note that 26 is a channel stopper area. In this way, when a resistor is inserted into the drain circuit of an N-channel type MOS transistor, the N+ type drain region 7, P
--Well 6, N-type silicon (Si) semiconductor substrate 1
, the NPNP structure thyristor portion consisting of the p+ type source region 3 has an equivalent circuit configuration as shown in FIG.
This means that 2 has been inserted. Therefore, the output terminal VOut
Even if undershoot appears at t, the transistor Trl
does not turn on, preventing the thyristor portion from turning on. It should be noted that the larger the resistance value of the resistance element 22, the more useful it is for preventing the parasitic thyristor effect.
If it becomes too large compared to the output idipedance of the transistor, the switching speed of the C-MIS will decrease, which is not good. As an example, the output impedance is 2
00 to 300 [Ω], the resistance value is 10 [Ω].
] If the degree is selected, it will hardly affect the switching speed and will help prevent the parasitic thyristor effect. Now N
If the surface resistance of the source and drain diffusions of a channel type MIS transistor is 5 [Ω/gate], the dimension L/W of the resistor is 2. P channel type MIS
type transistor source and drain diffusion (surface resistance ~1
Since the resistance becomes too large in the 50 [Ω/mouth] region, which is not good, a separate P-well 21 is made as described above.
The N+ layer is used. By the way, if the P-well where the resistive element 22 is formed is made to have the same potential as -Vss, this resistive element itself becomes part of the parasitic thyristor element, which is inconvenient.
1 is set to the same potential as the resistance element 22. That is, as shown in FIG. 3, the electrode windows of the P-well 21 and the resistive element 22 are made common, and the electrodes 24 and 25 are brought into common contact with the region of the resistive element 22 on the P-well. In this way, it does not become a parasitic thyristor element, and since the N1 type silicon (Si) semiconductor substrate 1 is at +VDD potential, the PN junction is reverse biased and isolated. In addition, this structure also has an output voltage of +DD+VF (forward rising voltage of the PN junction between the P-well 21 and the semiconductor substrate 1).
It is also quite convenient to clamp it so that it does not become more than that. As explained above, the present invention provides C-M
By connecting a resistance element to the output side of the IS field effect transistor, a parasitic thyristor effect can be prevented, and a resistance region 22 of the N+ type region within the p-well 21 is formed, thereby forming an N channel MIS field effect transistor. By connecting the other end of the electrode 24, one end of which is connected to the drain region 7 of the P-well 21 and the resistance region 22, and the output electrode 25 commonly connected to the other ends of the P-well 21 and the resistance region 22, Since the well 21 and the resistance region 22 can be set at the same potential and a reverse bias of the PN junction is applied to the semiconductor substrate 1, the structure is separated from the semiconductor substrate 1.
【図面の簡単な説明】
第１図は従来のＣ−ＭＩＳ構造の縦断面図、第２図はイ
ンバータの出力波形、第３図は本発明に係る一実施例の
縦断面図、第４図は寄生サイリスタ部分の回路図である
。
図において、１はシリコン半導体基板、２，７はドレイ
ン領域、３，８はソース領域、６，２１はＰ−ーウエル
、５，１０はゲート電極、２２は抵抗素子を示す。[Brief Description of the Drawings] Fig. 1 is a longitudinal cross-sectional view of a conventional C-MIS structure, Fig. 2 is an inverter output waveform, Fig. 3 is a longitudinal cross-sectional view of an embodiment according to the present invention, and Fig. 4 is a circuit diagram of a parasitic thyristor portion. In the figure, 1 is a silicon semiconductor substrate, 2 and 7 are drain regions, 3 and 8 are source regions, 6 and 21 are P-wells, 5 and 10 are gate electrodes, and 22 is a resistance element.
Claims (1)
ャンネル型ＭＩＳ電界効果トランジスタとを組合せた相
補形ＭＩＳ電界効果トランジスタによつて構成されるイ
ンバータにおいて、前記Ｎチャンネル型ＭＩＳ電界効果
トランジスタが形成されているＰ−ウェル６に隣接した
半導体基板の部分に、その内部にＮ＾＋型領域からなる
抵抗領域２２が形成されたＰ＾−ウェル２１を形成し、
前記Ｎチャンネル型ＭＩＳ電界効果トランジスタのドレ
イン領域７に一端を接続した電極２４の他端を前記抵抗
領域２２の一端と前記Ｐ＾−ウェル２１の一端とに共通
に接続し、該抵抗領域２２の他端と該Ｐ＾−ウェル２１
の他端とに共通に出力用電極２５を接続したことを特徴
とする半導体装置。1. In an inverter configured with complementary MIS field effect transistors that are a combination of a P-channel MIS field effect transistor and an N-channel MIS field effect transistor, the P-channel in which the N-channel MIS field effect transistor is formed A P^-well 21 is formed in a portion of the semiconductor substrate adjacent to the well 6, in which a resistance region 22 consisting of an N^+ type region is formed;
The other end of the electrode 24, one end of which is connected to the drain region 7 of the N-channel MIS field effect transistor, is commonly connected to one end of the resistance region 22 and one end of the P^-well 21. The other end and the P^-well 21
A semiconductor device characterized in that an output electrode 25 is commonly connected to the other end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50072008A JPS596065B2 (en) | 1975-06-16 | 1975-06-16 | Hand tie souchi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50072008A JPS596065B2 (en) | 1975-06-16 | 1975-06-16 | Hand tie souchi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS51148387A JPS51148387A (en) | 1976-12-20 |
| JPS596065B2 true JPS596065B2 (en) | 1984-02-08 |
Family
ID=13476944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50072008A Expired JPS596065B2 (en) | 1975-06-16 | 1975-06-16 | Hand tie souchi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596065B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5823949B2 (en) * | 1975-07-18 | 1983-05-18 | 株式会社東芝 | Semiconductor integrated circuit device |
| JPS60154554A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Complementary type insulated gate field effect semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191681A (en) * | 1975-01-22 | 1976-08-11 |
-
1975
- 1975-06-16 JP JP50072008A patent/JPS596065B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191681A (en) * | 1975-01-22 | 1976-08-11 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51148387A (en) | 1976-12-20 |
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