JPS59103425A - Switching device - Google Patents

Abstract

PURPOSE:To increase the input impedance and the conductance of a switch and to reduce the delay in switch-off by combining an MOSFET, a JFET and a bipolar transistor(TR). CONSTITUTION:When a voltage is applied to gate 4, since a channel is formed on the surface of P diffusion layer via a silicon oxide film 12, a current flows to a source 6. Thus, the MOSFET and the bipolar TR are both turned on. Since a positive voltage is applied to an n-channel diffusion layer 19, the JFET is brought into pinch-off state. Since the collector and base of the bipolar TR are short-circuited by the MOSFET, the entire on-resistance is made small. Since the JFET is turned on when the bipolar TR is turned off from on, the stored charge in the bipolar TR is relinquished and high speed switching is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improved semiconductor switching devices and circuits thereof.

[Prior art]

As is well known, semiconductor switching devices are essential elements in logic circuits, and are also used as elements for controlling the current of various electrical loads. Bipolar transistors and junction field effect transistors (hereinafter referred to as JP) are used as semiconductor switching elements.
(abbreviated as ET), Metal Oxide Semiconductor P
ET (hereinafter abbreviated as MO8) etc. are used.

These elements are incorporated into the circuit as appropriate according to their characteristics,
However, for example in logic circuits, it is desirable to operate with very low power and a very small delay time.
In addition, in power switching applications, it is required to handle larger currents and voltages with lower power losses. In response to these demands, the above-mentioned conventional elements have the following problems.

In order to perform switch operation in a bipolar transistor, is there a signal current at the base pole? The change in collector current is applied as an output. n-p-n.

Alternatively, it is a p-n-p target structure, in which minority carriers injected into the base layer from the emitter diffuse throughout the narrow space layer and flow into the highly reverse biased collector and base junctions, thereby turning from the cut-off state. Turn on. In the state after turn-on, current flows in the base layer due to the bipolar carriers of minority carriers (holes for n-type, electrons for pm) and majority carriers for recombining and annihilating them.

For this reason, although it has the advantage of being able to be in a high conductance state, it is necessary to continue supplying charge to the pace electrode during the turn-on period, which is lost due to recombination. In other words, it is a current input type and consumes a lot of power. Particularly when used as a power switching element, there is a drawback that reactive power increases. This operating principle also presents problems in increasing speed.

When a transistor is cut off, the time required for the injected charges supplied so far to recombine and disappear even if the base current is cut off becomes the turn-off delay time of the element.

This time depends on the amount of current passed through the base during turn-on. That is, even if the amount of charge is increased by flowing a base current beyond the amount required to recombine and annihilate minority carriers in the base, the amount of carriers in the base will be saturated and the conductance will no longer increase. In other words, it becomes saturated.

Therefore, the supplied excess charge must be removed at turn-off, which greatly impairs the switching speed.

Disadvantages of these bipolar transistors? Several attempts have been made and are in use. A structure in which bipolar transistors are connected in two stages, called a Darlington connection, is widely known and solves the above-mentioned problems, especially in power switches. By connecting all the collectors and emitters between the collectors and bases of the transistors in the output stage with the collectors in common, the current amplification effect of the transistors t1 can be taken as the product of those of each transistor, and the result can be dramatically increased. It is particularly effective for power applications that handle large currents. This configuration is also effective in increasing the speed of switching. This is because the transistor in the output stage is turned on with its collector and base shorted by the transistor in the previous stage, so it is impossible for injected carriers to saturate the base layer and forward bias the base-collector junction. , therefore, at turn-off, no excess charge is generated that must be dissipated, allowing for fast turn-off.
Can be turned off. However, the transistor on the input side may operate in saturation, and the input impedance remains low.There are other ways to prevent bipolar transistor saturation.
The idea is to connect a semiconductor-metal rectifier diode between the base and collector with the same direction of rectification polarity. Since the forward voltage drop of a semiconductor-to-metal rectifier diode is very small compared to that between the base and collector, the base-collector junction is only slightly forward biased. Therefore, accumulation of the above-mentioned excess carriers is small, and high-speed switching operation is possible. However, the problem of low input impedance cannot be solved.

Furthermore, the MO8 field effect transistor has a high input impedance, and since it is a majority carrier element, there is no injection of minority carriers, and there is no need for the time required for recombination disappearance as in a bipolar transistor. However, only majority carriers exist in the channel, which serves as a conductive part, and the conductance per unit cross section is lower than that of bipolar. Therefore, for power applications that handle large currents, the element must be large, and as a result, the capacitance on the input (ie, gate) side becomes large. Therefore, a large amount of energy is required to charge and discharge the input capacitance, that is, the input impedance decreases during high-speed operation.

[Purpose of the invention]

The purpose of the present invention is to increase the impedance including the input S ft k, increase the conductance of the switch, and shorten the switch-off delay caused by the accumulated charge between the emitter and the base, which is applied to a bipolar transistor. The object of the present invention is to provide a switching element and a circuit having high speed and high load drive capability.

[Summary of the invention]

In order to achieve all of these objectives, the present invention utilizes a MOSFET.
Depression type FETs such as ET and JPET (
DFET) and bipolar transistors υ, M
The source of O8F'ET and the source of DFE'l' are connected, and the connection point is connected to the base of the bipolar transistor, and the drain of MOSFET and the collector of the bipolar transistor are connected, and DF
The drain of the ET is connected to the emitter of a bipolar transistor, and the conduction and non-conduction of the bipolar transistor are controlled using the gate electrodes of the MO8FET and DFET as a common input electrode.

[Embodiments of the invention]

The present invention will be described in detail below using Examples.

FIG. 1 is a configuration diagram showing one embodiment of a switching element according to the present invention. This switching element is, for example, n
Channel type MO8FBTI, such as p-channel type JPET2. and, for example, an npn type bipolar transistor 3.

The north (S) of MOSFET is the source of JF'ET2 (
8), and its connection point is connected to the bipolar transistor 30 pace (B). Maku, MOSFE
The gate (G) of T1 is the gate of JFB'l'2) (G
)It is connected to the. Furthermore, the drain (D) of MO8FETI is the collector (C) of bipolar transistor 3.
The drain (D) of JFE'l'2 is connected to the emitter (E) of bipolar transistor 3.

The switching element configured in this way is.

The connection point between the gate (G) of MO8FETI and the gate (G) of JP'ET 2 is the gate electrode 4, the collector (C) of the bipolar transistor 3 is the drain electrode 5, and the emitter (E) of the bipolar transistor 3 is the source electrode 6.
used as.

The switching elements are assembled, for example, on the same semiconductor chip as shown in FIG. The n-type semiconductor substrate 7 with high resistance is medium, and this n-type semiconductor substrate 7
An n0 type semiconductor layer 8 is formed on the back surface of the semiconductor layer 8 by diffusing n+ type impurities.

A p-type diffusion layer 9 formed in an annular shape is formed on the main surface of the n-type semiconductor substrate 7, and further, this p-type diffusion layer 9
Inside, an n Jr type scattering layer 10 is formed concentrically with the p type diffusion layer 9. An electrode 11 is formed on a part of the surface of this nI type scattering layer 10, and a silicon oxide film 12 which is an insulating film is formed except for the region of this t-pole 11. On the surface of this silicon oxygen film 12, the p-type diffusion layer 9
An electrode 13 is formed on a region surrounded by the n" type diffusion layer 10.

In this way, a MOSFET 1 is formed in which the electrode 11 is the drain electrode, the electrode 13 is the gate electrode, and the electrode 14 formed on the surface of the n1 type semiconductor layer 8 is the source electrode.

Further, on the main surface of the n-type semiconductor substrate, a pffli diffusion layer 15 is formed in contact with and surrounding the p-type diffusion layer 9, and furthermore, a pffli diffusion layer 15 is formed in the pffi diffusion layer 15 concentrically with the p-type diffusion layer 15. An n3 type diffusion layer 16 is formed in a shape. This n0 type diffusion layer 16 has an electrode 17 on a part of its surface.
is formed, and the electrode 11 is formed extending on a part of the surface of the p-type diffusion layer 9, and a silicon oxide film 12 is formed except for the area of the electrode 17°11. ing.

In this way, the electrode 17 is connected to the emitter 11L pole, and the electrode 11
A bipolar transistor 3 is formed in which the base electrode is the base electrode and the electrode 14 is the collector electrode.

Furthermore, on the main surface of the n-type semiconductor substrate 7, the p
A pm diffusion layer 18 is formed apart from the p-type diffusion layer 15, and an n-type diffusion layer 19 is formed within the p-type diffusion layer 18. In this n-type diffusion layer (10) 19, an n-type diffusion layer 20 is formed.

Electrodes 21 and 22 are formed at both ends of the n-type diffusion layer 20, and electrodes 23 are formed at a portion of the n-type diffusion layer 19. These electrodes 21 to 23
A silicon oxide film 12 is formed except for the region.

In this way, the isolene 3 which is the n-type diffusion layer 18
In the layer, electrodes 21 and 22 are arranged as a drain electrode and a drain electrode, respectively.
JFE with source electrode and electrode 23 as gate t&
'll' 2 is formed.

Note that the switching element composed of a plurality of elements configured in this manner is connected on the chip surface using, for example, vapor-deposited wiring, as shown in FIG. 2, taking into consideration the common connection of each diffusion layer. There is.

Next, the operation of the switching element in this structure will be explained.

In FIG. 2, first, when no voltage is applied to the gate electrode 4, the n j- diffusion layer 10, the n-type diffusion layer 9, and the n-
In the MOSFET (11) formed using the type semiconductor substrate 8, the voltage of the gate electrode 13 provided through the silicon oxide film 12 is zero, and therefore a channel is formed on the surface of the p-type diffusion layer 12. This MO
SFET becomes OFF state.

In addition, a junction FET is formed between the electrodes 21 and 22 in the n-type diffusion layer 20, but since no voltage is applied to the gate electrode 23, a short circuit occurs between the electrodes 21 and 22 in the n-type diffusion layer 20. The junction type PET is in the ON state. Therefore, the voltage applied to the gate electrode 4 is blocked by the n-type semiconductor substrate 7, the p-type diffusion layer 15, the n-type diffusion layer 9, and the n-type diffusion layer 18, and the switching element becomes OFF'.

When a voltage is applied to the gate electrode 4, in the MOSFET described above, the voltage applied to the gate electrode 13 forms a channel on the surface of the p-type diffusion layer via the silicon oxide film 12, so that the drain electrode 4 , n3 type diffusion layer 16, n- type diffusion layer 15, channel formed in n type diffusion layer 19, n++ diffused layer 10, electrodes 11, 22, p type diffused layer 15, n+ type diffused layer 16 source electrode 6 current paths (12) are formed. As a result, both the MOSFET and the bipolar transistor turn on. Note that an n-type diffusion layer 9 is formed between the base and emitter of the bipolar transistor.
By applying a positive voltage to the JPET n-type diffusion layer 19, the path that was short-circuited at A depletion layer develops and is formed in a shallow layer near the surface.
! A portion of the diffusion layer 200 enters the depletion layer region, resulting in a so-called pinch-off. Therefore, this route JPET is OF
In this state, the collector and base of the bipolar transistor are short-circuited by the on-resistance between the drain and source of the MOSFET, and the overall on-resistance is lower than that of the so-called Darlington connection where the bipolar transistor is the first stage. Can be made smaller. The reason for this is that in the Darlington connection, none of the transistors can be saturated, that is, the base-collector and base-emitter cannot become forward biased, whereas in the switching element shown in the example, the MOSFET exhibits resistance characteristics. And (
13) Ru.

The effect of JPET is that when the switching element shown in the example shifts from the on state to the off state, the charges accumulated between the base and emitter of the bipolar transistor (p! diffusion layer 15 - n" type diffusion layer 16) are short-circuited, As a result of annihilating
The accumulation time associated with the same accumulated charge is shortened, and high-speed switching becomes possible.

It can be seen that the characteristics of the switching element thus constructed are improved as compared to conventional bipolar transistors, etc., as shown in Table 1.

(14) (15) Note that the current characteristics with respect to the saturation voltage of the switching elements according to the embodiments are shown for bipolar transistors, Darlington-connected transistors, and JFETs.

When compared with MOSFET, it was found that the graph in Figure 3 shows the results. In the figure, straight line A is a bipolar transistor, curve B is a Darlington-connected bipolar transistor, and straight line C is a junction type PET and MO8FET.
% straight line is the switching element according to this example.

FIG. 4 is a diagram showing operating waveforms of the switching element according to this embodiment. In the figure, (a) is the input drive voltage, (
b) is the pace current waveform of the bipolar transistor stage, (
C) shows the collector voltage waveform. As shown in FIG. 5, the operating waveforms of the switching element of the present embodiment shown in the operating waveforms show the following advantages compared to an equivalent bipolar transistor.

(1) Since the current in the base flows in proportion to the on-voltage in the collector, the spread of the base current becomes a pace current waveform that automatically corrects the short-time effect. (16) Voltage immediately after turning on becomes smaller.

(2) Since the current to the pace section is kept to the minimum necessary and the current drawing effect when off is large, the storage time can be shortened by nearly an order of magnitude.

(3) Since the input capacitance is small and the Miller effect is small, the on/off change is fast.

(4) Since the current to the base portion is small and all the current is supplied from the collector portion, the drive efficiency of the switch is high.

FIG. 6 shows a second embodiment of the invention. The difference from FIG. 1 is that a p-channel depression type MO8FET 24 is used instead of the p-channel JPET 2.

In a depletion type MOi9FET, the drain/source is conductive even when there is no bias voltage at the gate, and in the case of a p-channel, cutoff occurs when the gate potential is made much more positive than the source potential. becomes.

Structurally, a thin p-layer is formed directly under the gate where the channel is formed, and when a voltage is to be applied to the gate, the drain and source are connected by a p-type resistance layer (17). When a positive voltage is applied to the source, holes in the channel are repelled and withdrawn from the channel layer, causing the channel to lose its conductivity. Therefore, the operation is similar to the above-mentioned JPET.

FIG. 7 shows an example of an element structure for realizing the second embodiment.

The difference from FIG. 2 is that the p-channel depletion MO8 is integrated with the space layer 15 of the bipolar transistor.
FET section, whose gate electrode 25 is above the channel,
A drain pole 26 is adjacent thereto. When a voltage is applied to the gate electrode 4, the gate electrode 25 is also at the same potential, and the channel disappears due to the above-mentioned effect, and the p-channel MO8FET is turned off.

When the gate voltage is removed, the channel becomes condnct
ive, and the BE of the bipolar transistor 3 is short-circuited across the same channel.

In the element structure of FIG. 2 or FIG. 7, the structure of the bipolar transistor is vertical n + -p -n -
n'', it has a high collector-to-pace breakdown voltage and consumes a large emitter current, making it suitable as a power switch element.(18) However, in order to form a high-speed logic circuit, the first step is to It is necessary to use a combination of a plurality of the configurations shown in FIG. 6 or FIG. 6, and it is not preferable to share a collector layer.

FIG. 8 shows an independent bipolar, complementary MOS switching element structure that is a component of a logic circuit. The operation is similar to that shown in FIG. 7, but the structure is separated from adjacent elements by the p+ layer 27, which meets the above-mentioned purpose. The collector pole of the bipolar transistor is connected to the n layer via the n+ layer 28. collector's n
The first layer 8 is formed on the p-substrate 29 and is buried between it and the n-layer epitaxially grown thereon. This layer serves to increase the lateral conductivity of the collector current. Furthermore, by forming the 01 layer 8 deeply and connecting it to the n9 layer 8, it is possible to handle even larger currents.

The embodiment shown in FIG. 9 is an example in which the switching element of the present invention is used in a logic circuit. Even in the embodiment shown in FIG. 9 (19), the same reference numerals as in the circuit shown in FIG. The circuit shown in FIG. 9 differs from the already explained circuit shown in FIG. 6 in that the NPN transistor 3 is of the so-called Schottky clamp type 3' using a semiconductor metal rectifier diode for the switching circuit. N-channel enhance 77 between power supply Vcc and transistor 3 pace
Addition of 30 1MOS transistors. This is achieved by providing a pull-up circuit (simply a resistor) 31 that provides a high logic level. The gates of each FET are commonly connected to input terminal 4.

The operation in FIG. 9 is such that when a high level signal of 10 is applied to the input terminal 4, the transistor 24 is turned off and the transistor 1 is turned off.
, 30 are turned on, and therefore transistor 3' is turned on.

In this case, assuming that the load of the transistor 3 is the ']'TL circuit 9 and the load capacity ΔC, the transistor 1
A large pace current flows through the transistor 3'1
J171- is turned on, and for a steady input current Is of T'l''L (20), a pace current is supplied by the transistor 30, and the Schottky clamp of the transistor 3' causes the transistor 3' to go to the low logic level. Correspondingly, it is kept at a shallow saturation level.Next, when input terminal 4 becomes low level,
Since transistors 1 and 3° are off and transistor 24 is on, transistor 3' is off and the output becomes high level.

The transistor 7 may have a small element structure because the transistor 3' sinks the load current in a steady state and maintains a shallow saturated state.

The switching element shown in FIG. 9 can realize a high-speed logic circuit with low power consumption by reducing the number of coupling stages and functionally sharing the operation of transistors.

The characteristic of low input capacitance, which is one of the characteristics of the switching element shown in this example, is that the input drive power during high frequency drive can be significantly reduced.
8) It enables direct drive by a logic circuit, and is suitable for wide use in high-frequency switching stabilized power supplies.1) It enables cost reduction and improved reliability of power supply circuits.

FIG. 10 is a circuit diagram showing an embodiment of an input/output isolated type high frequency switching DC stabilized power supply using the switching element according to this embodiment. A primary winding of a high frequency transformer 41 and a switching element 42 are connected in series between a DC input power source 40 obtained by rectifying and smoothing ACloov. The secondary winding of the transformer 41 is connected to an output terminal 45 via a rectifying and smoothing circuit 43 consisting of a rectifying diode, an air-core reactor, and a film capacitor. On the other hand, output terminal 4
5 is connected to the input diode of a semiconductor photocoupler 47 via an error amplification circuit 46 consisting of an output voltage detection bridge and a differential amplifier, and the output side is a control input of a PWM (pulse width modulation) circuit 48 consisting of a 0MO8 timer. The output side thereof is connected to the gate electrode of the switching element 42. An auxiliary power supply circuit 49 consisting of a voltage dividing circuit of a resistor, a Zener diode, and a capacitor is connected to the power supply terminal of the PWM circuit 48 from the power supply 40 (22
) ing.

The PWM1 path 48 consisting of 0MO8 is used, for example, in astable multivibrator mode. P
The output pulse width of the WM circuit 48 is set to such a pulse width that the power supply takes on the maximum allowable output when the output from the photocoupler is 0. In other words, the polarity is such that the pulse width is narrowed in inverse proportion to the output of the photocoupler.

The operation in such a configuration is as follows.

First, when the voltage of the input power supply 40 is applied to the power supply circuit, the voltage of the PWM circuit 48 is established via the auxiliary power supply 49't-.
The PWM circuit 48 switches the switching element 42 with the maximum allowable pulse width output. Therefore, output terminal 45
The output voltage of the error amplifier circuit 46 rises rapidly from 0.
reaches the specified output voltage where the bridge output becomes almost 0,
The output voltage is stabilized.

In this way, the isolated power supply has a small drive capacity and can be used with CMO8
Based on the fact that it can be directly driven by a logic circuit, it has the following advantages as a power supply.

(23) (1) The circuit can be simplified and the cost can be reduced.

(2) High frequency operation can be easily achieved and the device can be made compact.

(3) Startup is reliable and control can be coordinated.

(4) The insulation area can be minimized.1. Easily resistant to pressure and surge.

As described above, according to the switching element of the present invention, impedance including input capacitance can be increased, and switch-off delay due to the on-resistance of the switch and accumulated charge between emitters as seen in bipolar transistors can be reduced. In this way, high speed and large capacity can be achieved.

Also, connect other bipolar transistors (%I) or enhancement type MO8FET (
%2) is already known, but in both cases it is necessary to saturate the voltage drop to a voltage drop that is sufficiently smaller than the pace emitter voltage to be shorted, and in bipolar, the speed is increased to supply a much larger pace current. is hindered. In addition, in enhancement type MO8FET, it is necessary to lower the gate voltage to below the threshold, so bipolar (
24) It must be driven to a level below the emitter potential of the transistor, making it unsuitable for logic circuits where the emitter potential functions as a common ground potential.Conversely, when the MO8FET is cut off, the source-drain voltage is It is clamped to the forward voltage drop across the emitter, and the gate is driven in common with the gate of the enhancement type MO8I;'ET, resulting in a state where the gate potential is higher than the source potential (p
In the case of channels), there are problems such as damage to the gate oxide film.

〔Effect of the invention〕

In contrast, in the present invention, since a tippletion type element is used, even if a short-circuit structure is adopted with a relatively large current, a sufficient cut-off state can be created with a large mate voltage amplitude, and the above problems can be solved. It also has the advantage of being able to solve problems.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a switching device, Fig. 2 is a structural diagram of the switching device, Fig. 3 is a current characteristic diagram with respect to saturation voltage, and Fig. 4 (25) is an operation waveform diagram of this embodiment. , Fig. 5 is an operating waveform diagram of the conventional product, Fig. 6 is a circuit diagram of the switching device, Fig. 7 is a structural diagram of the switching device, Fig. 8 is a configuration diagram of the switching device, and Fig. 9 is a diagram of the logic circuit. FIG. 10 is a circuit diagram showing an example of application to a constant current circuit. 1...MOSFET, 2...JFE'r, 3...
・Bipolar transistor, 4...gate, 5...
Drain, 6...source.・;,',,t:i7'l:X7 roc+ 7th mouth 2nd mouth 3rd figure Anko voltage (0 summer shi L top large) 4th country 5th mouth 6th prisoner 7 figure

Claims (1)

[Claims] 1. MOi9F'ET, depression type FE
It consists of T and bipolar transistor, MOSF
The source of the ET and the source of the depletion type PET are connected, the connection point is connected to the base of the bipolar transistor, the drain of the MOSFET is connected to the collector of the bipolar transistor, and the drain of the depletion type FET and the bipolar transistor are connected. The switching device is configured such that the emitter of the bipolar transistor is connected to the emitter of the bipolar transistor, and conduction and non-conduction between the collector and emitter of the bipolar transistor are controlled by a common input to each gate of the MOSFET and depletion type FET. device. 2. The switching device according to claim 1, wherein the MO8PET and depletion type FE'l' have channel and carrier polarities different from each other. 3. The collector layer of the bipolar transistor and the drain/layer of the enhancement type MO8PET are common, and the junction type FET? 2. The switching device according to claim 1, wherein the switching device is formed as a depression type F'ET by being insulated by an isolation layer in a common layer.