KR860000023B1 - Bridge rectifying circuit and it's manufactur methode by use of mosfet in mos i.c. - Google Patents

Abstract

A method for manufacturing a bridge rectifier, consisting of MOS FETs in the MOS IC, comprises: (1) a process for diffusing the P- impurity layers(8) in the diffused P- well(7); (2) a process for diffusing the high-density N impurity layers for a source(9), a drain(10) of the FET and a cathode(11) of the diode; (3) a process for forming an oxide layer(15) for a gate of the FET; and (4) a layer for connecting the electrodes between the FETs and the diodes to form a bridge rectifier.

Description

Manufacturing method of bridge type rectifier circuit using MOS field effect transistor in MOS integrated circuit and bridge type rectifier circuit

1 is a bridge type rectification circuit diagram using a conventional diode.

2 is an input and output waveform diagram of the bridge rectifier circuit of FIG.

3 (a) to 3 (h) are vertical cross-sectional views of a manufacturing process of a bridge rectifier circuit using a MOS field effect transistor constructed in an integrated circuit according to the present invention.

4 is an embodied circuit diagram of FIG.

The present invention relates to a method for manufacturing a bridge type rectifier circuit using a MOS field effect transistor and a diode, and a bridge type rectifier circuit. In particular, a method for manufacturing a bridge type rectifier circuit comprising a MOS field effect transistor and a diode in a MOS integrated circuit and a bridge type rectifier. It is about a circuit.

Conventional rectifying circuits for ac direct current output from ac inputs have been used separately from integrated circuits by half-wave or full-wave rectification using diodes, which are individual devices.

1 is a full-wave rectification circuit diagram constructed in the form of a bridge using a diode, which is a conventional discrete element.

In the figure, D ₁ -D ₄ is a rectifying diode, 1,2 is an AC input terminal, 3,4 is an output terminal of the rectified pulse flow.

2 (a) and 2 (b) are waveform diagrams of the AC input and rectified pulse current output of the bridge type rectifier circuit of FIG. 1, and FIG. 2 (a) is input to the AC input terminals 1 and 2 of FIG. Fig. 2 (b) is a full wave rectified waveform output to the output terminals 3 and 4 of Fig. 1.

When the positive voltage of the alternating current of FIG. 2 (a) is inputted to the alternating current input terminal 1 of FIG. 1, the diode D ₁ and the diode D ₃ become conductive, and the current flows into the alternating current input terminal ₁ . When the current flows to the AC input terminal 2 through the diode D ₃ , the positive voltage is applied to the output terminal 3. When the negative voltage of the AC of FIG. 2 (a) is applied to the AC input terminal 1 of FIG. Input terminal 2 receives a positive voltage and diode D ₂ and diode D ₄ are turned on so that current flows through the common input terminal 2, diode D ₂ , output terminals 3 and 4, and AC input terminal through diode D ₄ Since the current flows to 1 and the positive voltage is applied to the output terminal 3 as described above, the full-wave rectified pulse current as shown in FIG. 2 (b) appears at the output terminals 3 and 4.

There are many drawbacks in the case of integrated circuits in the bridge rectifier circuit using the diodes D ₁ -D ₄ of FIG. In other words, in the integrated circuit fabricated using the silicon wafer as a starting material, a voltage drop of 0.6-0.7 volts must exist due to the threshold voltage at the time of conduction of the diode and the on-resistance caused by the conduction at the time of conduction. (on resitance) together with the power loss.

Therefore, in the full-wave rectified bridge type rectifier circuit using four diodes D ₁ -D ₄ as shown in FIG. 1, four diodes are conducted for one cycle of the AC input, so the voltage drop and conduction of 0.6-0.7 volts by the one diode are conducted. In an integrated circuit chip in which a bridge-type rectifier circuit using the four diodes is incorporated, which causes heat generation by four times the power loss due to on-resistance of the time, the bridge in the chip is caused by the heat generation. The diodes D _1- D ₄ cannot be expected because of the characteristics of the integrated circuit components of the integrated rectifier circuit, the characteristics of the integrated circuits of the respective parts due to the temperature difference between the adjacent parts and the remote areas. It is not practical to incorporate the bridge type rectifier circuit to be used in an integrated circuit.

It is therefore an object of the present invention to provide a bridge rectifier circuit composed of MOS field effect transistors.

It is still another object of the present invention to provide a bridge rectifier circuit composed of MOS field effect transistors.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 (a) to 3 (h) are manufacturing process diagrams of a bridge type rectifier circuit using a MOS field effect transistor according to the present invention.

FIG. 3 (a) is a vertical cross-sectional view after diffusing a well during fabrication of a well-known SeaMOS transistor, in which 5 has a low concentration N-type substrate, 6 has a sio ₂ layer, and 7 has a low concentration P-type impurity Well layer.

FIG. 3 (a) shows a well diffusion for forming an n-channel MOS transistor in the fabrication of a Si-MOS integrated circuit after forming a SiO ₂ layer in a diffusion path on an N-type substrate having a low concentration N-type impurity as a starting material. Etching the SiO ₂ layer to form a window for the photolithography method, followed by injection of boron, which is a P-type impurity, with an ion accelerator, followed by high temperature heating in the diffusion furnace, The well layer 7 is formed by diffusion, and a new SiO ₂ layer 6a is formed on the upper part of the well layer 7 when the ion implanted P-type impurity is driven in the diffusion furnace.

Then, in order to diffuse the high concentration P-type impurity diffusion layer 8 of FIG. 3 (b) for the ohmic contact with the well layer having the low concentration P-type impurity, SiO ₂ layer 6a on the top of the high concentration P-type impurity diffusion layer 8 was After etching the SiO ₂ by the photolithography method, the P-type impurity is diffused in the diffusion path to form a high-concentration P-type impurity layer 8 as shown in FIG. A new SiO ₂ layer 8a grown at is formed to have a vertical cross-sectional structure as shown in FIG. 3 (b).

FIG. 3 (c) shows a vertical cross-sectional structure after diffusion of a high concentration of N-type impurities to form a source, drain, and diode of a MOS field source transistor, and FIG. 9 shows a source of a MOS field effect transistor. High concentration N-type impurity layer, 10 is a high concentration N-type impurity layer serving as a drain of the MOS field effect transistor, and 9a and 10a are SiO ₂ which is an oxide film grown when the n-type impurities of the high concentration n-type impurity layers 9 and 10 are diffused. 11 is a high concentration N-type impurity layer diffused by cathode formation, and 11a is a SiO ₂ layer which is an oxide film grown when the high concentration N-type impurity layer 11 is diffused.

After forming the high concentration P-type impurity layer 8 for the non-resistance contact of the well layer 7 as shown in FIG. 3 (b), the high concentration N-type impurity layer 9,10 for forming the source and drain of the MOS field effect transistor of FIG. And etching the SiO ₂ layer 6a of FIG. 3 (b) on the upper portion of the high concentration N-type impurity layer 11 for forming the cathode of the diode by photolithography, and diffusing the N-type impurity in the diffusion furnace in the third (c The high concentration N-type impurity layers 9, 10, and 11 are diffused into each other, and a new diffusion film SiO ₂ layers 9a, 10a, and 11a are grown thereon.

FIG. 3 (d) shows a vertical cross-sectional structure in the case where SiO ₂ , which is an oxide film of the focus forming portion and the gate forming portion of the MOS field transistor, is etched.

As shown in FIG. 3 (c), after the diffusion of the high concentration N-type impurities for forming the drain of the MOS field source transistor and the cathode of the source and the diode, the high-concentration N-type impurity for the resistivity contact of the well layer 7 is shown in FIG. 3 (d). After diffusion, the portion 12 for forming the contact of the high-concentration P-type impurity layer 8 for the non-resistance contact of the well layer 7 and the portion 13 for the contact between the source and the drain of the MOS field effect transistor as shown in FIG. When the SiO ₂ layer of the portion 14 for forming the oxide film is etched from SiO ₂ by photolithography, it becomes as shown in FIG. 3 (d).

FIG. 3 (e) shows a vertical cross-sectional structure after the gate forming oxide film of the MOS field transistor is grown. 15 is a gate oxide film of the MOS field transistor.

When the clean oxide film is grown in the diffusion path after the process of FIG. 3 (d), the entire gate oxide film 15 is grown as shown in FIG. 3 (e).

FIG. 3 (f) shows a vertical cross-sectional structure after etching the SiO ₂ layer, which is an oxide film, by photolithography for drawing the drain and source and diode cathode and anode electrodes of a MOS field effect transistor. The portion where the oxide film is etched to extract the source electrode of the MOS field effect transistor, 18 is the portion where the oxide film is etched to extract the drain electrode of the MOS field effect transistor, and 19 is the portion where the oxide film is etched to draw the anode electrode of the diode. 20 is a portion of the oxide film for etching the cathode of the diode.

After the process of FIG. 3 (e), the oxide film in part 16-20 of FIG. 3 (e) is etched by the photolithography method to withdraw the source and drain of the MOS field-effect transistor and the cathode and anode electrode of the diode. It becomes like (f).

FIG. 3 (g) shows a vertical cross-sectional structure of electrode formation of a bridge type rectifier circuit composed of a MOS field effect transistor and a diode. FIG. 3 (h) shows a wiring diagram of a vertical cross-sectional view of electrode formation shown in FIG. 3 (g). (g) In FIG. 20, gate electrode 21 of a Morse field effect transistor is a source electrode of a Morse field effect transistor, 22 is a drain electrode of a Morse field effect transistor, 23 is a anode electrode of a diode, and 24 is a cathode electrode of a diode. In Fig. 3 (h), F ₁ and F ₂ are Morse field effect transistors, D ₅ and D ₆ are diodes, 1,2 are AC input terminals, and 3 and 4 are rectified pulse current output terminals.

After the process of FIG. 3 (f), the substrate of FIG. 3 (f) is transferred to a vacuum evaporator, and aluminum is vacuum-deposited, and the gate electrode 20, the drain electrode 22, of the MOS field effect transistor by photolithography using an electrode forming mask. When the aluminum is etched by the source electrode 21 and the anode electrode 23 and the cathode electrode 24 of the diode to form the wiring as shown in FIG. 3 (h), the MOS field effect transistors F ₂ , F ₂ and diodes D ₅ , D ₆ are formed. It becomes a bridge rectifier circuit.

4 is a circuit diagram of a vertical cross-sectional structure in which the MOS field effect transistors F ₁ , F ₂ and diodes D ₅ , D ₆ of FIG. 3 (h) are incorporated in an integrated circuit. Identical with symbols and numbers.

Hereinafter, the circuit operation relationship of FIG. 4 will be described. Assume that an AC waveform as shown in FIG. 2 (a) is input to the AC input terminals 1 and 2. When the voltage of the center of the AC waveform in FIG. 2 (a) is input to the AC input terminal 1 in FIG. 4, the AC input terminal 2 becomes a negative potential, and the diode D ₅ becomes a forward bias to conduct, and the N-channel MOS field effect transistor The gate of F ₁ is turned off due to a negative voltage, and the gate of the n-channel MOS field effect transistor F ₂ is in a conductive state because a positive voltage is applied.

Therefore, current flows to AC input terminal 1, diode D ₅ , load applied to pulse output terminal 3, pulse output terminal 3 and 4, pulse output terminal 4, n-channel MOS field effect transistor F ₂ , and AC input terminal 2. 3 is a positive voltage.

Next, when the negative voltage of the AC waveform of FIG. 2 (a) is input to the AC input terminal 1 of FIG. 4, the AC input terminal 2 is subjected to a positive AC voltage, so that the diode D ₆ is conducted in the forward direction and the n-channel MOS field effect is applied. The gate voltage of the transistor F ₁ is also turned on because a positive voltage is applied, and the gate of the n-channel MOS field effect transistor F ₂ is turned off due to a negative voltage. Therefore, current flows through the AC input terminal 2, diode D ₆ , the pulse output terminal 3 and the load through the pulse output terminal 4, the n-channel MOS field effect transistor F ₁ to the AC input terminal 1, the positive AC voltage is input terminal As in the case of 1, the pulse current output terminal 3 becomes a positive voltage and outputs the pulse current as shown in FIG. 2 (b). Therefore, by using the Morse field effect transistors F ₁ and F ₂ , it is possible to eliminate the voltage drop of 0.6-0.7 volts caused when the diode is used.

As described above, since the present invention configures a bridge type rectifier circuit using a MOS field effect transistor and a diode, a voltage drop of 0.6-0.7 volts and power loss according to the diode conduction caused by the bridge type rectifier circuit using only diodes. The heat dissipation minimizes the change of the characteristics of each element in the integrated circuit, and has the advantage of manufacturing in the integrated process of the MOS integrated circuit.

Claims (2)

In the fabrication of a MOS integrated circuit, a first step of diffusing a well layer 7 and then a high concentration P-type impurity diffusion layer 8 is performed, and drain formation of a MOS field effect transistor is performed. Forming a high concentration N-type impurity layer 9 and a cathode of a diode; a second step of diffusing the high concentration N-type impurity layer 11; a third step of growing a gate oxide film 15 of a MOS field effect transistor; A bridge type using MOS field effect transistors in a MOS integrated circuit, characterized by having a fourth process of forming an electrode such that the bridge type rectifier circuit is composed of the effect transistors F ₁ , F ₂ and diodes D ₅ , D ₆ . Method of manufacturing rectifier circuit. In a bridge type rectifier circuit, when a positive AC voltage is input to the AC input terminal 1, the diode D ₅ and the MOS field effect transistor F ₂ become conductive, and a negative AC voltage is applied to the AC input terminal 1. A bridge type rectifier circuit using MOS field effect transistors in a MOS integrated circuit, characterized in that, when input, diode (D ₆ ) and MOS field effect transistor (F ₁ ) are conducted.

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