JP3210146B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

Description of the Field of the Invention The present invention relates to the structure of a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a schottky device using a PN junction diode and a Schottky barrier has been used as a rectifying device.
There is a method of using a barrier diode and a power MOSFET as a rectifying element. The PN junction diode has a forward voltage drop V due to the built-in potential of the PN junction.
F cannot be reduced below 0.8 V, and reverse recovery loss due to accumulation of minority carriers occurs. Since the Schottky barrier diode is a majority carrier device, VF can be reduced by using a barrier metal having a small Schottky barrier height without reverse recovery loss. However, as the height of the Schottky barrier decreases, the reverse leakage current increases. Therefore, there is a limit to reducing the Schottky barrier (2). On the other hand, since the power MOSFET has a current rising from 0 V, a rectifying element with a very small VF can be realized by using a MOSFET with a very small on-resistance. Further, since the device is a majority carrier device, there is no reverse recovery loss, and the reverse leakage current is very small because of the PN junction characteristics.

[0003]

2. Description of the Related Art The on-resistance of a power MOSFET has been realized by increasing the channel width per unit area by a fine processing technique. But,
As shown in FIG. 2, since the semiconductor device basically has a channel 3, a normal vertical MOSFE forming a channel on a plane is used.
At T, miniaturization is limited by the size of the channel length. Further, since there is a resistance component in the channel region 3, there is a limit in reducing the on-resistance. Further, since the gate oxide film 7 exists on the channel region 3, the gate source
The capacitance 15 between the gate and the drain and the capacitance 16 between the gate and the drain exist. Therefore, when such a power MOSFET is operated, a power loss occurs due to charging and discharging of these gate capacitances, so that it is not possible to increase the efficiency of electronic devices corresponding to the reduction in VF due to the reduction in on-resistance. There is.

[0004]

According to the present invention, there is provided a Schottky barrier region serving as a source region formed on a semiconductor substrate of a first conductivity type serving as a drain region, and extending over the Schottky barrier region and the drain region. In a semiconductor device having a gate oxide film and a gate electrode formed as described above and a source electrode in a window surrounded by the gate electrode, the source region in the window surrounded by the gate electrode has S
The i-plane has a groove having a depth of at least 0.1 μm to 2.0 μm from the Si plane of the gate region, and a Schottky barrier region serving as the source region is formed at the bottom of the groove from silicide. An end of the silicide is formed immediately below the gate electrode, has a second conductivity type impurity region immediately below the trench bottom silicide, and has an insulating film thicker than the gate oxide film in a drain region immediately below the gate electrode. A feature is that an impurity region of the second conductivity type is provided directly under the thick insulating film. ,

[0005]

When a power MOSFET is used as a synchronous rectifier, a gate drive power loss due to charging and discharging of a gate capacitance is reduced, and particularly when a high switching frequency is used, an on-resistance and a gate driving power are reduced. It is an object of the present invention to provide a semiconductor device for synchronous rectification having a very small capacitance.

[0006]

FIG. 1 is a structural view of one embodiment of the present invention, and FIG. 3 is an explanatory view of the operation. In FIG. 1, 1 is a high-concentration drain region, 2 is a low-concentration drain region, and 5 is a Schottky region. 7 is a gate oxide film, 8 is a poly-Si gate electrode, 9 is an interlayer insulating film, 10
Is a source electrode. FIG. 3 shows the rectification characteristics of the device. In one quadrant, there is a forward bias between the source and the drain. At this time, the gate voltage is positively biased with respect to the drain potential and the gate voltage is positively biased. Then, the surface of the N-type semiconductor in contact with the Schottky metal is in an accumulation state, and the N-type impurity concentration is higher. Therefore, the contact between the Schottky metal and the N-type semiconductor surface becomes ohmic contact, and the current starts to flow from 0V. Next, in the third quadrant, the source and the drain are in a reverse bias state. At this time, the gate voltage is biased to 0 or negative with respect to the drain potential. At this time, N
Current flows depending on the barrier height between the silicon and the silicide Schottky junction, but due to the spread of the depletion layer in the P-type shield region 4 and the floating P-type region 11,
The Schottky junction region is depleted, and the leakage current can be suppressed.

If the width of the gate electrode 8 is extremely small, the gate resistance increases, which causes a problem that high-frequency operation becomes difficult. In order to obtain a low gate resistance, it is necessary to secure a certain width of the gate electrode. However, when the width of the gate electrode is widened, the gate capacitance increases accordingly. Further, the depletion layer between the cells at the time of the reverse bias (4) assuring becomes difficult to be connected, which causes a problem that the reverse leakage current increases. Therefore,
A thick insulating film 6 is formed in the other drain region directly under the gate electrode which is not in contact with the Schottky metal, thereby reducing the gate capacitance in this region. Further, the depletion layer of each cell is connected between the cells via the P-type impurity region by the P-type impurity region 11 formed under the thick insulating film 6, so that the leakage current in the reverse direction is increased. Can be suppressed. When the synchronous rectifier thus manufactured is used in an electronic device, for example, a switching power supply, the on-resistance is small and the gate drive power is small, so that a high efficiency switching power supply can be obtained. ,Also,
Since the operation due to the parasitic bipolar transistor can be ignored, the reliability is improved.

FIGS. 4 (a) to 4 (l) are cross-sectional views showing the steps of a manufacturing method according to the present invention. First, (a) a low-concentration drain is applied to a high-concentration N-type substrate 1 serving as a high-concentration drain region. (B) a P-type impurity region 11 is formed in a part of a region serving as a gate electrode, and (c) a thick insulating film 6 is formed thereon. Is formed by thermal oxidation or CVD, and patterning is performed.
(D) Next, gate oxide film 7 and poly Si8 for gate electrode
To reduce the resistance of poly-Si, for example, POC
13 and so on to dope phosphorus to a high concentration. (E) Next,
Using the photoresist as a mask, patterning of poly-Si for the gate electrode is performed. At this time, the underlying Si is also etched by penetrating the poly-Si having the opened window to form a groove 12 having a depth in the range of 0.1 μm to 2.0 μm. (F) Next, the whole surface is oxidized. In this case, the oxide film thickness is poly Si
The region and the poly-Si window have different thicknesses due to different impurity concentrations. The poly Si region is formed thicker. (G)
Next, B + ion implantation and diffusion as P-type impurities are performed,
A P-type region 4 is formed. (H) Next, S in the poly-Si window
The oxide film on i is removed by a wet process. In this case, since the thickness on the poly-Si is thicker, the oxide film on the poly-Si remains.

(5) (i) Next, a metal is formed on the entire surface by vapor deposition or sputtering. The metal in this case is Ti, Pt, or the like.
(J) Next, low-temperature heat treatment at about 600 ° C.
The metal on Si in the i-window portion reacts with Si, and silicide 5a is formed only on Si in the poly-Si window portion. Further, an oxide film remains on the poly-Si, and the metal on this remains without reacting. Next, etching is performed with an etching solution having a selectivity between the silicide layer and the unreacted metal, for example, a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. In this case, the silicide formed at a low temperature remains only on the surface of the Si groove where the poly-Si window is open. Next, heat treatment at about 800 ° C. is performed to reduce the resistance of the silicide layer formed at 600 ° C. (K) Next, an interlayer insulating film is formed by a CVD method, a contact hole 9a is formed, and (l) an Al electrode 10 is formed.

[0010]

FIG. 5 is a characteristic diagram showing the relationship between the frequency (f) and the loss (w) of the embodiment of the present invention as compared with the conventional example. In the figure, the conventional example shows the respective characteristics of the present invention. According to the structure of the present invention, the ON resistance is smaller than that of the conventional power MOS, so that the conduction loss is small, and the gate capacitance is also small, so that the gate drive loss is small. Therefore, the loss as a rectifying element can be made very small as compared with the conventional power MOS, and the increase in loss can be made small even when the switching frequency becomes large. Normal power MOSFET
Since there is no parasitic bipolar transistor effect shown in FIG. Furthermore, since the Schottky barrier region can be formed in a self-aligned manner, the number of mask steps can be reduced, the steps can be simplified, and the on-resistance can be reduced, thereby reducing the chip size. Therefore, the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a structural view of an embodiment of the present invention (6).

FIG. 2 is a conventional structural diagram.

FIG. 3 is a diagram illustrating the operation of the present invention.

FIG. 4 is a process sectional view showing the manufacturing method of the present invention.

FIG. 5 is a characteristic diagram of the present invention compared to a conventional example.

[Explanation of symbols]

 Reference Signs List 2 drain region 3 channel region 4 shield region 5 silicide region 6 thick insulating film 7 gate oxide film 8 gate electrode 9 interlayer insulating film 10 source electrode 11 floating region 12 groove

Claims (1)

(57) [Claims] 1. A Schottky barrier region serving as a source region formed on a semiconductor substrate of a first conductivity type serving as a drain region, a gate oxide film and a gate electrode formed so as to extend over the Schottky barrier region and the drain region. And a source electrode in a window surrounded by the gate electrode, wherein the source region in the window surrounded by the gate electrode has a Si surface at least 0.1 μm to 2 μm larger than the Si surface of the gate region. A trench having a depth of 0.0 μm, a Schottky barrier region serving as the source region is formed from silicide at the bottom of the groove, and an end of the silicide serving as the source region is formed immediately below the gate electrode; An insulating film having a second conductivity type impurity region immediately below the silicide at the bottom of the trench and a drain region immediately below the gate electrode being thicker than the gate oxide film; And a semiconductor device having a second conductivity type impurity region immediately below the thick insulating film.