JPS6028393B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6028393B2 JPS6028393B2 JP4793677A JP4793677A JPS6028393B2 JP S6028393 B2 JPS6028393 B2 JP S6028393B2 JP 4793677 A JP4793677 A JP 4793677A JP 4793677 A JP4793677 A JP 4793677A JP S6028393 B2 JPS6028393 B2 JP S6028393B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- substrate bias
- semiconductor
- generation device
- semiconductor equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
- H01L27/0222—Charge pumping, substrate bias generation structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
‘１’発明の利用分野
本発明は、ＭＯＢ型集積回路における基板バイアス発生
装置を有する半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION '1' Field of Application of the Invention The present invention relates to an improvement in a semiconductor device having a substrate bias generation device in a MOB type integrated circuit.
‘２’ 従来技術 第１図は従来の基板バイアス発生装置の構成を示す。‘2’ Conventional technology FIG. 1 shows the configuration of a conventional substrate bias generating device.
この動作は自動発振器により発生させた発振信号をＭＯ
Ｓ型容量１とＭＯＳ型電界効果トランジスタ（以下ＭＯ
ＳＦＥＴと略記する）２によって発振信号の電圧レベル
を負万向に移動させ、ＭＯＳＦＥＴ３により整流して負
の基板バイアス電圧Ｖｓ血を発生させる。第２図はＭＯ
Ｓ容量１、ＭＯＳＦＥＴ２，３により構成された電圧レ
ベル移動及び整流回路部の断面構造例を示すもので、４
は集積回路チップをのせる良導電材料よりなるパッケー
ジの台、５はＳｉ基板、６〜６肌は基板と異なる導電型
の不純物により形成された拡散層で６′はチップのスク
ラィブ領域である、７〜７′″および８，８′は酸化膜
、９〜９″は良導電材料によって形成されたゲート電極
、１０〜１０″はＡＩ等の良導電材料により形成された
配線電極である。In this operation, the oscillation signal generated by the automatic oscillator is
S type capacitor 1 and MOS type field effect transistor (hereinafter referred to as MO
(abbreviated as SFET) 2 moves the voltage level of the oscillation signal in the negative direction, and MOSFET 3 rectifies it to generate a negative substrate bias voltage Vs. Figure 2 is MO
This figure shows an example of the cross-sectional structure of a voltage level shifting and rectifying circuit section composed of an S capacitor 1 and MOSFETs 2 and 3.
is a package base made of a highly conductive material on which an integrated circuit chip is placed; 5 is a Si substrate; 6 and 6 are diffusion layers formed of impurities of a conductivity type different from that of the substrate; 6' is a scribe region of the chip; 7 to 7'' and 8 and 8' are oxide films, 9 to 9'' are gate electrodes formed of a highly conductive material, and 10 to 10'' are wiring electrodes formed of a highly conductive material such as AI.
このような従来の構成では、第２図に示したように基板
バイアス発生装置によって発生した電位Ｖｓ伽をＳｉ基
板５に伝えるために配線電極１０にＡＩ線１１（直径は
約３０仏ｍ）等を用いて集積回路チップの外部で１０と
４を接続しなければならない。したがって本基板バイア
ス発生装置では山配線１１と１０とを接続するために１
０の面積を１００×１００れで程度に大きくとらなけれ
ばならず、集積回路チップの面積が大きくなってしまう
こと、および外部配線１ １をとりつけなければならな
いために、余分の集積回路製造工程が必要になる欠点が
ある。‘３’発明の目的
本発明は上記従来装置の欠点をなくし、面積が小さく、
かつ外部配線の不要な基板バイアス発生装置を含む半導
体装置を提供することを目的とする。In such a conventional configuration, as shown in FIG. 2, an AI wire 11 (with a diameter of about 30 meters) or the like is connected to the wiring electrode 10 in order to transmit the potential Vs generated by the substrate bias generator to the Si substrate 5. must be used to connect 10 and 4 outside the integrated circuit chip. Therefore, in this substrate bias generation device, in order to connect the mountain wirings 11 and 10,
Since the area of 0 must be made as large as 100 x 100, the area of the integrated circuit chip becomes large, and external wiring 11 must be attached, resulting in an extra integrated circuit manufacturing process. There are drawbacks that make it necessary. '3' Purpose of the Invention The present invention eliminates the drawbacks of the above-mentioned conventional device, has a small area,
Another object of the present invention is to provide a semiconductor device including a substrate bias generation device that does not require external wiring.
｛４１ 実施例 以下、本発明を実施例を参照して詳細に説明する。{41 Examples Hereinafter, the present invention will be explained in detail with reference to Examples.
第３図は本発明の実施例を示すものである。本実施例に
おいてはＭＯＳＦＥＴのソース拡散層６′が、スクラィ
ブ領域に形成された拡散層６と接続された構造になって
いる。このような構造においてスクラィブ領域拡散層６
と基板Ｓｉ５で形成されるＰＮ接合は集積回路チップの
スクラィブ作業において機械的に破壊されているために
ＰＮ接合の逆方向電流１２は大きな値となるために、６
と５とは電気的に導通した状態になる。したがって本実
施例においては、第２図の外部配線１１を用いなくても
６と５とは電気的に接続されることとなり、また大きな
面積を有する配線層１０が不要となるために、小さな面
積で基板バイアス発生装置を提供することができる。‘
５’まとめ
以上述べたように、本発明により面積が小さくかつ外部
配線のいらない基板バイアス発生装置を実現することが
できる。FIG. 3 shows an embodiment of the invention. In this embodiment, the source diffusion layer 6' of the MOSFET is connected to the diffusion layer 6 formed in the scribe region. In such a structure, the scribe region diffusion layer 6
Since the PN junction formed by the substrate Si5 and the substrate Si5 is mechanically destroyed during the scribing operation of the integrated circuit chip, the reverse current 12 of the PN junction becomes a large value.
and 5 are electrically connected. Therefore, in this embodiment, 6 and 5 are electrically connected without using the external wiring 11 shown in FIG. 2, and since the wiring layer 10 having a large area is not necessary, can provide a substrate bias generator. '
5' Summary As described above, according to the present invention, it is possible to realize a substrate bias generating device that has a small area and does not require external wiring.
第１図は従来の基板バイアス発生装置の構成図、第２図
は基板バイアス発生装置に用いられている電圧レベル移
動回路および整流回路部の断面構造を示す図、第３図は
本発明の実施例を示す図である。
第７域
第２図
第３図FIG. 1 is a configuration diagram of a conventional substrate bias generation device, FIG. 2 is a diagram showing a cross-sectional structure of a voltage level shifting circuit and a rectification circuit used in the substrate bias generation device, and FIG. 3 is a diagram showing an embodiment of the present invention. It is a figure which shows an example. Area 7 Figure 2 Figure 3
Claims (1)
発生装置とを有する半導体装置において、上記基板バイ
アス発生装置の出力端子を構成する半導体素子の不純物
領域を、スクライブ領域に設けられた不純物領域と一体
化し上記基板バイアス発生装置により発生したバイアス
電圧を上記半導体基板に印加することを特徴とする半導
体装置。1. In a semiconductor device having a semiconductor substrate and a substrate bias generation device provided on the substrate, an impurity region of a semiconductor element constituting an output terminal of the substrate bias generation device is an impurity region provided in a scribe region. A semiconductor device, wherein a bias voltage generated by the substrate bias generating device is applied to the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4793677A JPS6028393B2 (en) | 1977-04-27 | 1977-04-27 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4793677A JPS6028393B2 (en) | 1977-04-27 | 1977-04-27 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53133381A JPS53133381A (en) | 1978-11-21 |
| JPS6028393B2 true JPS6028393B2 (en) | 1985-07-04 |
Family
ID=12789249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4793677A Expired JPS6028393B2 (en) | 1977-04-27 | 1977-04-27 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6028393B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593252A (en) * | 1979-01-05 | 1980-07-15 | Mitsubishi Electric Corp | Substrate potential generating apparatus |
| US4591738A (en) * | 1983-10-27 | 1986-05-27 | International Business Machines Corporation | Charge pumping circuit |
-
1977
- 1977-04-27 JP JP4793677A patent/JPS6028393B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53133381A (en) | 1978-11-21 |
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