JPS59189665A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59189665A JPS59189665A JP6476283A JP6476283A JPS59189665A JP S59189665 A JPS59189665 A JP S59189665A JP 6476283 A JP6476283 A JP 6476283A JP 6476283 A JP6476283 A JP 6476283A JP S59189665 A JPS59189665 A JP S59189665A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- electrode
- input
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 17
- 239000010408 film Substances 0.000 abstract description 14
- 230000000670 limiting effect Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 230000001681 protective effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は半導体集積回路装置（以後、ＩＣと呼ぶ） Ｖ
Ｃ関し、特ＶＣ高周波用ｉＣや低雑音特性全要求される
低周波前置増巾ＩＣの入力破壊防止に関するものである
。[Detailed description of the invention] The non-invention is a semiconductor integrated circuit device (hereinafter referred to as IC) V
Regarding C, it is concerned with preventing input destruction of especially VC high-frequency ICs and low-frequency preamplifier ICs that require full low-noise characteristics.
高周波用ＩＣや低周波前置増巾ｘｃｖｃおいては、初段
回路の構成、性能がＩＣ全体の特性全左右することが少
なくない。例えば、増巾回路の雑音特性は、初段州中部
の雑音特性が支配的である。従っテ、初段州中部に用い
られるトランジスタは、高い電流増巾率を有し、かつベ
ース広がり抵抗（ｒｂｂ’）の低いものが必要とされ、
その具体的な形状として、丸形エミッタ、丸形ベースを
有するトランジスタや、複数個のベース電極を有するマ
ルチベーストランジスタが使用されている０通常、これ
らトランジスタのベース電極部は直接、ＩＣ外部の入力
端子ＶＣ接続されることが望ましいが、入力端子ＶＣ印
加される種々の異常電圧により、 ）ランジスタの劣
化あるいは破壊から傑物するための対策が必要であり１
保護用抵抗、ダイオード等が用いられる。In high-frequency ICs and low-frequency preamplifier xcvcs, the configuration and performance of the first stage circuit often determine the entire characteristics of the IC. For example, the noise characteristics of the amplification circuit are dominated by the noise characteristics in the central part of the first stage. Therefore, the transistor used in the first stage is required to have a high current amplification rate and a low base spread resistance (rbb').
Specifically, transistors with a round emitter and round base, and multi-base transistors with multiple base electrodes are used.Normally, the base electrode of these transistors is directly connected to the input external to the IC. It is desirable to connect the terminal VC, but due to various abnormal voltages applied to the input terminal VC, it is necessary to take measures to prevent deterioration or destruction of the transistor.1
Protective resistors, diodes, etc. are used.
例えば、第１図に示すような回路構成の入力段において
は、トランジスタ６のベースに接続された入力端子５が
電源端子１と短絡した場合、あるいは端子５ ＩＣ正の
静電パルスが印加された場合、入力端子５から入カドラ
ンジスタロのベース・エミッタ間全通る電流経路７を介
して過大電流が流れ、トランジスタ６０ベース・エミッ
タ間接合の劣化、破壊音生ずる。尚、第１図において、
２は電流源として働ら（ＰＮＰ）ランジスタ、３は負荷
抵抗、そして４は次段へ接続される初段の出力端子であ
り、この出力端子は集積回路内に構成されている。For example, in the input stage with the circuit configuration shown in Fig. 1, if the input terminal 5 connected to the base of the transistor 6 is short-circuited with the power supply terminal 1, or if a positive electrostatic pulse is applied to the terminal 5 IC. In this case, an excessive current flows from the input terminal 5 through the entire current path 7 between the base and emitter of the input quadrant transistor, causing deterioration of the base-emitter junction of the transistor 60 and generation of destructive noise. In addition, in Figure 1,
2 is a (PNP) transistor that serves as a current source, 3 is a load resistor, and 4 is an output terminal of the first stage connected to the next stage, and this output terminal is configured within the integrated circuit.
従って、このような場合、保護ダイオード８゜保護抵抗
９全第２図のように配置して、入力端子５の電位全フラ
ングし、かつ電流径路７？介する流入電流の制限を行な
う、抵抗９はトランジスタｌのベースと入力端子５との
間に接続され、ダイオード８は入力端子５−電源端子１
間に接続される。Therefore, in such a case, the protective diode 8° and the protective resistor 9 are arranged as shown in FIG. A resistor 9 is connected between the base of the transistor l and the input terminal 5, and a diode 8 is connected between the input terminal 5 and the power supply terminal 1.
connected between.
同様ＶＣ，第３図のような回路構成では、トランジスタ
１１のベースに接続された入力端子１５のグランド電位
への短絡や負の静電パルスＶこより、トランジスタ１１
０ベース・コレクタ間を介する電流径路１６を通じて過
大電流が流れる。第３図において、１２はＩＣ内の次段
用出力端子、１３は負荷抵抗、そして１４は電流源とし
て働ら（ＮＰＮトランジスタ全それぞれ示す。このため
、第４図に示す如く、保護ダイオード１８．保護抵抗１
７を接続して第２図と同じように保護している。Similarly, in the circuit configuration of VC, as shown in FIG.
An excessive current flows through the current path 16 between the zero base and the collector. In FIG. 3, 12 is an output terminal for the next stage in the IC, 13 is a load resistor, and 14 is a current source (all NPN transistors are shown). Therefore, as shown in FIG. 4, protection diodes 18. Protection resistance 1
7 is connected and protected in the same way as in Figure 2.
しかしながら、第２図２第４図の回路ＶＣおいては、保
護抵抗９．１７は、初段トランジスタ６゜１４のベース
抵抗となり、この結果、雑音特性を悪化させる。よって
、電気的特性の面からはできるかぎり低抵抗であること
が望ましく、逆ＶＣ電流制限の効果からは、できるかぎ
り高抵抗であることが好ましい。However, in the circuit VC of FIG. 2 and FIG. 4, the protective resistor 9.17 becomes the base resistance of the first stage transistor 6.14, and as a result, the noise characteristics deteriorate. Therefore, in terms of electrical characteristics, it is desirable that the resistance be as low as possible, and in terms of the effect of limiting the reverse VC current, it is desirable that the resistance be as high as possible.
このようｒＣ１従来の方法Ｖこおいては、保護抵抗の抵
抗値の設計が電気的特性、入力回路保護効果の両面に満
足するように行なわなければならないという欠点を有し
、電気的特性全優先すると保護効果は充分でなかった。As described above, the rC1 conventional method V has the disadvantage that the resistance value of the protective resistor must be designed to satisfy both the electrical characteristics and the input circuit protection effect, and the electrical characteristics have to be prioritized. The protective effect was not sufficient.
不発明の目的は、通電動作時においては電気的特性への
影響が少なく１反面、電流制限時ＶＣは十分な制限効果
？得られる入力保護回路全もった半導体装置ケ提供する
ことＶＣある。The purpose of the invention is to have little effect on electrical characteristics during current-carrying operation, but on the other hand, does VC have a sufficient limiting effect during current limiting? VC provides a semiconductor device with all the input protection circuits available.
本発明（は、電流制限用の抵抗を半導体基板内に形成さ
れた抵抗領域と半導体基板上ＶＣ形成された抵抗領域と
を並列接続して構成し、かつ基板の抵抗領域の抵抗値を
入力端子ＶＣ応じて変化させること全特徴とする。In the present invention, a current limiting resistor is constructed by connecting in parallel a resistance region formed in a semiconductor substrate and a resistance region formed as a VC on the semiconductor substrate, and the resistance value of the resistance region of the substrate is input to an input terminal. All features are to be changed according to VC.
以下１図面を参照して不発明の実施例を詳細に説明する
。Hereinafter, embodiments of the invention will be described in detail with reference to one drawing.
本発明の一実施例を示す平面図および断面図を第５図（
ａ）および（ｂ） ｖｃそれぞれ示す。第５図で示され
た半導体装置は次のように形成される。A plan view and a sectional view showing one embodiment of the present invention are shown in FIG.
a) and (b) vc are shown respectively. The semiconductor device shown in FIG. 5 is formed as follows.
まず、比抵抗１〜３Ω−ｃｍ程度のＰ型基板１９上に使
用目的に応じた適当な比抵抗（０５〜４Ω−ｃｍ程度）
全有するＮ型エピタキシャル層２０を形成する。次に、
Ｎ型エピタキシャル層２ｏの表面よりＰ型不純物例えば
ボロンを拡散あるいはイすン注入することＶＣより、層
抵抗の比較的高い（例えば３にΩ／口程度）Ｐ型半導体
領域２１を形成し、その表面および前記Ｎ型エピタキシ
ャル層２００表面に絶縁被膜例えば熱酸化してシリコン
酸化膜２２を形成する。しかる後に、多結晶シリコン薄
膜會シリコン酸化膜２２上に選択的に形成し。First, a suitable resistivity (about 05 to 4 Ω-cm) according to the purpose of use is placed on the P-type substrate 19 with a specific resistance of about 1 to 3 Ω-cm.
An N-type epitaxial layer 20 is formed over the entire structure. next,
By diffusing or implanting a P-type impurity, such as boron, from the surface of the N-type epitaxial layer 2o, a P-type semiconductor region 21 having a relatively high layer resistance (for example, about 3Ω/hole) is formed by VC. An insulating film such as a silicon oxide film 22 is formed on the surface and the surface of the N-type epitaxial layer 200 by thermal oxidation. Thereafter, a polycrystalline silicon thin film is selectively formed on the silicon oxide film 22.
Ｎ型不純物例えばリン全導入して高濃度Ｎ型多結晶シリ
コン薄膜領域２３を設ける。次に、本装置の表面全体に
絶縁被膜としてのシリコン酸化膜２４を例えばＣＶＤ法
などにより形成し、Ｐ型不純物領域２１および高濃度Ｎ
型多結晶シリコン薄膜領域２３の両端に電極部を設ける
ためＶＣ開口部２５全設ける。次に、開口部２５および
高濃度Ｎ型多結晶シリコン薄膜２４＠上の絶縁被膜２４
上に低抵抗物質例えばアルミニウムを選択的に形成して
電極部２６−１．２６−２および２７を得る。尚、第５
図（ａ） ＶＣＵシリコン収１１１Ｓ膜２２および２４
は図示していない。また、エピタキシャル＃２ｏｖｃＢ
トランジスタや抵抗等の他の素子も形成されるものであ
る。A high concentration N-type polycrystalline silicon thin film region 23 is provided by completely introducing an N-type impurity, for example, phosphorus. Next, a silicon oxide film 24 as an insulating film is formed on the entire surface of the device by, for example, the CVD method, and the P-type impurity region 21 and high concentration N
In order to provide electrode portions at both ends of the polycrystalline silicon thin film region 23, all VC openings 25 are provided. Next, the insulating coating 24 on the opening 25 and the high concentration N-type polycrystalline silicon thin film 24@
A low resistance material such as aluminum is selectively formed thereon to obtain electrode portions 26-1, 26-2 and 27. Furthermore, the fifth
Figure (a) VCU silicon 111S films 22 and 24
is not shown. Also, epitaxial #2ovcB
Other elements such as transistors and resistors are also formed.
この様な構造Ｖこおいて、電極部２６−１’（ｒ第１図
乃至第４図で示した入力端子５．１５ＶＣ，もう一方の
電極２６−２に人力トランジスタ２，１１のベースにそ
れぞれ接続し、さらに電極部２７を特定の電位に固定し
て入力回路における過電流制限素子とする。この場合、
電極部２７は電源電圧より低い電位に設定されることが
必要である。しタカっテ、電極２７は入力トランジスタ
のベースに接続されている電極２６−２に接続して、第
６図の如き構造とすることも可能である。In such a structure V, the input terminal 5.15VC shown in FIGS. In addition, the electrode portion 27 is fixed at a specific potential to serve as an overcurrent limiting element in the input circuit.In this case,
The electrode portion 27 needs to be set at a potential lower than the power supply voltage. Alternatively, the electrode 27 may be connected to the electrode 26-2 connected to the base of the input transistor to form a structure as shown in FIG. 6.
かかる構造および接続関係の過電流制限素子を有する半
碑体釦ＩＣおいて、いま、通常動作時全仮定すると、入
力端子に接続された電極２６−１に加えられる信号は比
較的微弱であり、ベース端子側の電極２６−２との電位
差はそれほど高くない。したがって、電極２７とその直
下の尚濃度〜型多結晶シリコン薄膜領域２３との電界は
弱く・多結晶シリコン薄膜領域２３とその上部の絶縁被
膜２４との界面より多結晶シリコン薄膜領域２３側に広
がる空乏層は無視てきうるものである。よって、この時
の電極２６−１および２６−２両端の抵抗は、Ｐ型半導
体領域２１と高濃度Ｎ型多結晶シリコン薄膜領域２３と
の合成抵抗分であって十分低い抵抗値が得られる。っま
シ、初段トランジスタのベース抵抗増加分は、無視でき
る程度である。In a half-shaped button IC having an overcurrent limiting element having such a structure and connection relationship, assuming that during normal operation, the signal applied to the electrode 26-1 connected to the input terminal is relatively weak; The potential difference with the electrode 26-2 on the base terminal side is not so high. Therefore, the electric field between the electrode 27 and the polycrystalline silicon thin film region 23 directly below it is weak and spreads toward the polycrystalline silicon thin film region 23 from the interface between the polycrystalline silicon thin film region 23 and the insulating film 24 above it. The depletion layer can be ignored. Therefore, the resistance across the electrodes 26-1 and 26-2 at this time is the combined resistance of the P-type semiconductor region 21 and the heavily doped N-type polycrystalline silicon thin film region 23, and a sufficiently low resistance value can be obtained. However, the increase in base resistance of the first stage transistor is negligible.
しかしながら、入力端子側になんらかの異常状態によジ
高い電位が印加された場合、入力端子側電極２６−１は
それＶＣ追従して電位が上昇し始める。一方、初段トラ
ンジスタ側電極２６−２はほぼトランジスタのベース電
位に固定されている。However, if a higher potential is applied to the input terminal side due to some abnormal condition, the input terminal side electrode 26-1 follows the VC and the potential begins to rise. On the other hand, the first-stage transistor side electrode 26-2 is fixed approximately at the base potential of the transistor.
したがって、第５図、第６図の双方において、電極２７
と直下の多結晶シリコン薄膜領域２３との電界が上昇し
、それＶＣつれ多結晶シリコン薄膜領域２３内部に空乏
層が広が９両端間の抵抗が増加し始め、Ｐ型半導体領域
２１との合成抵抗も同時に増加する。そして、多結晶シ
リコン薄膜領域２３の高電位０１ｌｌ’（電極２６−１
）で、空乏層が多結晶シリコン薄膜領域２３底部まで
達すると、その抵抗は無限大となり、Ｐ型半導体領域２
１の抵抗１［自。Therefore, in both FIGS. 5 and 6, the electrode 27
The electric field between VC and the polycrystalline silicon thin film region 23 directly below rises, and as the electric field increases, a depletion layer spreads inside the polycrystalline silicon thin film region 23 and the resistance between both ends of the VC begins to increase, resulting in synthesis with the P-type semiconductor region 21. Resistance also increases at the same time. Then, the high potential 01ll' of the polycrystalline silicon thin film region 23 (electrode 26-1
), when the depletion layer reaches the bottom of the polycrystalline silicon thin film region 23, its resistance becomes infinite and the P-type semiconductor region 2
1 resistance 1 [self.
にまで達する・つまり、電極２６−１側に異常電圧が印
加されると、それＶＣ応じて抵抗値が増加する。In other words, when an abnormal voltage is applied to the electrode 26-1 side, the resistance value increases in accordance with VC.
このように、通常時ＶＣは十分低く、異状電圧印加時Ｖ
Ｃは十分高い抵抗値をそれぞれ有Ｔる過大電流制限用素
子を実現できる。In this way, VC at normal times is sufficiently low, and when abnormal voltage is applied, V
C can realize an overcurrent limiting element having a sufficiently high resistance value.
さらに、Ｎ型エピタキシャル領域２０？：電源電圧ニハ
イアスすることにより、Ｎ型エピタキシャル領域２（ｌ
陰極側、Ｐ型半導体領域２１を陽極側とそれぞれとする
ダイオード構造が得られるので第２図、第４−図で示し
たダイオード８．１８も構成される。つまジ、本発明の
半導体装置を入力端子と初段トランジスタのベース間に
接続するだけで、通常動作時には電気的特性ＶＣ悪影響
？与えない、効果の大きい入力回路保護装置が得られる
。Furthermore, N type epitaxial region 20? : By lowering the power supply voltage, the N-type epitaxial region 2 (l
Since a diode structure is obtained in which the cathode side and the P-type semiconductor region 21 are the anode side, the diode 8.18 shown in FIGS. 2 and 4 is also constructed. Finally, if the semiconductor device of the present invention is simply connected between the input terminal and the base of the first stage transistor, will the electrical characteristics VC be adversely affected during normal operation? A highly effective input circuit protection device that does not cause damage to the input circuit can be obtained.
Ｐ型半導体領域２１は高抵抗であることが望ましいが、
層抵抗上あ壕り高抵抗領域が得られない場合は、ｉ；３
７図に示すように、領域２１を蛇行して形成アれば必要
とする抵抗値を得ることが容易である。Although it is desirable that the P-type semiconductor region 21 has high resistance,
If a high resistance region cannot be obtained in the layer resistance, i; 3
As shown in FIG. 7, if the region 21 is formed in a meandering manner, it is easy to obtain the required resistance value.
本発明で示されｆｃ電流制限抵抗はトランジスタと同一
絶縁領域内ＶＣ形成することも可能である。The fc current limiting resistor shown in the present invention can also be formed in the same insulation region as the transistor.
丁なわち、第８図に示すようＶＣ，領域２１は抵抗領域
となると共ｖｃＮＰＮ）ランジスタのベース領域となり
、エミッタ領域３０がその中に形成されている。領域２
０は高濃度絶縁Ｐ 領域２９ＶＣよって他から絶縁され
、又、基板１９との境界部には埋込み領域２８が形成さ
れている。領域２０ ＶＣはコレクタコンタクト領域３
３が形成すれ、これからコレクタ電極３２が導出されて
いる。エミッタ′１極３１がエミッタ領域３０ＶＣ形成
されている。That is, as shown in FIG. 8, the VC region 21 becomes a resistance region and a base region of a transistor (vcNPN), and an emitter region 30 is formed therein. Area 2
0 is insulated from others by a heavily doped insulating P2 region 29VC, and a buried region 28 is formed at the boundary with the substrate 19. Region 20 VC is collector contact region 3
3 is formed, from which a collector electrode 32 is led out. An emitter '1 pole 31 is formed in an emitter region 30VC.
上述した実施例では、入力端子に高電圧が印加された場
合について述べたが、入力端子に負の電圧が印加された
時の初段トランジスタ保護のためＶＣは、高濃度Ｎ型多
結晶シリコン薄膜領域２３を高濃度Ｐ型多結晶シリコン
薄膜領域とし、電極２７紮初段トランジスタのベース電
位あるｂは電源電圧ｖＣすることにより、同等の効果が
得られる。また、Ｐ型半導体領域２１’ｚＮ型半導体領
域と１−ることＶＣよって保護ダイオードの効果をもた
せることも可能である。In the above embodiment, the case where a high voltage is applied to the input terminal has been described, but in order to protect the first stage transistor when a negative voltage is applied to the input terminal, VC is a high concentration N-type polycrystalline silicon thin film region. The same effect can be obtained by using 23 as a heavily doped P-type polycrystalline silicon thin film region, and setting the electrode 27 and the base potential b of the first stage transistor to the power supply voltage vC. Further, it is also possible to provide the effect of a protection diode by using the P-type semiconductor region 21'zN-type semiconductor region and VC.
第１図は代表的な増巾回路初段部を示す回路図、第２図
は第１図の回路に初段トランジスタ保護用素子全追加し
た回路図、第３図は、代表的な他の増巾回路初段部全示
す回路図、第４図は第３図の回＠ＶＣ初段トランジスタ
保護用素子を追加した回路図、第５図（ａ）、 （ｂ）
はそれぞれ本発明の一実施例の平面図および断面図、第
６図は不発明の第２の実施例を示す断面図、第７図は本
発明の第３の実施例を示す断面図、第８図は本発明の第
４の実施例？示ア断面図である。
１．１０は電源端子、２．１４は電流源として働ら（Ｐ
ＮＰ）ランジスタ、３．１３は負荷抵抗、４．１２は出
力端子、５．１５は入力端子、６゜１１は初段増巾用Ｎ
ＰＮ）ランジスタ、７．１６は入力端子より流入する過
大電流経路、８．１８は保護ダイオード、９．１７は保
護抵抗、１９はＰ型基板、２０はＮ型エピタキシャル層
、２１はＰ型牛尋体領域、２２はシリコン酸１ヒ膜、２
３は尚濃度Ｎ型多結晶シリコン薄膜領域、２４は酸化膜
、２５に電極形成用開口部、２６−１．２６−２は電極
部、２７は電極部、２８は高濃度埋入みＮ 層、２９は
高濃度絶縁Ｐ 層、３０はエミッタ領域、３１はエミッ
タ電極、３２はコレクタ電第２図
第す図
／ｑ
第７区Figure 1 is a circuit diagram showing the first stage of a typical amplifier circuit, Figure 2 is a circuit diagram in which all first stage transistor protection elements are added to the circuit in Figure 1, and Figure 3 is a circuit diagram of another typical amplifier circuit. A circuit diagram showing the entire first stage of the circuit. Figure 4 is a circuit diagram of the circuit in Figure 3 with the addition of a VC first stage transistor protection element. Figures 5 (a) and (b)
6 is a sectional view showing a second embodiment of the invention, FIG. 7 is a sectional view showing a third embodiment of the invention, and FIG. Is Figure 8 the fourth embodiment of the present invention? FIG. 1.10 is a power supply terminal, 2.14 is a current source (P
NP) transistor, 3.13 is load resistance, 4.12 is output terminal, 5.15 is input terminal, 6゜11 is N for first stage expansion
PN) transistor, 7.16 is an excessive current path flowing from the input terminal, 8.18 is a protection diode, 9.17 is a protection resistor, 19 is a P-type substrate, 20 is an N-type epitaxial layer, 21 is a P-type cowhide body region, 22 is silicon acid 1 arsenic film, 2
3 is a still-concentrated N-type polycrystalline silicon thin film region, 24 is an oxide film, 25 is an opening for forming an electrode, 26-1, 26-2 is an electrode section, 27 is an electrode section, and 28 is a high-concentration buried N layer. , 29 is a high concentration insulating P layer, 30 is an emitter region, 31 is an emitter electrode, 32 is a collector electrode.
Claims (1)
上に絶縁層を介して形成された第２の半導体領域とが並
列に接続され、該第２の半導体領域に対し制御電極層が
設けられていることを特徴と一７６半導体装置。A first semiconductor region formed within a semiconductor substrate and a second semiconductor region formed on the region via an insulating layer are connected in parallel, and a control electrode layer is provided for the second semiconductor region. 176 semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6476283A JPS59189665A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6476283A JPS59189665A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59189665A true JPS59189665A (en) | 1984-10-27 |
| JPS6410101B2 JPS6410101B2 (en) | 1989-02-21 |
Family
ID=13267515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6476283A Granted JPS59189665A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59189665A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313371A (en) * | 1986-07-03 | 1988-01-20 | Rohm Co Ltd | Semiconductor device |
| FR2634076A1 (en) * | 1988-07-11 | 1990-01-12 | Samsung Electronics Co Ltd | Input detection device making it possible to improve the delay time of the input stage in semiconductor devices |
| JP2011054775A (en) * | 2009-09-02 | 2011-03-17 | Dainippon Printing Co Ltd | Organic transistor, circuit element, and manufacturing method of those |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285125A (en) * | 1989-04-27 | 1990-11-22 | Sanwa Shutter Corp | Balcony with double swinging doors |
-
1983
- 1983-04-13 JP JP6476283A patent/JPS59189665A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313371A (en) * | 1986-07-03 | 1988-01-20 | Rohm Co Ltd | Semiconductor device |
| FR2634076A1 (en) * | 1988-07-11 | 1990-01-12 | Samsung Electronics Co Ltd | Input detection device making it possible to improve the delay time of the input stage in semiconductor devices |
| JP2011054775A (en) * | 2009-09-02 | 2011-03-17 | Dainippon Printing Co Ltd | Organic transistor, circuit element, and manufacturing method of those |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6410101B2 (en) | 1989-02-21 |
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