JP3008900B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device having a temperature detecting function.
You. [0002] 2. Description of the Related Art Differences in the operation of semiconductor devices having active functions
Conventionally, to avoid destruction due to the
A semiconductor element having an active function in one semiconductor substrate, for example,
Form a heat-sensitive element such as a heat-sensitive thyristor, and
The temperature of the semiconductor substrate is detected and the semiconductor
The element is controlled to protect it from thermal destruction. [0003] [0005] However, this
With the conventional temperature detection function, the semiconductor element inside the semiconductor substrate
Special consideration is given to the positional relationship between the element and the thermal element.
Not a plurality of MOS type unit cells as semiconductor elements
When a power element consisting of a set of
To protect the semiconductor device from thermal destruction
Is insufficient. The present invention has been made in view of the above points.
To ensure that semiconductor elements are protected from thermal damage.
It is an object of the present invention to provide a semiconductor device which can be used. [0005] In order to achieve the above object,
In the semiconductor device of the present invention, a current flows during the conduction state.
The semiconductor power device that emits high heat by forming
A semiconductor chip, wherein the semiconductor power of the semiconductor chip is
-Area inside the element layout areaAbove the surface
Through the rimDetects the heat generation status of the semiconductor power element
A heat sensitive element portion is provided. [0006] According to the present invention, there is provided a semiconductor device comprising:
When the temperature of the printed circuit board rises abnormally,
When the heating temperature of the power element becomes abnormally high,
The temperature rise can be detected by the heat-sensitive element section. On this occasion,
The parasitic operation caused by the integration of the thermal element can be eliminated.
And furtherThermal power element is a semiconductor power elementIs the layout
Area inside the area to beIn other words, for semiconductor power devices
Enclosed and has low heat dissipation, and is relatively warm even among semiconductor chips.
It is located in the area where the temperature rises easily.
Conduction of semiconductor power element by detecting temperature in thermal element
The control ensures that the semiconductor power element is destroyed by heat.
You will be able to protect it from breaking. [0007] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
You. FIGS. 1 and 2 show a vertical power unit having a self-overheating protection function.
-MOS transistors (hereinafter referred to as power MOS)
FIG. 1 is a schematic diagram of the semiconductor chip.
FIG. FIG. 2 is a sectional view taken along the line α-α in FIG.
You. Power that is an active element is provided on most of the entire semiconductor substrate A.
-Multiple MOS 13 connected in parallel to form a multi-source structure
Thus, a power region M is formed. The center of the semiconductor substrate A
Part, in other words, the part where heat is hardly dissipated,
Polycrystalline silicon diode as thermal element in easy-to-make part
A plurality of cards 15 are connected in series and controlled around
MOS transistor 14 as part, polycrystalline silicon
Resistors 16 and a constant voltage zener diode 17 are formed.
The control region C is formed as a body. Also, on the semiconductor substrate A
Voltage from outside (V_inBonding to apply)
A pad section B is formed. These power region M and control region
Each element in the region C and the bonding pad portion B are electrically connected to each other.
Connected. Next, referring to FIG. 2, the configuration will be described in detail.
I do. 1 is N⁺Shaped silicon substrate, 2 is N^-Shaped silico
The epitaxial layers 3, 3a are deeply diffused P-type extensions.
Spreading layer, 4 is P-type diffusion layer, 5, 5a, 5b and 5c are N⁺
Type diffusion layer, 11 is P⁺P-type diffusion layer 3
3a, N⁺The diffusion layers 5, 5a, 5b and 5c are respectively
At the same time, they are formed in the same diffusion process. Power MOS13
The MOS structure is composed of a silicon epitaxial layer 2 and a silicon substrate.
A drain D comprising a plate 1 and a drain electrode 12;
A polycrystalline silicon layer 7 formed via an oxide film 6
Gate G and power M on its surface via an interlayer insulating film 8
A source comprising an aluminum electrode 9 covering the entire surface of the OS 13
The operation is performed by applying a voltage to the gate G.
As a result, an N-type channel is formed
A current flows between the source S and the drain D. The diffusion layer 4 and
The diffusion layer 3 partially overlaps, and the diffusion layer 3 diffuses deeply.
This is for over-voltage protection, and
This is to set the power supply voltage. Next, horizontal MOS transistor
The MOS structure of the resistor 14 is formed of aluminum on the diffusion layers 5a and 5b.
Sources S1 and
Formed via drain D1 and gate oxide film 6a
And a gate G1 made of a polycrystalline silicon layer 7a.
The operation is performed when a voltage is applied to the gate G1.
An N-type channel is formed in the portion
A current flows between the terminals D1. Constant voltage zener diode 17
Is formed of the diffusion layer 5c and the diffusion layer 11 and has a surface
Aluminum electrodes 9c and 9d are formed respectively. Next
A part of the surface of the diffusion layer 3a is thermally oxidized to form an insulating film (SiO 2).
_Two10) is formed. And polycrystalline on the insulating film 10.
Silicon resistor 16 and polycrystalline silicon as thermal element
The diode 15 is formed. Polycrystalline silicon resistor 16
Is a polycrystalline silicon layer 7c, an interlayer insulating film 8 and aluminum
It is formed from the memory electrodes 9g and 9h. In addition, polycrystalline silicon
The diode 15 selectively expands the polysilicon layer 7b.
To form a PN junction, on which an interlayer insulating film 8 is partially interposed.
Then, aluminum electrodes 9e and 9f are formed. Stated above
Gate oxide films 6 and 6a, polycrystalline silicon
Layers 7, 7a, 7b, 7c, aluminum electrodes 9, 9
a, 9b, 9c, 9d, 9e, 9g, 9h are the same
It can be made in the same process. Each of the above elements is shown in FIG.
They are wired together as shown in the equivalent circuit diagram. Each element is shown in the top view of FIG.
It is arranged as shown. That is, the control area C has a horizontal shape.
MOS transistor 14, polycrystalline silicon diode 1
5, resistor 16C and constant voltage zener diode 17 are arranged
And an aluminum electrode 9 covering the surface of the power region.
And each of them is electrically connected via a connection path C1. Figure
Medium 20 is the same as 20 in FIG.
The external connection terminal of the nickel electrode 9 is shown. Where the constant voltage
External connection terminal electrically connected to the anode of Zener diode 17
The child 20 is fixed to the ground potential. Therefore, as shown in FIG.
The diffusion layer 1 of the constant voltage zener diode 17
The P-type diffusion layer 3a electrically connected to 1 is also fixed to the ground potential.
You. Also, one of the voltages applied to the bonding pad B
The part is connected to a power MOS via a resistor 16b disposed beside the part.
13 gate electrodes G1 or lateral MOS transistors
In addition to the 14 drains D1, the others are also arranged horizontally
The gate of the lateral MOS transistor 14 is connected via the resistor 16a and the like.
Join G1. Next, referring to the equivalent circuit diagram of FIG.
Explain the work. In the drawings, reference numerals are common to those in FIGS. 1 and 2.
is there. However, 16a, 16b and 16c are polycrystalline silicon
Resistance, R_LIs the external load resistance, V_DDIs an external power supply.
When the silicon substrate temperature is normal, that is, when the power MO
When the junction temperature in S13 is the normal temperature, the applied voltage V
_inThe power MOS 13 is turned on,
When the silicon substrate temperature is abnormally high,
When the junction temperature in S13 rises abnormally,
The forward voltage of the polycrystalline silicon diode 15 is constant.
Because of having a negative temperature coefficient, the voltage drops between terminals of the resistor 16c.
(Ie, the gate G of the lateral MOS transistor 14).
1-source S1). Above a certain voltage
Then, the lateral MOS transistor 14 is turned on.
The resistance of the resistor 16b is turned on to turn on the lateral MOS transistor 14.
If it is sufficiently larger than the resistance value, the potential of 22 in FIG.
V _{twenty two}And 23 potential V_{twenty three}The change in the junction temperature
As shown in the rough, the junction temperature is around 130 ° C (protection operation temperature
V)_{twenty two}Drops sharply to almost 0V, so the power MO
S13 is forcibly turned off, causing the junction temperature to rise.
Element destruction can be avoided. According to the structure of the above embodiment, the insulating film 10
By forming, individual elements can be trimmed,
And parasiticmotionSemiconductor device without
In addition, an abnormal rise in the junction temperature of the power MOS
The element is arranged in the central control region C where the temperature tends to be high.
This allows for more accurate detection, and the
It can be done in the same process, which makes it simple and leads to cost reduction.
And the resistance of the polysilicon resistor 16c on the insulating film.
Resistance value and number of polycrystalline silicon diodes 15 connected in series
, The protection operation temperature can be set arbitrarily. Polycrystalline silico
Since the resistance of the resistor 16c can be individually trimmed,
Excellent protection operation temperature can be precisely controlled after fabrication
effective. The silicon epitaxial layer 2 has a power
Since it forms part of the drain of MOS13, the power
The potential changes according to the operation state of the MOS 13,
Temperature of the polycrystalline silicon diode 15 formed thereon
May act to degrade the degree of detection accuracy
However, according to the present embodiment, in the silicon epitaxial layer 2
A P-type diffusion layer 3a is formed on the
To form the polycrystalline silicon diode 15
Can be eliminated. in this regard
More specifically, a structure without the P-type diffusion layer 3a is assumed.
Then, it is insulated according to the potential of the silicon epitaxial layer 2.
Film (SiO_TwoFilm, etc.) 10 is polarized and polycrystalline silicon die
Charges are induced on the surface of the diode 15 on the insulating film 10 side.
U. In the case of the present embodiment, for example, a silicon epitaxy
When the metal layer 2 has a high potential, the polysilicon diode 1
5, the impurity concentration at the PN junction changes.
The temperature characteristics at the forward voltage change and the temperature
Accuracy deteriorates. In extreme cases, polycrystalline silicon
An inversion layer is formed under the P-type region of the ion 15
It will behave like a parasitic MOS transistor
Thus, temperature detection is no longer possible. According to this embodiment, the polycrystalline silicon
Since the P-type diffusion layer 3a is formed under the
PN between the diffusion layer 3a and the silicon epitaxial layer 2
A junction is formed, and the power MOS 13
Since it can be electrically separated, polycrystalline silicon
The ion 15 is not affected by the drain potential.
In addition, the parasitic operation described above can be eliminated,
The effect is that high temperature detection can be performed.
You. The present invention is not limited to the above embodiment,
Various modifications are possible as follows. (1) All elements in the control region C are formed on the insulating film 10
Alternatively, as shown in the second embodiment of FIG.
A transistor 14a is formed on the insulating film 10 and a constant voltage zener is formed.
Only the diode 17 may be formed in the diffusion layer 3a.
Conversely, the lateral MOS transistor 14a is connected to the diffusion layer 3a.
Inside, a constant voltage zener diode 17 is formed on the insulating film 10.
May be implemented. In addition, diffused polycrystalline silicon resistor 16
It may be formed in the layer 3a. (2) FIG. 1 shows a third embodiment of FIG.
FIG. 7 which is an α-α sectional view and an equivalent circuit diagram thereof
As shown in FIG.
Register 24 (24a, 24b, 24c) and N-type cha
Forming MOS transistors 25 (25a, 25b)
To form a complementary MOS transistor (C-MOS)
22 potentials V_{twenty two}To a potential V of 26₂₆As well
No. Also, a P-type channel MOS transistor is formed on the insulating film 10.
And form an N-type channel 24 (24a, 24b, 24c).
Diffusion of MOS transistor 25 (25a, 25b)
A C-MOS configuration formed in the layer 3a may be used. According to this embodiment, C-MOSs are connected in multiple stages.
Therefore, the input / output characteristics are the product of the input / output characteristics of each stage.
And V in FIG._{twenty three}And V₂₆Graph of relationship between temperature and junction temperature
As shown in FIG.₂₆Can be lowered sharply.
Therefore, the power MOS 13 suddenly responds to the rise in the junction temperature.
It can be turned off steeply. In addition, connection of C-MOS
The number of stages is not limited.
Becomes steep. 6 and 7, the same components are used.
Use the same reference numerals as those in FIGS. 2 and 3, respectively.
are doing. (3) As a control area C or a temperature sensing element
The arrangement of the polycrystalline silicon diode 15 in the above embodiment is
Without being limited to only the central part of the semiconductor substrate A as in
For example, FIG. 9A shows a schematic plan view of a semiconductor device.
As shown in FIG.
No. According to the experimental results of the present inventors, the load of FIG.
When the power MOS 13 is forcibly heated by short-circuit
As shown in the diagram of the relationship between the number of
Failure rate is 100 when there is no overheat protection function (0 places)
%, That is, only at one location, that is, only at the center of the semiconductor substrate A.
When the polycrystalline silicon diode 15 is arranged in
The pass rate is greatly reduced, and the defective rate is 0 when 5 or more locations are arranged.
%. Turn off large power in a short time such as load short
If it is assumed that heat will be consumed,
Since the temperature distribution in the plate A tends to be non-uniform,
Device does not provide sufficient protection,
It is effective to place them in places. (4) The above embodiment uses the power MOS 13 and
The lateral MOS transistor 14 is shown by an N-type channel.
However, the present invention is not limited to this, and may be a P-type channel. This
In the above case, the diffusion corresponding to the code 3a in the above embodiment is performed.
The layers are of the N-type conductivity type, where the N-type
Channel MOS transistor 25 (25a, 25b)
And a P-type channel MOS transistor 24 (24
a, 24b, 24c) in the diffusion layer 3a.
Good. MOS transistors in polycrystalline semiconductors
Channel mobility within a single-crystal semiconductor
Although it is smaller than that of
And the N-channel MOS transistor is a P-channel M
Carriers are electrons compared to OS transistors
With high channel mobility, and C-MO
Mobility is easy to balance when S configuration
You. (5) The semiconductor element having an active function is a power
It is not limited to the MOS 13 but may be a bipolar transistor,
It may be a power IC or the like. Also, the thermal element is made of polycrystalline silicon.
The thermistor may be used instead of the recon diode 15.
Further, the configuration of the control unit is not limited to the configuration shown in the embodiment.
Of course things are. (6) The embodiment uses a polycrystalline silicon resistor 16 as a resistor.
However, a resistor such as tantalum nitride may be used.
You may.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a semiconductor device showing one embodiment of the present invention. FIG. 2 is a sectional view taken along line α-α in FIG. FIG. 3 is an equivalent circuit diagram of FIGS. 1 and 2; 4 is a graph showing the relationship between the junction temperature and the V ₂₂ and V _23. FIG. 5 is a sectional view showing a second embodiment. FIG. 6 is a sectional view taken along the line α-α in FIG. 1 as a third embodiment. FIG. 7 is an equivalent circuit diagram of FIG. 6; 8 is a graph showing the relationship between V ₂₃ and V ₂₆ of the embodiment junction temperature of FIG. FIG. 9 is a schematic plan view of a semiconductor device in which a plurality of polycrystalline silicon diodes are arranged. FIG. 10 is a diagram showing the relationship between the number of locations and the defect rate. FIG. 11 is a top view showing a specific arrangement of the embodiment in FIG. 1; [Description of Signs] 10 Insulating film (SiO ₂ film) 13 Vertical power MOS transistor 15 Polycrystalline silicon diode which is a thermal element

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 27/04

Claims (1)

(57) Claims: (1) In a semiconductor chip on which a semiconductor power element that generates high heat when a current flows in the conductive state is formed, a region of the semiconductor chip on which the semiconductor power element is laid out A semiconductor device disposed on a surface of a region inside the semiconductor device via an insulating film and detecting a heat generation state of the semiconductor power element. (2) The semiconductor power element includes a plurality of M connected in parallel.
2. The semiconductor device according to claim 1, wherein the region in which the thermosensitive element portion is disposed is located inside a region where the plurality of MOS transistor structures are disposed in the semiconductor chip. 13. The semiconductor device according to claim 1. (3) The semiconductor device according to claim 1 or 2, wherein the heat-sensitive element section is disposed substantially at a center of the semiconductor chip. ( 4 ) The heat-sensitive element portion is provided in front of the surface of the semiconductor chip.
The semiconductor device according to any one of the serial first term claims is a diode formed in polysilicon disposed over the insulating film to the third term. ( 5 ) The semiconductor device according to claim 4 , wherein the thermal element uses a negative temperature coefficient of a forward voltage of the polycrystalline silicon diode. (6) the thermosensitive element portion, the polycrystalline range of silicon diodes claims in which the plurality of series-connected fourth
Item 6. The semiconductor device according to item 5 or 5 . ( 7 ) The semiconductor device according to any one of claims 1 to 6, wherein the heat-sensitive element portions are arranged at a plurality of locations on the semiconductor chip. ( 9 ) The semiconductor device according to claim 7 , wherein the thermosensitive element section is arranged at five or more locations.