JP2701824B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2701824B2 JP2701824B2 JP8023918A JP2391896A JP2701824B2 JP 2701824 B2 JP2701824 B2 JP 2701824B2 JP 8023918 A JP8023918 A JP 8023918A JP 2391896 A JP2391896 A JP 2391896A JP 2701824 B2 JP2701824 B2 JP 2701824B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- polycrystalline silicon
- heat
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 20
- 230000006378 damage Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 48
- 238000009792 diffusion process Methods 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000001514 detection method Methods 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 101150090280 MOS1 gene Proteins 0.000 description 1
- 241001676573 Minium Species 0.000 description 1
- 101100401568 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MIC10 gene Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 244000045947 parasite Species 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体装置に係り、
特に温度検出機能を有する半導体装置に関するものであ
る。
【０００２】
【従来の技術】能動機能をもつ半導体素子の動作時の異
常な接合温度上昇による破壊をさける為に、従来では同
一半導体基板内に能動機能をもつ半導体素子と、例えば
感熱サイリスタ等の感熱素子を形成し、感熱素子により
半導体基板の温度を検出し、その検出信号により半導体
素子を制御して熱破壊しないように保護している。
【０００３】
【発明が解決しようとする課題】しかしながら、この従
来の温度検出機能では、半導体基板内で感熱素子近辺の
部分と、感熱素子とが電気的に絶縁されていないので寄
生動作が生じる等の問題がある。そこで本発明は上記の
点に鑑みて創案されたもので、半導体基板と感熱素子部
との間に絶縁膜を形成する事により、両者を電気的に完
全に分離し、温度検出機能を損なう事なく寄生動作がな
い半導体装置を提供する事を目的とする。
【０００４】
【課題を解決するための手段】上記の目的を達成する為
に本発明は、第１導電型の半導体層を有する半導体基板
と、前記半導体基板に形成され、前記半導体層をその構
成要素の一部として動作するものであって、導通状態の
際に電流が流れることで熱破壊に至るような高温に達す
るパワー素子と、 前記半導体層の一領域上に形成された
絶縁膜と、前記半導体基板の温度を検出するために、前
記絶縁膜上に形成された半導体より成る感熱素子部と、
前記感熱素子部の下方の前記半導体層の前記一領域に形
成され、前記半導体層との間でＰＮ接合を形成する第２
導電型の半導体領域とから構成される。
【０００５】
【作用及び発明の効果】そして本発明は前記の手段によ
り、半導体基板の温度が異常に上昇した時、すなわち半
導体素子の接合温度が異常に高くなった時には、この温
度上昇を感熱素子部で検出することができる。この際、
感熱素子部は絶縁膜上に形成されているので、半導体基
板内に形成されているパワー素子等から電気的な悪影響
を直接受けることがなくなる。
【０００６】ここで、感熱素子部はパワー素子の構成要
素である第１導電型の半導体層上に形成されているの
で、パワー素子の動作状態に応じて該半導体層の電位が
変化し、その電位により絶縁膜上の半導体に形成された
感熱素子部に悪影響を及ぼす可能性がある。即ち、半導
体層の電位に応じて絶縁膜が分極し、感熱素子部の半導
体の絶縁膜側表面に電荷が誘起され、実効的な半導体特
性が変わり、それにより温度検出精度が悪化する可能性
があるのである。
【０００７】しかしながら、本発明によると感熱素子部
は第２導電型の半導体領域上に絶縁膜を介して形成され
ているで、半導体層と半導体領域との間に形成されるＰ
Ｎ接合により半導体層の電位の影響をなくすことがで
き、寄生動作等の温度検出精度を悪化させる要因をなく
すことができるという効果がある。
【０００８】
【実施例】以下、本発明を図面に示す実施例により詳述
する。図１及び図２は自己過熱保護機能を有する縦形パ
ワーＭＯＳトランジスタ（以下、パワーＭＯＳという）
に応用した例であって、図１にその模式的平面図を示
す。引続き図２に図１中のα−α断面図を示す。半導体
基板Ａの全体の大部分に能動素子であるパワーＭＯＳ１
３が複数個並列接続してマルチソース構造となりパワー
領域Ｍを形成している。半導体基板Ａの中央部、言い換
えれば最も放熱しにくい部分で、温度が高く成り易い部
分に感熱素子としての多結晶シリコンダイオード１５を
複数個直列接続して形成し、その周辺に制御部としての
横形ＭＯＳトランジスタ１４、多結晶シリコン抵抗１
６、定電圧ツェナダイオード１７を形成し、全体として
制御領域Ｃを形成する。また、半導体基板Ａ上には外部
から電圧（Ｖｉｎ）を印加する為のボンディングパッド
部Ｂを形成する。これらパワー領域Ｍ及び制御領域Ｃの
各素子及びボンディングバッド部Ｂは電気的に互いに接
続される。
【０００９】次に図２において、その構成を詳しく説明
する。１はＮ+ 形のシリコン基板、２はＮ- 形のシリコ
ンエピタキシャル層、３及び３ａは深く拡散したＰ形拡
散層、４はＰ形拡散層、５，５ａ，５ｂ及び５ｃはＮ+
形拡散層、１１はＰ+ 形拡散層であり、Ｐ形拡散層３と
３ａ、Ｎ+ 形拡散層５，５ａ，５ｂ及び５ｃはそれぞれ
同時に同じ拡散行程で形成される。尚、Ｎ- 形シリコン
エピタキシャル層２が本発明が言うところの半導体層に
相当し、Ｐ形拡散層３ａが半導体領域に相当する。パワ
ーＭＯＳ１３のＭＯＳ構造は、シリコンピタキシャル層
２とシリコン基板１とドレイン電極１２から成るドレイ
ンＤと、ゲート酸化膜６を介して形成される多結晶シリ
コン層７から成るゲートＧと、その表面に層間絶縁膜８
を介しパワーＭＯＳ１３表面全体を覆うアルミニウム電
極９から成るソースＳとから構成され、その動作はゲー
トＧに電圧を印加すると図中ｃｈの部分にＮ形のチャネ
ルが形成されソースＳとドレインＤ間に電流が流れる。
尚、拡散層４と拡散層３が一部重なって、しかも拡散層
３が深く拡散しているのは過電圧保護の為であり、所定
のブレークダウン電圧に設定する為である。次に横形Ｍ
ＯＳトランジスタ１４のＭＯＳ構造は拡散層５ａ及び５
ｂ上のアルミニウム電極９ａ及び９ｂから成るそれぞれ
ソースＳ１及びドレインＤ１と、ゲート酸化膜６ａを介
して形成される多結晶シリコン層７ａから成るゲートＧ
１とから構成され、その動作はゲートＧ１に電圧がかか
ると図中ｃｈ１の部分にＮ形のチャネルが形成されソー
スＳ１とドレインＤ１間に電流が流れる。定電圧ツェナ
ダイオード１７は拡散層５ｃと拡散層１１とから形成さ
れ、その表面にそれぞれアルミニウム電極９ｃ及び９ｄ
を形成する。次に拡散層３ａ表面上の一部を熱酸化して
絶縁膜（ＳｉＯ2 膜等）１０を形成する。そして絶縁膜
１０上に多結晶シリコン抵抗１６と、感熱素子としての
多結晶シリコンダイオード１５を形成する。多結晶シリ
コン抵抗１６は、多結晶シリコン層７ｃと層間絶縁膜８
とアルミニウム電極９ｇ及び９ｈから形成される。ま
た、多結晶シリコンダイオード１５は多結晶シリコン層
７ｂを選択的拡散しＰＮ接合をつくり、その上に層間絶
縁膜８を一部介しアルミニウム電極９ｅ及び９ｆを形成
する。以上述べた実施例の構成でゲート酸化膜６と６
ａ、多結晶シリコン層７，７ａ，７ｂ，７ｃ，アルミニ
ウム電極９，９ａ，９ｂ，９ｃ，９ｄ，９ｅ，９ｇ，９
ｈはそれぞれ同じ工程で造る事が出来る。また前記の各
素子は、図３に示す等価回路図にあるように互いに配線
される。
【００１０】尚、各々の素子は例えば第１１図の上面図
に示すように配置される。すなわち、制御領域Ｃには横
形ＭＯＳトランジスタ１４、多結晶シリコンダイオード
１５、抵抗１６Ｃ，定電圧ツェナーダイオード１７が配
置しており、パワー領域の表面を覆うアルミニウム電極
９とその各々は接続路Ｃ１を経由して電気接続される。
図中、２０は図３中における２０と同じ点であり、アル
ミニウム電極９の外部接続端子を表わす。ここで、定電
圧ツェナダイオード１７の陽極に電気接続する外部接続
端子２０は接地電位に固定されている。従って、図２に
示されるように、定電圧ツェナダイオード１７の拡散層
１１に電気接続するＰ形拡散層３ａも接地電位に固定さ
れている。又、ボンディングパッド部Ｂに印加される電
圧の一部はその横に配置する抵抗１６ｂを介してパワー
ＭＯＳ１３のゲート電極Ｇ１あるいは横型ＭＯＳトラン
ジスタ１４のドレインＤ１に加わり、他は同じく横に配
置する抵抗１６ａ等を介して横形ＭＯＳトランジスタ１
４のゲートＧ１に加わる。
【００１１】次に、図３の等価回路図を用いて全体の動
作を説明する。図において符号は図１及び図２と共通で
ある。但し、１６ａ，１６ｂ，１６ｃは多結晶シリコン
抵抗、ＲL は外部の負荷抵抗、ＶDDは外部電源である。
シリコン基板温度が通常温度の時、すなわちパワーＭＯ
Ｓ１３の接合温度が通常温度の時には印加された電圧Ｖ
inによりパワーＭＯＳ１３はオン状態となっているが、
シリコン基板温度が異常に高い時、すなわちパワーＭＯ
Ｓ１３の接合温度が異常に上昇した時には感熱素子であ
る多結晶シリコンダイオード１５の順方向電圧は一定の
負の温度係数を持つ為に低下し、抵抗１６ｃの端子間電
圧（すなわち、横形ＭＯＳトランジスタ１４のゲートＧ
１−ソースＳ１間電圧）が上昇する。一定の電圧以上に
なると横形ＭＯＳトランジスタ１４がオン状態となる。
抵抗１６ｂ抵抗値を横形ＭＯＳトランジスタ１４のオン
抵抗値より十分に大きくしておけば、図４の２２の電位
Ｖ 22及び２３の電位Ｖ23の接合温度による変化を表すグ
ラフに示すように接合温度１３０℃近辺（保護動作温
度）でＶ22はほぼ０Ｖまで急激に下がるのでパワーＭＯ
Ｓ１３は強制的にオフ状態となり、接合温度上昇による
素子の破壊をさける事が出来る。
【００１２】上記の実施例の構成によれば、絶縁膜１０
を形成する事により、個別素子のトリミングが可能な、
しかも寄生動物がない半導体装置を提供する事ができ、
またパワーＭＯＳ１３の接合温度の異常な上昇が、感熱
素子を温度の高く成り易い中央部の制御領域Ｃに配置す
るのでより正確に検出でき、また、製造工程が同時に同
じ工程で行えるので簡単となり、コストダウンにもつな
がり、さらに絶縁膜上の多結晶シリコン抵抗１６ｃの抵
抗値及び、多結晶シリコンダイオード１５の直列接続数
により保護動作温度を任意に設定出来る。多結晶シリコ
ン抵抗１６ｃの抵抗値を個別にトリミング出来る為、製
造後に保護動作温度を精密に制御出来る等という優れた
効果がある。
【００１３】又、シリコンエピタキシャル層２はパワー
ＭＯＳ１３のドレインの一部を構成しているのでパワー
ＭＯＳ１３の動作状態に応じてその電位が変化し、その
上に形成されている多結晶シリコンダイオード１５の温
度検出精度を悪化させるように作用する可能性がある
が、本実施例によると、シリコンエピタキシャル層２内
にＰ形拡散層３ａを形成し、その上に絶縁膜１０を介し
て多結晶シリコンダイオード１５を形成しているのでこ
のような不具合をなくすことができる。この点について
詳述すると、仮に、Ｐ形拡散層３ａがない構造を想定す
ると、シリコンエピタキシャル層２の電位に応じて絶縁
膜（ＳｉＯ2 膜等）１０が分極し、多結晶シリコンダイ
オード１５の絶縁膜１０側表面に電荷が誘起されてしま
う。本実施例の場合には、例えばシリコンエピタキシャ
ル層２が高電位になると、多結晶シリコンダイオード１
５のＰＮ接合部における不純物濃度が変化してしまい、
その順方向電圧における温度特性が変化してしまい温度
検出の精度が悪化してしまう。極端な場合、多結晶シリ
コンダイオード１５のＰ形領域下部に反転層が形成され
てしまいＭＯＳトランジスタのような寄生動作をしてし
まうので、もはや温度検出が不可能になる。
【００１４】本実施例によると、多結晶シリコンダイオ
ード１５下にＰ形拡散層３ａを形成しているので、Ｐ形
拡散層３ａとシリコンエピタキシャル層２との間にＰＮ
接合が形成され、パワーＭＯＳ１３のドレイン電位から
電気的に分離することができるので、多結晶シリコンダ
イオード１５はドレイン電位の影響を受けることがな
く、上述のような寄生動作をなくすことができ、より精
度が高い温度検出を行うことができるという効果があ
る。
【００１５】尚、本発明は上記の実施例に限定されず、
以下の如く種々変形可能である。
（１）制御領域Ｃの素子は全て絶縁膜１０上に形成して
もよく、図５の第２の実施例に示す様に横形ＭＯＳトラ
ンジスタ１４ａを絶縁膜１０上に形成し、定電圧ツェナ
ダイオード１７だけを拡散層３ａ内に形成してもよい。
また逆に、横形ＭＯＳトランジスタ１４ａを拡散層３ａ
内に、定電圧ツェナダイオード１７を絶縁膜１０上に形
成してもよい。この他に多結晶シリコン抵抗１６を拡散
層３ａ内に形成してもよい。
【００１６】（２）図６の第３の実施例としての図１に
おけるα−α断面図、及びその等価回路図である図７に
示すように、絶縁膜１０上にＰ形チャネルＭＯＳトラン
ジスタ２４（２４ａ，２４ｂ，２４ｃ）、及びＮ形チャ
ネルＭＯＳトラジスタ２５（２５ａ，２５ｂ）を形成
し、相補形ＭＯＳトランジスタ（Ｃ−ＭＯＳ）を構成し
て２２の電位Ｖ22を増幅して２６の電位Ｖ26としてもよ
い。又、絶縁膜１０上にＰ形チャネルＭＯＳトランジス
タ２４（２４ａ、２４ｂ，２４ｃ）を形成し、Ｎ形チャ
ネルＭＯＳトランジスタ２５（２５ａ，２５ｂ）を拡散
層３ａ内に形成したＣ−ＭＯＳ構成でも良い。
【００１７】本例によるとＣ−ＭＯＳが多段に接続され
るので、その入出力特性は、各々の段の入出力特性の積
となり、図８のＶ23及びＶ26と接合温度の関係のグラフ
に示すように、２６の電位Ｖ26を急峻に下げる事がで
き、従って、パワーＭＯＳ１３を接合温度上昇に対し急
峻にオフ状態にする事ができる。尚、Ｃ−ＭＯＳの接続
段数は限定される事なく、その数が多い程、入出力特性
は急峻となる。また、図６、図７において同一構成要素
の符号は、それぞれ図２、図３のものと同じものを使用
している。
【００１８】（３）制御領域Ｃあるいは感温素子として
の多結晶シリコンダイオード１５の配置は、上記実施例
の如く半導体基板Ａの中央部だけに限定される事なく、
例えば半導体装置の模式的平面図を表わす図９（ａ）乃
至（ｅ）に示すように、複数箇所に対称に配置してもよ
い。尚、本発明者らの実験結果によると、図１０の負荷
ショートさせパワーＭＯＳ１３を強制的に発熱させた場
合の配置箇所数と不良率との関係図に示すように、自己
過熱保護機能がない（０箇所）場合には不良率は１００
％となり、１箇所、すなわち半導体基板Ａの中央部だけ
に多結晶シリコンダイオード１５を配置した場合には不
良率は大幅に低減し、５箇所以上配置すると不良率は０
％となる。負荷ショートの様な短時間に大きな電力を消
費し発熱するような場合を想定した場合には、半導体基
板Ａ内の温度分布が不均一になり易いため、１箇所の配
置では保護機能が不十分であるので、本例の如く、複数
箇所配置するのが有効である。
【００１９】（４）上記実施例はパワーＭＯＳ１３及び
横形ＭＯＳトランジスタ１４をＮ型のチャネルで示した
が、本発明はそれに限らずＰ形のチャネルでもよい。こ
の場合には上記実施例において符号３ａに相当する拡散
層はＮ形導電形となり、そこで、絶縁層１０上にＮ形チ
ャンネルＭＯＳトランジスタ２５（２５ａ，２５ｂ）を
形成し、Ｐ形チャンネルＭＯＳトランジスタ２４（２４
ａ，２４ｂ，２４ｃ）をその拡散層３ａ内に形成しても
よい。通常、多結晶半導体内におけるＭＯＳトランジス
タのチャネルモビリティは単結晶半導体内におけるもの
と比較して小さくなるが、上記のように形成する事によ
り、Ｎ形チャネルＭＯＳトランジスタはＰ形チャネルＭ
ＯＳトランジスタに比較してキャリアが電子であるため
にチャネルモビリティの高いものが作り易く、Ｃ−ＭＯ
Ｓ構成としたときモビリティのバランスがとり易くな
る。
【００２０】（５）能動機能をもつ半導体素子はパワー
ＭＯＳ１３に限定されず、バイポーラトランジスタ、パ
ワーＩＣ等であってもよい。また、感熱素子も多結晶シ
リコンダイオード１５に限らずサーミスタ等でもよい。
さらに制御部の構成は実施例に示す構成に限定されない
事はもちろんである。
（６）実施例は抵抗体として多結晶シリコン抵抗１６を
用いたが、それに限らず窒化タンタル等の抵抗体であっ
てもよい。DETAILED DESCRIPTION OF THE INVENTION
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device having a temperature detecting function.
You.
[0002]
2. Description of the Related Art Differences in the operation of semiconductor devices having active functions
Conventionally, to avoid destruction due to the
A semiconductor element having an active function in one semiconductor substrate, for example,
Form a heat-sensitive element such as a heat-sensitive thyristor, and
The temperature of the semiconductor substrate is detected and the semiconductor
The element is controlled to protect it from thermal destruction.
[0003]
[0005] However, this
With the conventional temperature detection function, the temperature near the thermal element in the semiconductor substrate
Part and the thermal element are not electrically insulated.
There are problems such as the occurrence of raw motion. Therefore, the present invention
Invented in view of the point, the semiconductor substrate and thermal element
By forming an insulating film between them,
It is completely separated and no parasitic operation occurs without impairing the temperature detection function.
It is an object to provide a semiconductor device.
[0004]
In order to achieve the above object,
The present invention provides a semiconductor substrate having a semiconductor layer of a first conductivity type.
And forming the semiconductor layer on the semiconductor substrate.
That operate as part of a component
When current flows, it reaches a high temperature that can lead to thermal destruction
Power elementWhen, SaidsemiconductorOn one area of the layerFormed in
In order to detect the temperature of the insulating film and the semiconductor substrate,
Thermosensitive element portion made of a semiconductor formed on the insulating filmWhen,
A shape is formed in the one region of the semiconductor layer below the heat-sensitive element portion.
And forming a PN junction with the semiconductor layer.
Conductive type semiconductor region andConsists of
[0005]
The present invention is based on the above-mentioned means.
When the temperature of the semiconductor substrate rises abnormally,
When the junction temperature of the conductor element becomes abnormally high,
The temperature rise can be detected by the heat-sensitive element section. On this occasion,
Since the thermal element is formed on an insulating film,
Electrical adverse effects from power elements etc. formed in the plate
Will not be directly received.
Here, the heat-sensitive element portion is a constituent element of the power element.
Formed on the first conductive type semiconductor layer
Then, the potential of the semiconductor layer changes depending on the operation state of the power element.
Change and the potential formed on the semiconductor on the insulating film
There is a possibility that the thermal element will be adversely affected. That is, semiconductor
The insulation film is polarized according to the potential of the body layer,
Charge is induced on the insulating film side surface of the
May change, thereby lowering the temperature detection accuracy
There is.
However, according to the present invention, the heat-sensitive element section
Is formed on the semiconductor region of the second conductivity type via an insulating film.
Is formed between the semiconductor layer and the semiconductor region.
The effect of the potential of the semiconductor layer can be eliminated by the N-junction.
Eliminates factors that degrade temperature detection accuracy, such as parasitic operation.
There is an effect that can be.
[0008]
BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I do. Figures 1 and 2 show a vertical package with a self-overheating protection function.
Power MOS transistor (hereinafter referred to as power MOS)
FIG. 1 shows a schematic plan view of the example.
You. FIG. 2 is a sectional view taken along line α-α in FIG. semiconductor
Power MOS1 which is an active element is provided on most of the entire substrate A.
3 is connected in parallel to form a multi-source structure with power
An area M is formed. Central part of semiconductor substrate A, in other words
In other words, it is the part where heat radiation is most difficult, and the part where the temperature tends to be high
Polycrystalline silicon diode 15 as a heat sensitive element
It is formed by connecting multiple units in series, and
Horizontal MOS transistor 14, polycrystalline silicon resistor 1
6. Form a constant voltage zener diode 17, and as a whole
The control area C is formed. In addition, on the semiconductor substrate A,
Pad for applying voltage (Vin) from
A part B is formed. These power region M and control region C
Each element and the bonding pad portion B are electrically connected to each other.
Continued.
Next, referring to FIG. 2, the structure will be described in detail.
I do. 1 is N+Shaped silicon substrate, 2 is N-Shaped silico
The epitaxial layers 3, 3a are deeply diffused P-type extensions.
Spreading layer, 4 is P-type diffusion layer, 5, 5a, 5b and 5c are N+
Type diffusion layer, 11 is P+P-type diffusion layer 3
3a, N+The diffusion layers 5, 5a, 5b and 5c are respectively
At the same time, they are formed in the same diffusion process. Note that N-Shaped silicon
The epitaxial layer 2 serves as a semiconductor layer according to the present invention.
The P-type diffusion layer 3a corresponds to a semiconductor region. Power
-The MOS structure of MOS13 is a silicon epitaxial layer
2 comprising a silicon substrate 1 and a drain electrode 12
D and a polycrystalline silicon formed through the gate oxide film 6.
A gate G composed of a capacitor layer 7 and an interlayer insulating film 8
Aluminum covering the entire surface of the power MOS 13 through the
And a source S consisting of poles 9, the operation of which is
When a voltage is applied to G, the N-type channel
And a current flows between the source S and the drain D.
Note that the diffusion layer 4 and the diffusion layer 3 partially overlap, and
3 is deeply diffused for overvoltage protection and
This is for setting the breakdown voltage. Next, horizontal M
The MOS structure of the OS transistor 14 includes diffusion layers 5a and 5a.
b consisting of aluminum electrodes 9a and 9b respectively
Through the source S1 and the drain D1, and through the gate oxide film 6a
G made of polycrystalline silicon layer 7a formed by
1, the operation of which determines whether a voltage is applied to the gate G1.
Then, an N-type channel is formed in the portion of ch1 in the figure,
A current flows between the drain S1 and the drain D1. Constant voltage zener
The diode 17 is formed by the diffusion layer 5c and the diffusion layer 11.
Aluminum electrodes 9c and 9d
To form Next, a part of the surface of the diffusion layer 3a is thermally oxidized.
Insulating film (SiOTwo10) is formed. And insulating film
10 and a polycrystalline silicon resistor 16 as a thermal element.
A polycrystalline silicon diode 15 is formed. Polycrystalline silicon
The capacitor 16 is composed of the polycrystalline silicon layer 7 c and the interlayer insulating film 8.
And aluminum electrodes 9g and 9h. Ma
The polycrystalline silicon diode 15 is a polycrystalline silicon layer.
7b is selectively diffused to form a PN junction, and an interlayer insulation is formed on it.
Aluminum electrodes 9e and 9f are formed partially through the edge film 8.
I do. With the configuration of the embodiment described above, the gate oxide films 6 and 6
a, polycrystalline silicon layers 7, 7a, 7b, 7c, aluminum
Electrodes 9, 9a, 9b, 9c, 9d, 9e, 9g, 9
h can be manufactured in the same process. Each of the above
The elements are wired together as shown in the equivalent circuit diagram in FIG.
Is done.
Each element is shown in, for example, the top view of FIG.
Are arranged as shown in FIG. That is, the control area C has a horizontal
MOS transistor 14, polycrystalline silicon diode
15, a resistor 16C and a constant voltage zener diode 17 are provided.
Aluminum electrode that covers the power area
9 and each of them are electrically connected via a connection path C1.
In the figure, reference numeral 20 denotes the same point as 20 in FIG.
The external connection terminal of the minium electrode 9 is shown. Where the constant
External connection electrically connected to the anode of the voltage Zener diode 17
The terminal 20 is fixed at the ground potential. Therefore, in FIG.
As shown, the diffusion layer of the constant voltage zener diode 17
11 is also fixed to the ground potential.
Have been. Also, the voltage applied to the bonding pad portion B is
Part of the pressure is supplied to the power via the resistor 16b placed next to it.
The gate electrode G1 of the MOS 13 or the lateral MOS transistor
In addition to the drain D1 of the transistor 14, the other
Horizontal MOS transistor 1 via a resistor 16a
4 gate G1.
Next, referring to the equivalent circuit diagram of FIG.
Explain the work. In the drawings, reference numerals are common to those in FIGS. 1 and 2.
is there. However, 16a, 16b and 16c are polycrystalline silicon
Resistance, RLIs the external load resistance, VDDIs an external power supply.
When the silicon substrate temperature is normal, that is, when the power MO
When the junction temperature in S13 is the normal temperature, the applied voltage V
inThe power MOS 13 is turned on,
When the silicon substrate temperature is abnormally high,
When the junction temperature in S13 rises abnormally,
The forward voltage of the polycrystalline silicon diode 15 is constant.
Because of having a negative temperature coefficient, the voltage drops between terminals of the resistor 16c.
(Ie, the gate G of the lateral MOS transistor 14).
1-source S1). Above a certain voltage
Then, the lateral MOS transistor 14 is turned on.
The resistance of the resistor 16b is turned on to turn on the lateral MOS transistor 14.
If it is sufficiently larger than the resistance value, the potential of 22 in FIG.
V twenty twoAnd 23 potential Vtwenty threeThe change in the junction temperature
As shown in the rough, the junction temperature is around 130 ° C (protection operation temperature
V)twenty twoDrops sharply to almost 0V, so the power MO
S13 is forcibly turned off, causing the junction temperature to rise.
Element destruction can be avoided.
According to the configuration of the above embodiment, the insulating film 10
By forming, individual elements can be trimmed,
Moreover, it is possible to provide a semiconductor device free of parasites,
In addition, an abnormal rise in the junction temperature of the power MOS
The element is arranged in the central control region C where the temperature tends to be high.
This allows for more accurate detection, and the
It can be done in the same process, which makes it simple and leads to cost reduction.
And the resistance of the polysilicon resistor 16c on the insulating film.
Resistance value and number of polycrystalline silicon diodes 15 connected in series
, The protection operation temperature can be set arbitrarily. Polycrystalline silico
Since the resistance of the resistor 16c can be individually trimmed,
Excellent protection operation temperature can be precisely controlled after fabrication
effective.
The silicon epitaxial layer 2 has a power
Since it forms part of the drain of MOS13, the power
The potential changes according to the operation state of the MOS 13,
Temperature of the polycrystalline silicon diode 15 formed thereon
May act to degrade the degree of detection accuracy
However, according to the present embodiment, in the silicon epitaxial layer 2
A P-type diffusion layer 3a is formed on the
To form the polycrystalline silicon diode 15
Can be eliminated. in this regard
More specifically, a structure without the P-type diffusion layer 3a is assumed.
Then, it is insulated according to the potential of the silicon epitaxial layer 2.
Film (SiOTwoFilm, etc.) 10 is polarized and polycrystalline silicon die
Charges are induced on the surface of the diode 15 on the insulating film 10 side.
U. In the case of the present embodiment, for example, a silicon epitaxy
When the metal layer 2 has a high potential, the polysilicon diode 1
5, the impurity concentration at the PN junction changes.
The temperature characteristics at the forward voltage change and the temperature
The accuracy of detection will deteriorate. In extreme cases, polycrystalline silicon
An inversion layer is formed below the P-type region of the diode 15.
It has a parasitic operation like a MOS transistor
Temperature detection is no longer possible.
According to this embodiment, the polycrystalline silicon
Since the P-type diffusion layer 3a is formed under the
PN between the diffusion layer 3a and the silicon epitaxial layer 2
A junction is formed, and the power MOS 13
Since it can be electrically separated, polycrystalline silicon
The ion 15 is not affected by the drain potential.
In addition, the parasitic operation described above can be eliminated,
The effect is that high temperature detection can be performed.
You.
The present invention is not limited to the above embodiment,
Various modifications are possible as follows.
(1) All elements in the control region C are formed on the insulating film 10
Alternatively, as shown in the second embodiment of FIG.
A transistor 14a is formed on the insulating film 10 and a constant voltage zener is formed.
Only the diode 17 may be formed in the diffusion layer 3a.
Conversely, the lateral MOS transistor 14a is connected to the diffusion layer 3a.
Inside, a constant voltage zener diode 17 is formed on the insulating film 10.
May be implemented. In addition, diffused polycrystalline silicon resistor 16
It may be formed in the layer 3a.
(2) FIG. 1 shows a third embodiment of FIG.
FIG. 7 which is an α-α sectional view and an equivalent circuit diagram thereof
As shown in FIG.
Register 24 (24a, 24b, 24c) and N-type cha
Forming MOS transistors 25 (25a, 25b)
To form a complementary MOS transistor (C-MOS)
22 potentials Vtwenty twoTo a potential V of 2626As well
No. Also, a P-type channel MOS transistor is formed on the insulating film 10.
And form an N-type channel 24 (24a, 24b, 24c).
Diffusion of MOS transistor 25 (25a, 25b)
A C-MOS configuration formed in the layer 3a may be used.
According to this embodiment, the C-MOSs are connected in multiple stages.
Therefore, the input / output characteristics are the product of the input / output characteristics of each stage.
And V in FIG.twenty threeAnd V26Graph of relationship between temperature and junction temperature
As shown in FIG.26Can be lowered sharply.
Therefore, the power MOS 13 suddenly responds to the rise in the junction temperature.
It can be turned off steeply. In addition, connection of C-MOS
The number of stages is not limited.
Becomes steep. 6 and 7, the same components are used.
Use the same reference numerals as those in FIGS. 2 and 3, respectively.
doing.
(3) As a control area C or a temperature sensing element
The arrangement of the polycrystalline silicon diode 15 in the above embodiment is
Without being limited to only the central part of the semiconductor substrate A as in
For example, FIG. 9A shows a schematic plan view of a semiconductor device.
As shown in FIG.
No. According to the experimental results of the present inventors, the load of FIG.
When the power MOS 13 is forcibly heated by short-circuit
As shown in the diagram of the relationship between the number of
Failure rate is 100 when there is no overheat protection function (0 places)
%, That is, only at one location, that is, only at the center of the semiconductor substrate A.
When the polycrystalline silicon diode 15 is arranged in
The pass rate is greatly reduced, and the defective rate is 0 when 5 or more locations are arranged.
%. Turn off large power in a short time such as load short
If it is assumed that heat will be consumed,
Since the temperature distribution in the plate A tends to be non-uniform,
Device does not provide sufficient protection,
It is effective to place them in places.
(4) The above embodiment uses the power MOS 13 and
The lateral MOS transistor 14 is shown by an N-type channel.
However, the present invention is not limited to this, and may be a P-type channel. This
In the above case, the diffusion corresponding to the code 3a in the above embodiment is performed.
The layers are of the N-type conductivity type, where the N-type
Channel MOS transistor 25 (25a, 25b)
And a P-type channel MOS transistor 24 (24
a, 24b, 24c) in the diffusion layer 3a.
Good. MOS transistors in polycrystalline semiconductors
Channel mobility within a single-crystal semiconductor
Although it is smaller than that of
And the N-channel MOS transistor is a P-channel M
Carriers are electrons compared to OS transistors
With high channel mobility, and C-MO
Mobility is easy to balance when S configuration
You.
(5) The semiconductor element having an active function is a power
It is not limited to the MOS 13 but may be a bipolar transistor,
It may be a power IC or the like. Also, the thermal element is made of polycrystalline silicon.
The thermistor may be used instead of the recon diode 15.
Further, the configuration of the control unit is not limited to the configuration shown in the embodiment.
Of course things are.
(6) The embodiment uses a polycrystalline silicon resistor 16 as a resistor.
However, a resistor such as tantalum nitride may be used.
You may.
【図面の簡単な説明】
【図１】本発明の一実施例を示す半導体装置の模式的平
面図である。
【図２】図１中のα−α断面図である。
【図３】図１及び図２の等価回路図である。
【図４】Ｖ22及びＶ23と接合温度の関係を示すグラフで
ある。
【図５】第２の実施例を示す断面図である。
【図６】第３の実施例としての図１中のα−α断面図で
ある。
【図７】図６の等価回路図である。
【図８】図６の実施例のＶ23及びＶ26と接合温度の関係
を示すグラフである。
【図９】多結晶シリコンダイオードを複数箇所配置した
半導体装置の模式的平面図である。
【図１０】配置箇所数と不良率との関係図である。
【図１１】図１における実施例の具体的な配置を示す上
面図である。
【符号の説明】
１０ 絶縁膜（ＳｉＯ2 膜）
１３ 縦形パワーＭＯＳトランジスタ
１４ 横形ＭＯＳトランジスタ
１５ 感熱素子である多結晶シリコンダイオード
１６ 多結晶シリコン抵抗
１７ 定電圧ツェナダイオードBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a semiconductor device showing one embodiment of the present invention. FIG. 2 is a sectional view taken along line α-α in FIG. FIG. 3 is an equivalent circuit diagram of FIGS. 1 and 2; 4 is a graph showing the relationship between the junction temperature and the V 22 and V 23. FIG. 5 is a sectional view showing a second embodiment. FIG. 6 is a sectional view taken along the line α-α in FIG. 1 as a third embodiment. FIG. 7 is an equivalent circuit diagram of FIG. 6; 8 is a graph showing the relationship between V 23 and V 26 of the embodiment junction temperature of FIG. FIG. 9 is a schematic plan view of a semiconductor device in which a plurality of polycrystalline silicon diodes are arranged. FIG. 10 is a diagram showing the relationship between the number of locations and the defect rate. FIG. 11 is a top view showing a specific arrangement of the embodiment in FIG. 1; [Description of Signs] 10 Insulating film (SiO 2 film) 13 Vertical power MOS transistor 14 Horizontal MOS transistor 15 Polycrystalline silicon diode which is a thermal element 16 Polycrystalline silicon resistor 17 Constant voltage Zener diode
Claims (1)
る半導体基板と、 前記半導体基板に形成され、前記半導体層をその構成要
素の一部として動作するものであって、導通状態の際に
電流が流れることで熱破壊に至るような高温に達するパ
ワー素子と、 前記 半導体層の一領域上に形成された絶縁膜と、 前記半導体基板の温度を検出するために、前記絶縁膜上
に形成された半導体より成る感熱素子部と、前記感熱素子部の下方の前記半導体層の前記一領域に形
成され、前記半導体層との間でＰＮ接合を形成する第２
導電型の半導体領域と、 を有する事を特徴とする半導体装置。 （２）前記感熱素子部は、多結晶シリコンダイオードで
ある特許請求の範囲第１項記載の半導体装置。（３）前記感熱素子部は、前記多結晶シリコンダイオー
ドの順方向電圧の負の温度係数を利用するものである特
許請求の範囲第２項記載の半導体装置。 （４）前記感熱素子部は、前記多結晶シリコンダイオー
ドを複数個直列接続したものである特許請求の範囲第２
項又は第３項記載の半導体装置。 （５） 前記半導体領域は、所定電位に固定されている特
許請求の範囲第１項乃至第４項のいずれかに記載の半導
体装置。（６） 前記第１導電型はＮ形であり、前記第２導電型は
Ｐ形であり、前記半導体領域は接地されている特許請求
の範囲第５項記載の半導体装置。（７） 前記感熱素子部は複数箇所に配置されている特許
請求の範囲第１項乃至第６項のいずれかに記載の半導体
装置。（８） 前記感熱素子部は、５箇所以上配置されている特
許請求の範囲第７項記載の半導体装置。(57) Claims: (1) A semiconductor substrate having a semiconductor layer of a first conductivity type, and formed on the semiconductor substrate, wherein the semiconductor layer operates as a part of its component, a power element reaches a high temperature such as thermal destruction by current flow during the conductive state, an insulating film formed on one region of the semiconductor layer, in order to detect the temperature of the semiconductor substrate, wherein A heat-sensitive element portion made of a semiconductor formed on an insulating film; and a heat-sensitive element formed in the one region of the semiconductor layer below the heat-sensitive element portion.
And forming a PN junction with the semiconductor layer.
A semiconductor device , comprising: a conductive semiconductor region . (2) The semiconductor device according to claim 1, wherein the heat-sensitive element section is a polycrystalline silicon diode. (3) The heat-sensitive element section includes the polycrystalline silicon diode.
Which utilizes the negative temperature coefficient of the forward voltage of the
The semiconductor device according to claim 2. (4) The heat-sensitive element section includes the polycrystalline silicon diode.
Claim 2 wherein a plurality of diodes are connected in series.
Item 4. The semiconductor device according to item 3 or 3. (5) The semiconductor device according to any one of claims 1 to 4 , wherein the semiconductor region is fixed at a predetermined potential. (6) The semiconductor device according to claim 5, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor region is grounded. (7) The semiconductor device according to any one of claims 1 to 6, wherein the thermosensitive element unit is arranged at a plurality of locations. (8) The semiconductor device according to claim 7 , wherein the thermosensitive element section is arranged at five or more locations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8023918A JP2701824B2 (en) | 1996-02-09 | 1996-02-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8023918A JP2701824B2 (en) | 1996-02-09 | 1996-02-09 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61250208A Division JPH0693485B2 (en) | 1985-11-29 | 1986-10-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236709A JPH08236709A (en) | 1996-09-13 |
| JP2701824B2 true JP2701824B2 (en) | 1998-01-21 |
Family
ID=12123891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8023918A Expired - Lifetime JP2701824B2 (en) | 1996-02-09 | 1996-02-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2701824B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160088807A (en) | 2015-01-16 | 2016-07-26 | 에스아이아이 세미컨덕터 가부시키가이샤 | Semiconductor device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4620889B2 (en) * | 2001-03-22 | 2011-01-26 | 三菱電機株式会社 | Power semiconductor device |
| WO2013015014A1 (en) * | 2011-07-22 | 2013-01-31 | 富士電機株式会社 | Super junction semiconductor device |
| JP6503202B2 (en) | 2015-03-12 | 2019-04-17 | エイブリック株式会社 | Semiconductor device |
| JP6872933B2 (en) * | 2017-03-01 | 2021-05-19 | 株式会社豊田中央研究所 | Semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5721849A (en) * | 1980-07-14 | 1982-02-04 | Fujitsu Ltd | Semiconductor integrated circuit |
| DE3138535A1 (en) * | 1981-09-28 | 1983-04-07 | Siemens AG, 1000 Berlin und 8000 München | TEMPERATURE SENSOR WITH A SEMICONDUCTOR BODY |
| JPS59163528A (en) * | 1983-03-09 | 1984-09-14 | Seiko Epson Corp | Temperature detecting circuit |
| JPS60131469A (en) * | 1983-12-20 | 1985-07-13 | Toshiba Corp | Semiconductor flow rate detecting element |
| JPS61208862A (en) * | 1985-03-14 | 1986-09-17 | Sanyo Electric Co Ltd | Semiconductor resistor |
-
1996
- 1996-02-09 JP JP8023918A patent/JP2701824B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160088807A (en) | 2015-01-16 | 2016-07-26 | 에스아이아이 세미컨덕터 가부시키가이샤 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08236709A (en) | 1996-09-13 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970902 |
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| EXPY | Cancellation because of completion of term |