WO2002015377A1 - Power supply unit - Google Patents

Power supply unit Download PDF

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Publication number
WO2002015377A1
WO2002015377A1 PCT/JP2000/005376 JP0005376W WO0215377A1 WO 2002015377 A1 WO2002015377 A1 WO 2002015377A1 JP 0005376 W JP0005376 W JP 0005376W WO 0215377 A1 WO0215377 A1 WO 0215377A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
mos transistor
output
voltage
rectifier circuit
Prior art date
Application number
PCT/JP2000/005376
Other languages
French (fr)
Japanese (ja)
Inventor
Ikuo Nishimoto
Tatsuya Ueno
Original Assignee
Yamatake Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamatake Corporation filed Critical Yamatake Corporation
Priority to PCT/JP2000/005376 priority Critical patent/WO2002015377A1/en
Priority to AU2000264741A priority patent/AU2000264741A1/en
Publication of WO2002015377A1 publication Critical patent/WO2002015377A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a power supply device using a MOS transistor as a rectifying element, which can reliably prevent a charge charged in a smoothing capacitor from being discharged through the MS transistor, for example, by electromagnetic induction coupling.
  • the present invention relates to a power supply device suitable for generating a predetermined internal power supply from power energy supplied via a coil.
  • spherical semiconductors have been proposed in which functional elements such as transistor sensors and semiconductor integrated circuits that perform predetermined processing functions are formed on the surface of a spherical semiconductor chip (pole) having a diameter of about 1 mm.
  • a spherical semiconductor of this type in which a coil (loop antenna) 2 serving as an antenna element is provided on the surface of a spherical semiconductor chip 1.
  • This spherical semiconductor is configured to operate by receiving power supply from an external device using electromagnetic induction coupling via the coil 2 and to transmit and receive information signals to and from the external device via the coil. You.
  • the integrated circuit formed on the semiconductor chip 1 includes, for example, a power supply unit 3 which receives a power (electromagnetic energy) supplied from the outside via a coil 2 and generates a predetermined internal power supply, as shown in FIG. It has a receiving unit 4 for receiving an information signal from the device via the coil 2 and a transmitting unit 5 for transmitting an information signal via the coil 2 to an external device.
  • the integrated circuit includes a device main body 6 including an arithmetic control unit and the like, and also includes a sensor unit 7 such as a temperature sensing element, a memory 8, and the like, and is configured to perform a predetermined function by the operation of the device main body 6.
  • the transmission and reception of the information signal via the coil 2 is performed by modulating the information signal using an electromagnetic induction magnetic field for transmitting electric power as a carrier.
  • the power supply unit 3 is provided with, for example, a rectifier circuit 10 for performing full-wave rectification of power energy supplied via the coil 2 as shown in FIG.
  • the rectifier circuit 10 is generally configured by bridge-connecting four MOS transistors 11, 12, 13, and 14 formed on the semiconductor chip 1. These MOS transistors 11, 12, 13, and 14 have their gates cross-connected to the coil 2 so as to be selectively (complementarily) driven to conduct.
  • the rectifier circuit 10 smoothes the full-wave rectified output (pulsating flow) via the capacitor 15 to generate a stable internal power supply (DC voltage).
  • the capacitor 15 is charged due to the element structure of the M ⁇ S transistor. It cannot be denied that the generated charge is discharged through the MOS transistor.
  • a MOS transistor generally has a device structure in which a source region and a drain region are symmetrically provided with a channel region formed under a gate electrode with an insulating layer interposed therebetween. Therefore, the direction of the current flowing through the channel region is determined according to the magnitude of the voltage applied to each of the source and the drain. In other words, the MOS transistor operates by exchanging the functions as the source and the drain according to the voltages applied to the source region and the drain region, respectively.
  • the rectifier circuit 10 configured as described above, when the full-wave rectified output of the rectifier circuit 10 is smoothed using the capacitor 15, the rectified circuit 10 is obtained by the smoothed output (DC voltage). Is specified at the DC output terminal. Then, the AC voltage applied from the coil 2 to the AC input terminal of the rectifier circuit 10 becomes the smoothed output
  • the power supply device in a power supply device that supplies power energy by electromagnetic inductive coupling via a coil 2 and rectifies this power energy (AC power) to generate an internal power supply, the power supply device is an internal power supply.
  • AC power AC power
  • the power supply device In the initial state before generating the voltage, there is a problem of where to obtain the drive power supply for the voltage comparison circuit. In other words, in order for the power supply to operate, an internal power supply for operating the voltage comparison circuit is required. Conversely, if the power supply does not operate, the internal power cannot be generated.
  • another power supply such as a battery for driving the voltage comparison circuit, but it is extremely difficult to incorporate the battery in the above-mentioned spherical semiconductor. Disclosure of the invention
  • An object of the present invention is to provide a power supply device in which a smoothing capacitor is provided on the output side of a rectifier circuit using a MOS transistor as a rectifier, to provide a stable and reliable power supply device.
  • An object of the present invention is to provide a power supply device that guarantees a rectifying operation, reliably prevents discharge from the capacitor through a MOS transistor, and can efficiently obtain a smoothed output.
  • An object of the present invention is to provide a power supply device suitable for generating a predetermined DC power supply from a power supply.
  • a power supply device includes a rectifying circuit that uses a MOS transistor as a rectifying element, connects its AC input terminal to the AC power supply, and rectifies AC power obtained from the AC power supply. And a capacitor connected to the DC output terminal of the rectifier circuit for smoothing the output from the rectifier circuit.
  • the input voltage obtained from the AC power supply and the output voltage obtained by smoothing the output of the rectifier circuit with the capacitor operate as the drive power supply, and are inverted according to the magnitude of the input voltage and the output voltage.
  • a control circuit that operates to forcibly turn off a MOS transistor that constitutes the rectifier circuit when the output voltage exceeds the input voltage.
  • control circuit operates as the drive power supply the input voltage obtained from the AC power supply and the output voltage obtained by smoothing the output of the rectifier circuit with the capacitor, and the magnitude of the input voltage and the output voltage Configuration ensures that even when the input voltage is started and the output voltage smoothed by the capacitor is not obtained, the operation can be reliably performed. It is characterized by doing so.
  • the rectifier circuit is composed of four MOS transistors connected in a bridge, and the two MOS transistors forming the opposite sides of the bridge are paired and gate-controlled according to the AC input voltage to control the MOS transistors. It is a full-wave rectifier circuit that conducts full-wave rectification of the AC power obtained from the AC power source by selectively conducting each pair.
  • the control circuit is provided for each pair of MOS transistors forming the opposite side of the bridge.
  • the control circuit includes a first MOS transistor that is diode-connected and operates using the input voltage as a driving power source, and a second MOS transistor that operates using the output voltage as a driving power source,
  • the gates of the first and second M ⁇ transistors are connected in common to A voltage is compared with the output voltage. Then, when the output voltage exceeds the input voltage, the resistance of the second MOS transistor is reduced, for example, the output obtained from the source of the second MOS transistor is greatly changed (inverted), and the rectification is performed. It is configured to forcibly shut off the MOS transistor that constitutes the circuit.
  • the control circuit is a four-terminal voltage comparison circuit having a first power supply terminal also serving as a first input terminal, a second power supply terminal also serving as a second input terminal, a common power supply terminal, and an output terminal. It is characterized by being realized as a circuit.
  • the plurality of MOS transistors constituting the full-wave rectifier circuit and the control circuit are simultaneously integrated on a semiconductor substrate.
  • the AC power supply is realized as a coil for inputting power energy supplied from an external device by electromagnetic inductive coupling.
  • the semiconductor substrate is realized as a spherical semiconductor having a coil serving as an AC power supply mounted on a surface thereof.
  • FIG. 1 is a schematic configuration diagram of a power supply device according to an embodiment of the present invention.
  • FIG. 2 is a timing diagram for explaining the operation of the power supply device shown in FIG. 1 when the power is turned on.
  • FIG. 3 is a timing chart for explaining the operation of the power supply device shown in FIG. 1 when there is a positive potential change at the time of power-on.
  • FIG. 4 is a timing chart for explaining a schematic operation of the power supply device shown in FIG. 1 in a steady state.
  • FIG. 5 is a diagram showing the relationship between a spherical semiconductor and a coil provided on the surface thereof.
  • FIG. 6 is a diagram showing a schematic configuration example of an integrated circuit provided in a spherical semiconductor.
  • FIG. 7 is a diagram showing a configuration example of a conventional power supply device. BEST MODE FOR CARRYING OUT THE INVENTION
  • the power supply device is incorporated in a spherical semiconductor, rectifies power energy supplied from an external device by electromagnetic induction coupling via a coil, and rectifies the power inside the spherical semiconductor.
  • a power supply device that generates power will be described as an example.
  • FIG. 1 is a schematic configuration diagram of a power supply device according to this embodiment, and reference numeral 20 denotes a coil as an AC power supply.
  • the coil 20 is positioned in a predetermined magnetic field formed by an external device (not shown), is electromagnetically inductively coupled to the magnetic field, and receives power energy given as electromagnetic waves from the external device and supplies the power energy to the power supply device.
  • an external device not shown
  • This power supply device includes, for example, a rectifier circuit 30 configured using a MOS transistor as a rectifier and rectifying the AC power supplied from the coil 20. Further, the power supply device includes a capacitor 31 connected to the DC output terminal of the rectifier circuit 30 for smoothing the rectified output (DC; pulsating current) from the rectifier circuit 30.
  • the rectifier circuit 30 rectifies the AC power, which is the power energy obtained from the coil 20, and smoothes the rectified output (pulsating voltage) through the capacitor 31, thereby obtaining the internal power of the predetermined DC voltage. A power supply is generated.
  • the rectifier circuit 30 is realized as a full-wave rectifier circuit in which four MOS transistors Q1, Q2, Q3, and Q4 simultaneously integrated on a semiconductor substrate are bridge-connected. More specifically, the rectifier circuit 30 includes a pair of a p-MOS transistor Q1 and an n-MOS transistor Q2 provided in series with the sources connected in common, and a ??-MOS transistor Q3.
  • a bridge circuit is constructed by connecting the set of n-MOS transistors Q 4 in parallel, and the parallel connection point (drain) is used as the DC output terminal, and the series connection point (source) of each set of MOS transistors is connected to the AC. It is configured as an input end.
  • the gates of the n-MOS transistors Q 2 and Q 4 are obtained from the coil 20.
  • the AC voltages to be supplied are complementary to each other.
  • These nM ⁇ S transistors Q 2 and Q 4 conduct (turn on) when a voltage higher than the threshold voltage V thn is applied between their gates and sources, as will be described later.
  • the circuit is turned off.
  • the P-MOS transistors Q 1 and Q 3 conduct (turn on) when a low voltage (high negative voltage) equal to or lower than the threshold voltage V thp is applied to the gate of the source.
  • the control circuits 40 and 50 described later are used. It is operated by gate control.
  • the rectifier circuit 30 configured by bridge-connecting the four MOS transistors Q 1, Q 2, Q 3, and Q 4 basically includes the AC power supplied from the coil 20. (In the state where the potential at point a is higher than the potential at point b in FIG. 1), the MOS transistors Q 1 and Q 4 conduct, and the current path (+) And outputs the power from the DC output terminal. In addition, the rectifier circuit 30 applies the MOS transistors Q 3 and Q 2 to the negative-phase component of the AC power supplied from the coil 20 (in FIG. 1, the state where the potential at the point b is higher than the potential at the point a).
  • a current path (1) is formed as shown by the dashed line in the figure, and the power is output from the DC output terminal.
  • the rectifier circuit 30 performs full-wave rectification on the AC power obtained from the coil 20, and charges the capacitor 31 with the full-wave rectified output.
  • the capacitor 31 generates a predetermined stabilized DC voltage (output voltage Vout) by smoothing the full-wave rectified output.
  • the control circuits 40 and 50 for controlling the gates of the p-M 0 S transistors Q 1 and Q 3 respectively include an input voltage Vin obtained from the coil 20 and a DC output of the rectification circuit 30.
  • the output voltage Vout smoothed by the capacitor 31 operates as a driving power source, and the input voltage Vin and the output voltage V It consists of a four-terminal voltage comparison circuit that inverts according to the magnitude of out.
  • control circuits 40 and 50 basically selectively turn on the P-MOS transistors Q1 and Q3 when the input voltage Vin is higher than the output voltage Vout, Conversely, when the output voltage Vout exceeds the input voltage Vin, in other words, when the AC input voltage Vin falls below the output voltage Vout, the respective pMOS transistors Q1 and Q3 are forcibly cut off (off) control. Play a role.
  • control circuit 40 (50) is connected to the first power supply terminal 41 (51), which is one end of the coil 20 and also serves as the first input terminal to which the input voltage Vin is applied, A second power supply terminal 42 (52) also serving as a second input terminal to which the voltage Vout is applied, a common power supply terminal 43 (53) connected to the ground line (negative side of the capacitor 31) of the semiconductor substrate, and p- Each is configured as a four-terminal voltage comparison circuit having output terminals 44 (54) for outputting gate control signals for the MOS transistors Q1 and Q3.
  • the control circuit 40 (50) responds to a comparison result (magnitude relation) between the input voltage Vin and the output voltage Vout applied to the first and second input terminals 41, 42 (51, 52), respectively.
  • the inversion operation is performed by changing the gate control signal (control voltage Vcont) output from the output terminal 44 (54).
  • the control voltage Vcont is applied to the gate of the p-MOS transistor Ql (Q3), and the operation of the p-MOS transistor Q1 (Q3) is controlled.
  • the control circuit 40 (50) includes a first P-MOS transistor Q11 (Q21) which is diode-connected and operates using the input voltage Vin as a driving power supply, and the output voltage Vout as a driving power supply.
  • a second p-MOS transistor, Q12 (Q22) is activated in parallel.
  • the first p-MOS transistor Q11 (Q21) includes a diode-connected n-MOS transistor Q13 (Q23) as a load connected in series to its drain.
  • the second p-MOS transistor Q 12 (Q22) has an n- A MOS transistor Q 14 (Q24) is provided as a load.
  • the first and second p-MOS transistors Ql1, Q12 have their gates connected in common, and the drains of the first p-MOS transistors Ql1 (Q21) Each gate receives the voltage generated at the gate and operates.
  • the n-MOS transistors Q13 and Q14 (Q23, Q24) provided as loads for each of the P-MOS transistors Q11 and Q12 (Q21.Q22) are connected to the gates in common to form a current mirror circuit. And each functions as a resistance element having a constant conduction (on) resistance.
  • the ⁇ -MOS transistors Q 13 and Q 14 are, for example, MOS transistors of the same specification having uniform characteristics, specifically, their conduction (on) resistances R 13 and R 14 are equal to each other.
  • the first P-MOS transistor Q 11 has, for example, a conduction (on) resistance R 11 of the n-MOS transistor Q 13 (Q 23) as its load.
  • the control circuit 40 (50) configured as described above basically receives the positive input from one terminal a (b) of the coil 20 to the first and second input terminals 41 and 42 (51, 52). It operates when the voltage Vin is applied and the output voltage Vout is applied from the capacitor 31.
  • the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q12 (Q22) is changed to the ground potential of the semiconductor substrate as described later. Conversely, when the output voltage Vout is higher than the input voltage Vin, the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q12 (Q22) is substantially set as the output voltage Vout. As described above, the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q 12 (Q22), which changes according to the magnitude relationship between the input voltage Vin and the output voltage Vout, is output to the output terminal 44 (54). It is used as a gate control signal output from.
  • control circuit 40 (50) configured as described above operates using the input voltage Vin and the output voltage Vout as its driving power supply, and in particular, in this control circuit 40 (50), Even when the supply of AC power from the coil 20 is started, that is, in the initial state where the capacitor 31 is not charged by the output of the rectifier circuit 30 and the output voltage Vout is not generated, it is ensured as described below. It is supposed to work.
  • the power energy (AC power) ) Supply shall be started.
  • the AC power supplied via the coil 20 is a positive-phase component, and the potential Va at the point a in the rectifier circuit 30 in FIG. 1 is gradually increased.
  • the input voltage Vin is given as a potential difference [Va-Vb] between the potential Va at the point a and the potential Vb at the point b.
  • the n-MOS transistor Q4 When the potential difference [Va-Vb] between the points a and b exceeds the operation threshold Vthn, the n-MOS transistor Q4 is turned on. On the other hand, when the potential at the point g in the initial stage is higher than the potential at the point b [Vb> Vg], the g-side of the n-MOS transistor Q4 having a lower potential functions as a source. Before the potential difference [Va-Vb] between the points a and b reaches the operation threshold Vthn, the potential difference [Va-Vg] between the points a and g exceeds the operation threshold Vthn. S transistor Q 4 conducts (ON).
  • n-MOS transistor Q4 conducts (turns on) with the rise in the potential at point a, As a result, the potential Vb at the point b and the potential Vg at the point g become substantially equal.
  • the potential Va at the point a is applied to the source of the P-MOS transistor Q1 immediately before or after the conduction (on) timing of the n_MOS transistor Q4.
  • the gate of the P-MOS transistor Q1 is initially kept at zero (0) potential, and the drain connected to point c on the output side is also kept at zero (0) potential. Therefore, the p-MOS transistor Q1 is turned on when the potential Va exceeds the operation threshold Vthp.
  • the P-MOS transistor Q1 and the n-MOS transistor Q4 which are the opposite sides of the ridge circuit in the rectifier circuit 30, are conductive (on) with respect to the positive phase component of the AC power supplied through the coil 20. ).
  • the P-MOS transistor Q 2 and the n-MOS transistor Q 3, which are the other side of the bridge circuit in the rectifier circuit 30, are applied with voltages of opposite polarities between the gate and the source. These p-MOS transistor Q2 and n-MOS transistor Q3 are kept off.
  • the potential V a at point a is applied to the electrode side connected to the first input terminal 41 of the first p-M ⁇ S transistor Ql 1 in the control circuit 40, and the potential V at point b is applied to the other side. b is added.
  • the point a side of the first p_M ⁇ S transistor Q11 functions as a source.
  • the potential Vb at the point b is applied to the source of the nM ⁇ S transistor Q13 in accordance with the ON operation of the nM ⁇ S transistor Q4 described above.
  • the input voltage Vin given as the potential difference [Va-Vb] between the potential Va at the point a and the potential Vb at the point b is determined by the first P-MOS transistor Q11 connected in series and its load.
  • MOS transistors Ql 1 and Q13 function as resistors having predetermined conduction (on) resistances R 11 and R 13 by their conduction, respectively, and a voltage applied between both ends (between points a and g). (Input voltage Vin) is divided by resistance.
  • the P-MOS transistor Q1 of the rectifier circuit 30 becomes conductive as described above. It is in a state just after being turned on, and the capacitor 31 is almost not charged. Therefore, only the voltage at point c generated at the source of the P-MOS transistor Q1 is applied to the drain of the second P-MOS transistor Q12 as its output voltage Vout. Since the current output from the point c is also used for charging the capacitor 31, the output voltage Vout is applied to the source of the P-MOS transistor Q1 at the start of the supply of the AC power (at the initial stage). It is lower than the input voltage Vin, that is, the potential Va at the point a. Therefore, the second p_MOS transistor Q12 rarely conducts simultaneously with the above-described first p-MOS transistor Q11.
  • the voltage Vc (output voltage Vout) at the point c applied to the source of the second P-MOS transistor Q12 is changed to the voltage at the point a applied to the source of the first p-MOS transistor Q11. Since the voltage is lower than the voltage Va (input voltage Vin) and the current flowing through the second p-MOS transistor Q12 is regulated by the above-described current mirror circuit, it is necessary to have a sufficiently large on-resistance R12. And As a result, the potential Vd at the point d, which is the source of the second P-MOS transistor Q12, is maintained at a value close to the potential Vb at the point b, and is kept low.
  • each of the above p-M ⁇ ON resistance of S transistor Q11, Q12 R11, R1 2 has a magnitude relationship of [R11 ⁇ R12].
  • the potential Vd at point d which is the common connection point on the side, decreases.
  • the potential Vd at the point d is set to be substantially equal to the potential Vb at the point b. Can be.
  • the control voltage Vcont applied to the gate of the P-MOS transistor Q1 of the rectifier circuit 30 is kept sufficiently lower than the input voltage Vin applied to its source to keep the P-MOS transistor Q1 on. Becomes possible. Note that the capacitor 31 is charged by the output of the rectifier circuit 30, and the input voltage Vin starts to decrease beyond its maximum amplitude and falls below the output voltage Vout defined by the charge charged in the capacitor 31.
  • the on-resistances R11 and R12 of the first and second P-MOS transistors Q11 and Q12 have a magnitude relationship of [R11> R12], and the first p-MOS transistor Q11
  • the potential Vd at point d which is the common connection point on the second P-MOS transistor Q12 side, is higher than the potential Ve at point e, which is the common connection point on the side.
  • the potential Vd at the point d on the source side of the second P-MOS transistor Q12 becomes substantially equal to the potential Vc (> Va) at the point c.
  • the control circuit 50 described above operates on the p-MOS transistor Q3 of the rectifier circuit 30 in the same manner as the control circuit 40 with respect to the negative phase component of the AC power. Accordingly, the discharge of the charge charged in the capacitor 31 through the p-MOS transistor Q2 is similarly prevented.
  • control circuit 40 The operation of the control circuit 40 described above is under ideal conditions in which the potential of each part of the power supply is set to 0 V as described above, but is actually caused by static electricity or the like. In some cases, the reference potential of the control circuit 40 has some potential, and the source potential Vd of the second pMOS transistor Q12 is displaced.
  • the operation of the control circuit 40 in such an initial state is verified, for example, as shown in FIG. 3, when the potential Vd at the point d has a positive potential, the P-MOS transistor of the rectifier circuit 30 A control voltage V cont having a positive value is applied to the gate of Q1 in advance.
  • Vd is set to a predetermined potential (for example, 0v).
  • control circuit 40 controls the control voltage Vcont applied to the gate of the p-MOS transistor Q1 of the rectifier circuit 30 , so that the P-MOS transistor Q1 is turned on at this point. Then, with the conduction of the p-MOS transistor Q1, the drain (c From this point, the output voltage Vout is applied to the control circuit 40, so that the second P-MOS transistor Q12 operates in response to the output voltage Vout, and the control circuit 40 operates.
  • the control circuit 40 when the power supply device is started in a state where a positive potential due to static electricity or the like is applied to the control circuit 40, the control signal Vcont output from the output terminal 44 is temporarily output during the initial operation of the control circuit 40. Since the voltage is returned to 0v, the p-MOS transistor Q1 in the rectifier circuit 30 can be reliably turned on. On the other hand, when the control circuit 40 is charged with a negative potential in the initial state, the control circuit 40 applies the gate of the p-MOS transistor Q 1 of the rectifier circuit 30 to the thin line V d in FIG. A negative potential as shown by is applied in advance as the control voltage V cont.
  • the potential at the point d gradually increases from the time when the P-MOS transistor Q1 is turned on, and the voltage Vc (output voltage Vout) at the point c also increases from the time when the P-MOS transistor Q1 is turned on as shown by a broken line in FIG. >.
  • the transistors Q1 and Q4 After the transistors Q1 and Q4 are turned on, they operate in the same manner as the operation under the ideal conditions described above. Therefore, even when the control circuit 40 is charged with a negative potential due to static electricity or the like, the control circuit 40 can be reliably operated as described above, and the rectifier circuit 30 can be started stably. It is possible to do.
  • the p_MOS transistor Q1 According to the power supply device including the control circuit 40 (50) for controlling the voltage applied to the gate of Q2, the internal power supply smoothed via the capacitor 31 is supplied at the start of the supply of AC power.
  • the control circuit 40 (50) can be reliably operated even at the initial time when no signal is generated, and its full-wave rectified output can be obtained via the rectifier circuit 30. Then, the capacitor 31 is gradually charged by the full-wave rectified output of the rectifier circuit 30, and the smoothed DC voltage can be stably generated through the capacitor 31.
  • the input voltage Vin provided as an AC voltage is lower than the output voltage Vout smoothed by the capacitor 31, and the voltage relationship applied to the source region and the drain region of the p_MOS transistor Q 1 (Q 3) Even if the function is reversed and the function is switched, the p-MOS transistor Q1 (Q3) is forcibly cut off (turned off), so that the p-MOS transistor Q1 (Q3) acts as a discharge path for the capacitor 31. None do. Therefore, the power energy supplied via the coil 20 can be efficiently rectified, and the internal power supply can be generated stably.
  • the control circuit 40 (50) for controlling the operation of the rectifier circuit 30 includes the input voltage Vin obtained from the coil 20 as described above. And the output voltage Vout, which is the DC output of the rectifier circuit 30 and is smoothed by the capacitor 31, operates as a driving power source, and has the magnitude of the input voltage Vin and the output voltage Vout. It is realized as a four-terminal voltage comparison circuit that inverts in response. Therefore, even in a state where no electric charge is stored in the capacitor 31, that is, even when the supply of the power energy (AC power) is started, the control circuit 40 (50) is reliably operated to start the operation of the power supply device. This has the advantage that the circuit configuration is relatively simple.
  • the present invention is not limited to the embodiment described above.
  • the control circuit 40 (50) is used to control the gate voltages of the P-MOS transistors Q1 and Q3 on the positive side, but the n_M ⁇ S transistor on the negative side is controlled.
  • the same configuration can be applied to the case where the gates of Q 2 and Q 4 are controlled.
  • all of the MOS transistors constituting the rectifier circuit 30 can be constituted by p-M ⁇ S transistors or n-MOS transistors. It also has the disadvantage that its rectification efficiency is reduced by half, but it goes without saying that it can be similarly applied to the case where a half-wave rectifier circuit is used instead of a full-wave rectifier circuit.
  • a power supply device that rectifies AC power through a rectifying circuit using a MOS transistor as a rectifying element and smoothes the rectified output through a capacitor, the AC input voltage And a DC output voltage as its driving source, and a control circuit for comparing the AC input voltage and the DC output voltage to gate-control the MOS transistor of the rectifier circuit, that is, a four-terminal voltage comparison circuit. Therefore, reverse discharge from the capacitor via the rectifier circuit is reliably prevented, and the internal power supply can be obtained stably.
  • the structure is simple, and excellent effects such as being suitable for being incorporated into a coupled spherical semiconductor that supplies electric power by electromagnetic induction coupling through a coil are obtained.

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Abstract

A power supply unit receives electric energy from an external device by induction coupling through coils (20) and generates predetermined DC power. The power supply unit comprises a rectifier circuit (30) for rectifying the AC power coupled to the AC input of a bridge rectifier consisting of four MOS transistors; and a capacitor (31) connected with the DC output of the rectifier circuit for smoothing the output from the rectifier circuit. The power supply unit further comprises control circuits (40, 50) that are driven by the input voltage Vin from the coil (AC power supply) and the output voltage Vout that is the rectifier output smoothed by the capacitor. The control circuits operate oppositely depending on the comparison between the input and output voltages; they forcedly turn off MOS transistors forming the rectifier if the output voltage exceeds the input voltage.

Description

明 細 書  Specification
電 源 装 置 技術分野 Power supply equipment technical field
本発明は、 MO Sトランジスタを整流素子として用いた電源装置であって、 平滑用のコンデンサに充電された電荷の上記 M〇 Sトランジスタを介する放電 を確実に防止することができ、 例えば電磁誘導結合によりコイルを介して給電 される電力エネルギから所定の内部電源を生成するに好適な電源装置に関する。 背景技術  The present invention relates to a power supply device using a MOS transistor as a rectifying element, which can reliably prevent a charge charged in a smoothing capacitor from being discharged through the MS transistor, for example, by electromagnetic induction coupling. The present invention relates to a power supply device suitable for generating a predetermined internal power supply from power energy supplied via a coil. Background art
近時、 直径 1 mm程度の球状の半導体チップ （ポール） の表面にトランジス タゃセンサ等の機能素子や、 所定の処理機能を果たす半導体集積回路を形成し た球状半導体が提唱されている。 この種の球状半導体には、 例えば図 5に示す ように球状の半導体チップ 1の表面にアンテナ素子として機能するコイル （ル ープアンテナ） 2を設けたものがある。 この球状半導体は、 コイル 2を介する 電磁誘導結合を利用して外部装置から電力供給を受けて作動し、 また上記コィ ルを介して外部装置との間での情報信号を送受するように構成される。  Recently, spherical semiconductors have been proposed in which functional elements such as transistor sensors and semiconductor integrated circuits that perform predetermined processing functions are formed on the surface of a spherical semiconductor chip (pole) having a diameter of about 1 mm. For example, as shown in FIG. 5, there is a spherical semiconductor of this type in which a coil (loop antenna) 2 serving as an antenna element is provided on the surface of a spherical semiconductor chip 1. This spherical semiconductor is configured to operate by receiving power supply from an external device using electromagnetic induction coupling via the coil 2 and to transmit and receive information signals to and from the external device via the coil. You.
ちなみに半導体チップ 1上に形成される集積回路は、 例えば図 6に示すよう にコイル 2を介して外部から給電される電力 （電磁エネルギ） を受けて所定の 内部電源を生成する電源部 3、 外部装置からの情報信号をコイル 2を介して受 信する受信部 4、 また外部装置に対して上記コイル 2を介して情報信号を送信 する送信部 5を備える。 更に集積回路は、 演算制御部等からなる装置本体 6を 備えると共に感温素子等のセンサ部 7やメモリ 8等を備え、 装置本体 6の動作 により所定の機能を果たすように構成される。  Incidentally, the integrated circuit formed on the semiconductor chip 1 includes, for example, a power supply unit 3 which receives a power (electromagnetic energy) supplied from the outside via a coil 2 and generates a predetermined internal power supply, as shown in FIG. It has a receiving unit 4 for receiving an information signal from the device via the coil 2 and a transmitting unit 5 for transmitting an information signal via the coil 2 to an external device. Further, the integrated circuit includes a device main body 6 including an arithmetic control unit and the like, and also includes a sensor unit 7 such as a temperature sensing element, a memory 8, and the like, and is configured to perform a predetermined function by the operation of the device main body 6.
尚、 コイル 2を介する情報信号の送受信は、 電力を伝送する電磁誘導磁場を キャリアとして情報信号を変調する等して行われる。 ところで電源部 3は、 例えば図 7に示すようにコイル 2を介して給電された 電力エネルギを全波整流する整流回路 1 0を備えて構成される。 尚、 上記整流 回路 1 0は一般的には半導体チップ 1上に形成される 4個の MO Sトランジス 夕 1 1， 1 2， 1 3， 1 4をブリッジ接続して構成される。 またこれらの MO S トランジスタ 1 1 , 1 2， 1 3 , 1 4は、 そのゲートを前記コイル 2に対して交 差接続されて選択的 （相補的） に導通駆動されるように構成される。 そしてこ の整流回路 1 0による全波整流出力 （脈流） をコンデンサ 1 5を介して平滑化 することで、 安定した内部電源 （直流電圧） を生成するものとなっている。 しかしながら上述した如く M〇Sトランジスタ 1 1 , 1 2 , 1 3 , 1 4をプリ ッジ接続して構成される整流回路 1 0においては、 M〇Sトランジスタの素子 構造上、 コンデンサ 1 5に充電された電荷が該 MO Sトランジスタを介して放 電することが否めない。 The transmission and reception of the information signal via the coil 2 is performed by modulating the information signal using an electromagnetic induction magnetic field for transmitting electric power as a carrier. By the way, the power supply unit 3 is provided with, for example, a rectifier circuit 10 for performing full-wave rectification of power energy supplied via the coil 2 as shown in FIG. Note that the rectifier circuit 10 is generally configured by bridge-connecting four MOS transistors 11, 12, 13, and 14 formed on the semiconductor chip 1. These MOS transistors 11, 12, 13, and 14 have their gates cross-connected to the coil 2 so as to be selectively (complementarily) driven to conduct. The rectifier circuit 10 smoothes the full-wave rectified output (pulsating flow) via the capacitor 15 to generate a stable internal power supply (DC voltage). However, as described above, in the rectifier circuit 10 configured by connecting the M〇S transistors 11 1, 12, 13, and 14 in a pledge connection, the capacitor 15 is charged due to the element structure of the M〇S transistor. It cannot be denied that the generated charge is discharged through the MOS transistor.
即ち、 MO Sトランジスタは、 一般的にはゲート電極下に絶縁層を介して形 成されるチャネル領域を挟んでソース領域とドレイン領域とを対称に設けた素 子構造を有する。 この為、 チャネル領域を介して流れる電流の向きは、 ソース およびドレインにそれぞれ加わる電圧の大きさに応じて決定される。 換言すれ ば MO Sトランジスタは、 ソース領域およびドレイン領域にそれぞれ加わる電 圧に応じてそのソースおよびドレインとしての機能を入れ替えて動作する。 ちなみに上述した如く構成された整流回路 1 0においては、 該整流回路 1 0 の全波整流出力をコンデンサ 1 5を用いて平滑化すると、 この平滑化出力 （直 流電圧） により該整流回路 1 0の直流出力端の電圧が規定される。 するとコィ ル 2から整流回路 1 0の交流入力端に与えられる交流電圧が上記平滑化出力 That is, a MOS transistor generally has a device structure in which a source region and a drain region are symmetrically provided with a channel region formed under a gate electrode with an insulating layer interposed therebetween. Therefore, the direction of the current flowing through the channel region is determined according to the magnitude of the voltage applied to each of the source and the drain. In other words, the MOS transistor operates by exchanging the functions as the source and the drain according to the voltages applied to the source region and the drain region, respectively. Incidentally, in the rectifier circuit 10 configured as described above, when the full-wave rectified output of the rectifier circuit 10 is smoothed using the capacitor 15, the rectified circuit 10 is obtained by the smoothed output (DC voltage). Is specified at the DC output terminal. Then, the AC voltage applied from the coil 2 to the AC input terminal of the rectifier circuit 10 becomes the smoothed output
(直流電圧） よりも低くなつた時点で、 導通状態にある MO Sトランジスタに おけるソース領域とドレイン領域との機能が入れ替わり、 コンデンサ 1 5に充 電された電荷が該 MO Sトランジスタを介して放電される。 これ故、 コイル 2 から得られる電力エネルギ （交流電力） を M〇Sトランジスタを用いて構築さ れた整流回路 1 0により全波整流するといえども、 その平滑化出力として十分 に高い直流電圧を得ることができなくなると言う不具合が生じる。 When the voltage falls below (DC voltage), the functions of the source region and the drain region in the conductive MOS transistor are switched, and the charge charged in the capacitor 15 is discharged through the MOS transistor. Is done. Therefore, the power energy (AC power) obtained from coil 2 is constructed using M〇S transistors. Even though full-wave rectification is performed by the rectified circuit 10, a sufficiently high DC voltage cannot be obtained as a smoothed output.
そこで従来、 例えば特開平 9 _ 1 3 1 0 6 4号公報に開示されるように電圧 比較回路を用いて整流回路 1 0の交流入力端に与えられる交流電圧 （入力電圧 V in) と、 この整流回路 1 0の全波整流出力であって、 コンデンサ 1 5を用い て平滑化した直流電圧 （出力電圧 Vout) とを比較し、 上記入力電圧 V inがそ の出力電圧 Voutよりも低くなつたとき、 MO Sトランジスタを強制的に遮断 (オフ） することでコンデンサ 1 5に充電された電荷の MO Sトランジスタを 介する放電を阻止することが提唱されている。  Therefore, conventionally, as disclosed in, for example, Japanese Patent Application Laid-Open No. 9-131064, an AC voltage (input voltage Vin) applied to the AC input terminal of the rectifier circuit 10 by using a voltage comparison circuit, Compared with the full-wave rectified output of the rectifier circuit 10 and the DC voltage (output voltage Vout) smoothed using the capacitor 15, the input voltage Vin was lower than the output voltage Vout. At this time, it has been proposed that the charge stored in the capacitor 15 is prevented from being discharged through the MOS transistor by forcibly turning off (turning off) the MOS transistor.
しかしながら球状半導体に見られるように、 コイル 2を介する電磁誘導結合 により電力エネルギを供給し、 この電力エネルギ （交流電力） を整流して内部 電源を生成する電源装置においては、 該電源装置が内部電源を生成するまでの 初期状態において、 上述した電圧比較回路の駆動電源をどこから得るかと言う 問題がある。 換言すれば電源装置が作動するには電圧比較回路を動作させるた めの内部電源が必要であり、 逆に電源装置が作動しなければ上記内部電源が生 成できないと言う矛盾が生じる。 このような不具合を解消するべく、 電圧比較 回路を駆動するための電池等の別電源を備えることが考えられるが、 上述した 球状半導体に電池を組み込むことは甚だ困難である。 発明の開示  However, as seen in a spherical semiconductor, in a power supply device that supplies power energy by electromagnetic inductive coupling via a coil 2 and rectifies this power energy (AC power) to generate an internal power supply, the power supply device is an internal power supply. In the initial state before generating the voltage, there is a problem of where to obtain the drive power supply for the voltage comparison circuit. In other words, in order for the power supply to operate, an internal power supply for operating the voltage comparison circuit is required. Conversely, if the power supply does not operate, the internal power cannot be generated. To solve such a problem, it is conceivable to provide another power supply such as a battery for driving the voltage comparison circuit, but it is extremely difficult to incorporate the battery in the above-mentioned spherical semiconductor. Disclosure of the invention
本発明は上述した不具合を解消するべくなされたもので、 その目的は、 MO Sトランジスタを整流素子として用いた整流回路の出力側に平滑用のコンデン サを設けた電源装置において、 安定で確実な整流動作を保証すると共に、 上記 コンデンサからの MO Sトランジスタを介する放電を確実に防止して、 その平 滑化出力を効率よく得ることのできる電源装置を提供することにある。  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described disadvantages. An object of the present invention is to provide a power supply device in which a smoothing capacitor is provided on the output side of a rectifier circuit using a MOS transistor as a rectifier, to provide a stable and reliable power supply device. An object of the present invention is to provide a power supply device that guarantees a rectifying operation, reliably prevents discharge from the capacitor through a MOS transistor, and can efficiently obtain a smoothed output.
特にコイルを介する電磁誘導結合により外部装置から給電される電力エネル ギから所定の直流電源を生成するに好適な電源装置を提供することにある。 このような目的を達成するべく本発明に係る電源装置は、 MO Sトランジス 夕を整流素子とし、 その交流入力端を交流電源に接続して該交流電源から得ら れる交流電力を整流する整流回路と、 この整流回路の直流出力端に接続されて 該整流回路からの出力を平滑化するコンデンサとを備え、 In particular, power energy supplied from an external device by electromagnetic induction coupling through a coil An object of the present invention is to provide a power supply device suitable for generating a predetermined DC power supply from a power supply. In order to achieve such an object, a power supply device according to the present invention includes a rectifying circuit that uses a MOS transistor as a rectifying element, connects its AC input terminal to the AC power supply, and rectifies AC power obtained from the AC power supply. And a capacitor connected to the DC output terminal of the rectifier circuit for smoothing the output from the rectifier circuit.
更に前記交流電源から得られる入力電圧、 および前記整流回路の出力を前記 コンデンサにて平滑化した出力電圧をその駆動電源として作動すると共に、 上 記入力電圧と出力電圧との大きさに応じて反転動作して前記出力電圧が入力電 圧を上回るとき前記整流回路を構成する MO Sトランジスタを強制的にオフ制 御する制御回路とを備えることを特徴とする。  Further, the input voltage obtained from the AC power supply and the output voltage obtained by smoothing the output of the rectifier circuit with the capacitor operate as the drive power supply, and are inverted according to the magnitude of the input voltage and the output voltage. A control circuit that operates to forcibly turn off a MOS transistor that constitutes the rectifier circuit when the output voltage exceeds the input voltage.
特に制御回路を、 前記交流電源から得られる入力電圧、 および前記整流回路 の出力を前記コンデンサにて平滑化した出力電圧をその駆動電源として作動す ると共に、 上記入力電圧と出力電圧との大きさに応じて反転動作するように構 成することで、 入力電圧の供給開始時であって、 コンデンサにて平滑化した出 力電圧が得られていない場合であっても、 その確実な動作を保証するようにし たことを特徴としている。  In particular, the control circuit operates as the drive power supply the input voltage obtained from the AC power supply and the output voltage obtained by smoothing the output of the rectifier circuit with the capacitor, and the magnitude of the input voltage and the output voltage Configuration ensures that even when the input voltage is started and the output voltage smoothed by the capacitor is not obtained, the operation can be reliably performed. It is characterized by doing so.
好ましくは前記整流回路は、 ブリッジ接続された 4個の MO Sトランジスタ からなり、 プリッジの対辺をなす 2個の MO Sトランジスタを対として交流入 力電圧に応じてゲート制御して上記 MO Sトランジスタの対毎に選択的に導通 させて前記交流電源から得られる交流電力を全波整流する全波整流回路からな る。  Preferably, the rectifier circuit is composed of four MOS transistors connected in a bridge, and the two MOS transistors forming the opposite sides of the bridge are paired and gate-controlled according to the AC input voltage to control the MOS transistors. It is a full-wave rectifier circuit that conducts full-wave rectification of the AC power obtained from the AC power source by selectively conducting each pair.
また前記制御回路は、 前記プリッジの対辺をなす MO Sトランジス夕の対に それぞれに対応して設けられる。 特にこの制御回路を、 ダイオード接続されて 前記入力電圧を駆動電源として作動する第 1の MO S卜ランジス夕と、 前記出 力電圧を駆動電源として作動する第 2の MO Sトランジスタとにより構成し、 上記第 1および第 2の M〇 トランジス夕の各ゲ一トを共通接続して前記入力 電圧と前記出力電圧とを比較動作させる。 そして前記入力電圧よりも出力電圧 が上回ったときに前記第 2の MO Sトランジスタを低抵抗化して、 例えば第 2 の MO Sトランジスタのソースから得られる出力を大きく変化させ （反転さ せ） 、 整流回路を構成する MO Sトランジスタを強制的に遮断するように構成 する。 The control circuit is provided for each pair of MOS transistors forming the opposite side of the bridge. In particular, the control circuit includes a first MOS transistor that is diode-connected and operates using the input voltage as a driving power source, and a second MOS transistor that operates using the output voltage as a driving power source, The gates of the first and second M〇 transistors are connected in common to A voltage is compared with the output voltage. Then, when the output voltage exceeds the input voltage, the resistance of the second MOS transistor is reduced, for example, the output obtained from the source of the second MOS transistor is greatly changed (inverted), and the rectification is performed. It is configured to forcibly shut off the MOS transistor that constitutes the circuit.
そして前記制御回路を、 第 1の入力端子を兼ねる第 1の電源端子、 第 2の入 力端子を兼ねる第 2の電源端子、 共通電源端子、 および出力端子を備えた 4端 子形の電圧比較回路として実現することを特徴とする。  The control circuit is a four-terminal voltage comparison circuit having a first power supply terminal also serving as a first input terminal, a second power supply terminal also serving as a second input terminal, a common power supply terminal, and an output terminal. It is characterized by being realized as a circuit.
ちなみに前記全波整流回路および制御回路をそれぞれ構成する複数の MO S トランジスタは、 半導体基板上に同時集積される。 また前記交流電源は、 電磁 誘導結合により外部装置から給電される電力エネルギを入力するコイルとして 実現される。 更に上記半導体基板は、 その表面に交流電源をなすコイルを実装 した球状の半導体として実現される。 図面の簡単な説明  Incidentally, the plurality of MOS transistors constituting the full-wave rectifier circuit and the control circuit are simultaneously integrated on a semiconductor substrate. The AC power supply is realized as a coil for inputting power energy supplied from an external device by electromagnetic inductive coupling. Further, the semiconductor substrate is realized as a spherical semiconductor having a coil serving as an AC power supply mounted on a surface thereof. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の一実施形態に係る電源装置の概略構成図。  FIG. 1 is a schematic configuration diagram of a power supply device according to an embodiment of the present invention.
図 2は、 図 1に示す電源装置における電源投入時の動作を説明するための夕 イミング図。  FIG. 2 is a timing diagram for explaining the operation of the power supply device shown in FIG. 1 when the power is turned on.
図 3は、 図 1に示す電源装置において、 電源投入時に正の電位変動があった 場合の動作を説明するためのタイミング図。  FIG. 3 is a timing chart for explaining the operation of the power supply device shown in FIG. 1 when there is a positive potential change at the time of power-on.
図 4は、 図 1に示す電源装置の定常状態における概略的な動作を説明するた めのタイミング図。  FIG. 4 is a timing chart for explaining a schematic operation of the power supply device shown in FIG. 1 in a steady state.
図 5は、 球状半導体とその表面に設けられたコイルとの関係を示す図。 図 6は、 球状半導体が備える集積回路の概略的な構成例を示す図。  FIG. 5 is a diagram showing the relationship between a spherical semiconductor and a coil provided on the surface thereof. FIG. 6 is a diagram showing a schematic configuration example of an integrated circuit provided in a spherical semiconductor.
図 7は、 従来の電源装置の構成例を示す図。 発明を実施するための最良の形態 FIG. 7 is a diagram showing a configuration example of a conventional power supply device. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図面を参照して本発明の一実施形態に係る電源装置について、 球状半 導体に組み込まれ、 コイルを介する電磁誘導結合により外部装置から供給され る電力エネルギを整流して上記球状半導体の内部電源を生成する電源装置を例 に説明する。  Hereinafter, a power supply device according to an embodiment of the present invention will be described with reference to the drawings. The power supply device is incorporated in a spherical semiconductor, rectifies power energy supplied from an external device by electromagnetic induction coupling via a coil, and rectifies the power inside the spherical semiconductor. A power supply device that generates power will be described as an example.
図 1はこの実施形態に係る電源装置の概略構成図を示しており、 2 0は交流 電源としてのコイルである。 このコイル 2 0は、 図示しない外部装置が形成す る所定の磁場中に位置付けられて該磁場に電磁誘導結合し、 上記外部装置から 電磁波として与えられる電力エネルギを受信して電源装置に供給する役割を担 ラ。  FIG. 1 is a schematic configuration diagram of a power supply device according to this embodiment, and reference numeral 20 denotes a coil as an AC power supply. The coil 20 is positioned in a predetermined magnetic field formed by an external device (not shown), is electromagnetically inductively coupled to the magnetic field, and receives power energy given as electromagnetic waves from the external device and supplies the power energy to the power supply device. Responsible.
この電源装置は、 例えば MO Sトランジスタを整流素子として用いて構成さ れて前記コイル 2 0から供給される交流電力を整流する整流回路 3 0を備える。 更に電源装置は、 上記整流回路 3 0の直流出力端に接続されて該整流回路 3 0 からの整流出力 （直流；脈流） を平滑化するコンデンサ 3 1を備える。 そして 前記コイル 2 0から得られる電力エネルギである交流電力を整流回路 3 0にて 整流し、 その整流出力 （脈流電圧） をコンデンサ 3 1を介して平滑化して、 所 定の直流電圧の内部電源を生成するものとなっている。  This power supply device includes, for example, a rectifier circuit 30 configured using a MOS transistor as a rectifier and rectifying the AC power supplied from the coil 20. Further, the power supply device includes a capacitor 31 connected to the DC output terminal of the rectifier circuit 30 for smoothing the rectified output (DC; pulsating current) from the rectifier circuit 30. The rectifier circuit 30 rectifies the AC power, which is the power energy obtained from the coil 20, and smoothes the rectified output (pulsating voltage) through the capacitor 31, thereby obtaining the internal power of the predetermined DC voltage. A power supply is generated.
ちなみに上記整流回路 3 0は、 半導体基板上に同時集積される 4個の MO S トランジス夕 Q 1 , Q 2， Q 3 , Q 4をブリツジ接続した全波整流回路として実 現される。 具体的には整流回路 3 0は、 ソースを共通接続して直列に設けられ た p - MO Sトランジスタ Q 1と n- MO Sトランジスタ Q 2との組、 および]? -MO Sトランジスタ Q 3と n-MO Sトランジスタ Q 4との組を並列接続して ブリッジ回路を構築し、 その並列接続点 （ドレイン） を直流出力端とし、 また 各組の MO Sトランジスタの直列接続点 （ソース） を交流入力端として構成さ れる。  Incidentally, the rectifier circuit 30 is realized as a full-wave rectifier circuit in which four MOS transistors Q1, Q2, Q3, and Q4 simultaneously integrated on a semiconductor substrate are bridge-connected. More specifically, the rectifier circuit 30 includes a pair of a p-MOS transistor Q1 and an n-MOS transistor Q2 provided in series with the sources connected in common, and a ??-MOS transistor Q3. A bridge circuit is constructed by connecting the set of n-MOS transistors Q 4 in parallel, and the parallel connection point (drain) is used as the DC output terminal, and the series connection point (source) of each set of MOS transistors is connected to the AC. It is configured as an input end.
尚、 n-MO Sトランジスタ Q 2， Q 4のゲートには、 前記コイル 2 0から得 られる交流電圧がそれぞれ相補的に入力されるようになっている。 そしてこれ らの n-M〇Sトランジスタ Q 2 , Q 4は、 後述するようにそのゲート ·ソース 間にその閾値電圧 V thn以上の高い電圧が加わったときに導通 （オン） 動作し、 ゲート ·ソース間に加わる電圧がその閾値電圧 V thn以下の低い場合には遮断 (オフ） 動作する。 また P - MO Sトランジスタ Q 1 , Q 3は、 逆にソースに対 してその閾値電圧 V thp以下の低い電圧 （負の高い電圧） がそのゲートに加わ つたときに導通 （オン） 動作する。 そしてゲートに加わる電圧がソースよりも その閾値電圧 V thp以上に高い場合 （負の低い電圧） には遮断 （オフ） 動作す るものであるが、 特にここでは後述する制御回路 4 0 , 5 0によりゲート制御 されて動作するようになっている。 The gates of the n-MOS transistors Q 2 and Q 4 are obtained from the coil 20. The AC voltages to be supplied are complementary to each other. These nM〇S transistors Q 2 and Q 4 conduct (turn on) when a voltage higher than the threshold voltage V thn is applied between their gates and sources, as will be described later. When the voltage applied to the power supply is lower than the threshold voltage V thn, the circuit is turned off. Conversely, the P-MOS transistors Q 1 and Q 3 conduct (turn on) when a low voltage (high negative voltage) equal to or lower than the threshold voltage V thp is applied to the gate of the source. When the voltage applied to the gate is higher than the source by more than the threshold voltage V thp (low negative voltage), the circuit is turned off (turned off). In particular, here, the control circuits 40 and 50 described later are used. It is operated by gate control.
しかして上述した如く 4個の MO Sトランジスタ Q 1 , Q 2 , Q 3， Q 4をブ リッジ接続して構成される整流回路 3 0は、 基本的にはコイル 2 0から供給さ れる交流電力の正相成分 （図 1において a点の電位が b点の電位よりも高い状 態） に対して MO Sトランジスタ Q 1 , Q 4を導通させ、 図中破線で示すよう な電流路 （+ ) を形成してその電力を直流出力端から出力する。 また上記整流 回路 3 0は、 コイル 2 0から供給される交流電力の逆相成分 （図 1において b 点の電位が a点の電位よりも高い状態） に対して MO Sトランジスタ Q 3， Q 2を導通させ、 図中一点鎖線で示すような電流路 （一） を形成してその電力を 直流出力端から出力する。 これによつて整流回路 3 0は、 コイル 2 0から得ら れる交流電力を全波整流し、 この全波整流出力によりコンデンサ 3 1を充電す る。 そしてコンデンサ 3 1は上記全波整流出力を平滑化することで所定の安定 化された直流電圧 （出力電圧 Vout) を生成する。  Thus, as described above, the rectifier circuit 30 configured by bridge-connecting the four MOS transistors Q 1, Q 2, Q 3, and Q 4 basically includes the AC power supplied from the coil 20. (In the state where the potential at point a is higher than the potential at point b in FIG. 1), the MOS transistors Q 1 and Q 4 conduct, and the current path (+) And outputs the power from the DC output terminal. In addition, the rectifier circuit 30 applies the MOS transistors Q 3 and Q 2 to the negative-phase component of the AC power supplied from the coil 20 (in FIG. 1, the state where the potential at the point b is higher than the potential at the point a). Is made conductive, a current path (1) is formed as shown by the dashed line in the figure, and the power is output from the DC output terminal. As a result, the rectifier circuit 30 performs full-wave rectification on the AC power obtained from the coil 20, and charges the capacitor 31 with the full-wave rectified output. The capacitor 31 generates a predetermined stabilized DC voltage (output voltage Vout) by smoothing the full-wave rectified output.
さて前記 p - M 0 Sトランジスタ Q 1， Q 3のゲートをそれぞれ制御する制御 回路 4 0 , 5 0は、 前記コイル 2 0から得られる入力電圧 V in、 および前記整 流回路 3 0の直流出力であって前記コンデンサ 3 1にて平滑化された出力電圧 Voutをその駆動電源として作動すると共に、 上記入力電圧 V i nと出力電圧 V ou tとの大きさに応じて反転動作する 4端子形の電圧比較回路からなる。 これ らの制御回路 40, 50は、 基本的には前記出力電圧 Voutよりも入力電圧 V in が上回るときに前記各 P-MOSトランジスタ Q1，Q 3を選択的に導通 （ォ ン） 駆動し、 また逆に前記出力電圧 Voutが入力電圧 Vinを上回るとき、 換言 すれば交流の入力電圧 Vinが出力電圧 Voutよりも下回ったときに前記各 p-M OSトランジスタ Q1，Q3を強制的に遮断 （オフ） 制御する役割を担う。 即ち、 制御回路 40 (50) は、 コイル 20の一端であって入力電圧 Vinが 加えられる第 1の入力端子を兼ねた第 1の電源端子 41 (51) 、 コンデンサ 31の正極側であって出力電圧 Voutが加えられる第 2の入力端子を兼ねた第 2の電源端子 42 (52) 、 半導体基板の接地ライン （コンデンサ 31の負極 側） に接続される共通電源端子 43 (53) 、 および p-MOSトランジスタ Q1，Q 3に対するゲート制御信号を出力する出力端子 44 (54) を備えた 4端子形の電圧比較回路としてそれぞれ構成される。 そして制御回路 40 (5 0 ) は、 上記第 1および第 2の入力端子 41, 42 (51, 52) にそれぞれ加 えられる入力電圧 Vinと出力電圧 Voutとの比較結果 （大小関係） に応じて、 その出力端子 44 (54) から出力するゲート制御信号 （制御電圧 Vcont) を 変化させることで反転動作する。 この制御電圧 Vcontが p-MOSトランジス タ Ql (Q 3) のゲートに印加され、 該 p-MOSトランジスタ Q 1 (Q 3) の動作が制御される。 The control circuits 40 and 50 for controlling the gates of the p-M 0 S transistors Q 1 and Q 3 respectively include an input voltage Vin obtained from the coil 20 and a DC output of the rectification circuit 30. The output voltage Vout smoothed by the capacitor 31 operates as a driving power source, and the input voltage Vin and the output voltage V It consists of a four-terminal voltage comparison circuit that inverts according to the magnitude of out. These control circuits 40 and 50 basically selectively turn on the P-MOS transistors Q1 and Q3 when the input voltage Vin is higher than the output voltage Vout, Conversely, when the output voltage Vout exceeds the input voltage Vin, in other words, when the AC input voltage Vin falls below the output voltage Vout, the respective pMOS transistors Q1 and Q3 are forcibly cut off (off) control. Play a role. That is, the control circuit 40 (50) is connected to the first power supply terminal 41 (51), which is one end of the coil 20 and also serves as the first input terminal to which the input voltage Vin is applied, A second power supply terminal 42 (52) also serving as a second input terminal to which the voltage Vout is applied, a common power supply terminal 43 (53) connected to the ground line (negative side of the capacitor 31) of the semiconductor substrate, and p- Each is configured as a four-terminal voltage comparison circuit having output terminals 44 (54) for outputting gate control signals for the MOS transistors Q1 and Q3. The control circuit 40 (50) responds to a comparison result (magnitude relation) between the input voltage Vin and the output voltage Vout applied to the first and second input terminals 41, 42 (51, 52), respectively. The inversion operation is performed by changing the gate control signal (control voltage Vcont) output from the output terminal 44 (54). The control voltage Vcont is applied to the gate of the p-MOS transistor Ql (Q3), and the operation of the p-MOS transistor Q1 (Q3) is controlled.
具体的には制御回路 40 (50) は、 ダイオード接続されて前記入力電圧 V inを駆動電源として作動する第 1の P- MOSトランジスタ Q 11 (Q 21) と、 前記出力電圧 Voutを駆動電源として作動する第 2の p-MOSトランジス 夕 Q12 (Q22) とを並列に備える。 上記第 1の p-MOSトランジスタ Q 11 (Q21) は、 ダイオード接続された n-MOSトランジスタ Q 13 (Q 23 ) を、 そのドレインに直列接続された負荷として備える。 また第 2の p - MOSトランジスタ Q 12 (Q22) は、 そのドレインに直列接続された n - MOSトランジスタ Q 14 (Q24) を負荷として備える。 Specifically, the control circuit 40 (50) includes a first P-MOS transistor Q11 (Q21) which is diode-connected and operates using the input voltage Vin as a driving power supply, and the output voltage Vout as a driving power supply. A second p-MOS transistor, Q12 (Q22), is activated in parallel. The first p-MOS transistor Q11 (Q21) includes a diode-connected n-MOS transistor Q13 (Q23) as a load connected in series to its drain. The second p-MOS transistor Q 12 (Q22) has an n- A MOS transistor Q 14 (Q24) is provided as a load.
しかして第 1および第 2の p-MOSトランジスタ Ql 1, Q 12 (Q 21 , Q22) は、 そのゲートを共通に接続してなり該第 1の p-MOSトランジス 夕 Ql l (Q21) のドレインに生じる電圧を、 各ゲートにそれぞれ受けて動 ' 作する。 また上記各 P- MOSトランジスタ Q 11， Q 12 (Q21.Q22) の負荷として設けられた n_MOSトランジスタ Q 13 , Q 14 (Q23, Q 2 4) は、 ゲートを共通に接続してカレントミラ一回路を形成しており、 それぞ れ一定の導通 （オン） 抵抗を持つ抵抗素子として機能する。  Thus, the first and second p-MOS transistors Ql1, Q12 (Q21, Q22) have their gates connected in common, and the drains of the first p-MOS transistors Ql1 (Q21) Each gate receives the voltage generated at the gate and operates. The n-MOS transistors Q13 and Q14 (Q23, Q24) provided as loads for each of the P-MOS transistors Q11 and Q12 (Q21.Q22) are connected to the gates in common to form a current mirror circuit. And each functions as a resistance element having a constant conduction (on) resistance.
尚、 η-MOSトランジスタ Q 13， Q 14 (Q 23， Q 24) は、 例えば特 性の揃った同一仕様の MOSトランジスタ、 具体的にはその導通 （オン） 抵抗 R 13, R 14が互いに等しい MOSトランジスタとして実現される。 また第 1の P-MOSトランジスタ Q 11 (Q21) は、 例えばその導通 （オン） 抵 抗 R 1 1が、 その負荷としての n- MOSトランジスタ Q 13 (Q 23) の導 通 （オン） 抵抗 R13と実質的に等しい特性を有するものとして実現される。 このように構成された制御回路 40 (50) は、 基本的には第 1および第 2 の入力端子 41， 42 (51, 52) に、 コイル 20の一方の端子 a (b) から 正の入力電圧 Vinが加えられ、 またコンデンサ 31から出力電圧 Voutが加え られたときに動作する。 そして出力電圧 Voutが入力電圧 Vinよりも小さいと きには、 後述するように第 2の p-MOSトランジスタ Q 12 (Q 22) のド レインに生じる電圧 （制御電圧 Vcont) を半導体基板の接地電位とし、 逆に出 力電圧 Voutが入力電圧 Vinよりも大きいときには、 第 2の p- MOSトランジ ス夕 Q 12 (Q22) のドレインに生じる電圧 （制御電圧 Vcont) を略出力電 圧 Voutとする。 このように入力電圧 Vinと出力電圧 Voutとの大小関係に応じ て変化する前記第 2の p-MOSトランジスタ Q 12 (Q22) のドレインに 生じる電圧 （制御電圧 Vcont) が、 出力端子 44 (54) から出力されるゲー ト制御信号として用いられる。 さて上述した如く構成される制御回路 40 (50) は、 前述したように入力 電圧 Vinと出力電圧 Voutとをその駆動電源として動作するものであるが、 特 にこの制御回路 40 (50) においてはコイル 20から交流電力の供給が開始 される時点、 即ち、 整流回路 30の出力によってコンデンサ 31が充電されて なく、 出力電圧 Voutが生成されていない初期状態においても、 以下に説明す るように確実に動作するようになっている。 Note that the η-MOS transistors Q 13 and Q 14 (Q 23 and Q 24) are, for example, MOS transistors of the same specification having uniform characteristics, specifically, their conduction (on) resistances R 13 and R 14 are equal to each other. Implemented as MOS transistors. The first P-MOS transistor Q 11 (Q 21) has, for example, a conduction (on) resistance R 11 of the n-MOS transistor Q 13 (Q 23) as its load. Is realized as having substantially the same characteristics as The control circuit 40 (50) configured as described above basically receives the positive input from one terminal a (b) of the coil 20 to the first and second input terminals 41 and 42 (51, 52). It operates when the voltage Vin is applied and the output voltage Vout is applied from the capacitor 31. When the output voltage Vout is smaller than the input voltage Vin, the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q12 (Q22) is changed to the ground potential of the semiconductor substrate as described later. Conversely, when the output voltage Vout is higher than the input voltage Vin, the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q12 (Q22) is substantially set as the output voltage Vout. As described above, the voltage (control voltage Vcont) generated at the drain of the second p-MOS transistor Q 12 (Q22), which changes according to the magnitude relationship between the input voltage Vin and the output voltage Vout, is output to the output terminal 44 (54). It is used as a gate control signal output from. As described above, the control circuit 40 (50) configured as described above operates using the input voltage Vin and the output voltage Vout as its driving power supply, and in particular, in this control circuit 40 (50), Even when the supply of AC power from the coil 20 is started, that is, in the initial state where the capacitor 31 is not charged by the output of the rectifier circuit 30 and the output voltage Vout is not generated, it is ensured as described below. It is supposed to work.
今、 電源装置の各部がその初期状態である零 （0) 電位に保たれており （V in=Vout=0 v=半導体基板の電位） 、 この状態においてコイル 20を介し て電力エネルギ （交流電力） の供給を開始するものとする。 そしてコイル 20 を介して供給される交流電力が正相成分であって、 図 1における整流回路 30 における a点の電位 V aが徐々に上昇するものとする。 この場合、 入力電圧 V inは、 a点の電位 V aと b点の電位 Vbとの電位差 [Va— Vb] として与え られる。  Now, each part of the power supply is maintained at its initial state of zero (0) potential (Vin = Vout = 0 v = potential of the semiconductor substrate). In this state, the power energy (AC power) ) Supply shall be started. The AC power supplied via the coil 20 is a positive-phase component, and the potential Va at the point a in the rectifier circuit 30 in FIG. 1 is gradually increased. In this case, the input voltage Vin is given as a potential difference [Va-Vb] between the potential Va at the point a and the potential Vb at the point b.
このときの整流回路 30の動作と制御回路 40の挙動について図 2を参照し て説明する。 コイル 20から与えられる入力電圧 Vinが徐々に上昇すると、 こ れに伴って a点の電位 V aが上昇し、 b点の電位 Vbが低下する。 すると整流 回路 30における n- MOSトランジスタ Q4のソース （b点側） に加わる電 圧に比較して、 そのゲート （a点側） に加わる電圧が徐々に高くなり、 そのゲ ート ·ソース間電圧が該 n- MOSトランジスタ Q 4の動作閾値 Vthnを越えた 時点で該 n- MOSトランジスタ Q4が導通 （オン） する。 この結果、 この n - MOSトランジスタ Q4を介して上記 b点が半導体基板の接地ラインである g 点につながることになる。  The operation of the rectifier circuit 30 and the behavior of the control circuit 40 at this time will be described with reference to FIG. When the input voltage Vin supplied from the coil 20 gradually increases, the potential Va at the point a increases and the potential Vb at the point b decreases accordingly. Then, as compared with the voltage applied to the source (point b side) of the n-MOS transistor Q4 in the rectifier circuit 30, the voltage applied to the gate (point a side) gradually increases, and the gate-source voltage Exceeds the operating threshold value Vthn of the n-MOS transistor Q4, the n-MOS transistor Q4 turns on. As a result, the point b is connected to the point g, which is the ground line of the semiconductor substrate, via the n-MOS transistor Q4.
尚、 コイル 20の一端が接続された b点は、 半導体基板の接地ラインである g点に対して、 通常、 フローティング状態にある。 従って仮に初期時における g点の電位が b点の電位と等しい場合 [Vb = Vg] には、 上記 a点と b点と の電位差 [Va— Vb] が動作閾値 Vthnに達した時点で該 n- MOS スタ Q4が導通 （オン） する。 これに対して初期時における g点の電位が b点 の電位よりも高い場合 [Vbく Vg] には、 n-MOSトランジスタ Q4の b 点に接続されたソース領域がそのままソースとして機能するので、 a点と b点 との電位差 [Va— Vb] が動作閾値 Vthnを越えた時点で該 n- MOSトラン ジス夕 Q 4が導通 （オン） する。 一方、 初期時における g点の電位が b点の電 位よりも高い場合 [Vb>Vg] には、 n-MOSトランジスタ Q4は、 電位 の低い g点側がソースとして機能する。 そして a点と b点との電位差 [Va— Vb] が動作閾値 Vthnとなる以前に、 a点と g点との電位差 [Va— Vg] が動作閾値 Vthnを越えるので、 これによつて n_M〇Sトランジスタ Q 4が導 通 （オン） する。 従って g点 （半導体基板の接地電位） に対して b点がフロー ティング状態にあるか否かに拘わりなく、 a点の電位の上昇に伴って n-MO Sトランジスタ Q4が導通 （オン） し、 これによつて b点の電位 Vbと g点の 電位 V gとが実質的に等しくなる。 The point b to which one end of the coil 20 is connected is normally in a floating state with respect to the point g, which is the ground line of the semiconductor substrate. Therefore, if the potential at the point g in the initial stage is equal to the potential at the point b [Vb = Vg], when the potential difference [Va−Vb] between the points a and b reaches the operation threshold Vthn, the n -MOS The star Q4 is turned on. On the other hand, when the potential at the point g in the initial stage is higher than the potential at the point b [Vb <Vg], the source region connected to the point b of the n-MOS transistor Q4 functions as the source as it is. When the potential difference [Va-Vb] between the points a and b exceeds the operation threshold Vthn, the n-MOS transistor Q4 is turned on. On the other hand, when the potential at the point g in the initial stage is higher than the potential at the point b [Vb> Vg], the g-side of the n-MOS transistor Q4 having a lower potential functions as a source. Before the potential difference [Va-Vb] between the points a and b reaches the operation threshold Vthn, the potential difference [Va-Vg] between the points a and g exceeds the operation threshold Vthn. S transistor Q 4 conducts (ON). Therefore, regardless of whether point b is in a floating state with respect to point g (ground potential of the semiconductor substrate), n-MOS transistor Q4 conducts (turns on) with the rise in the potential at point a, As a result, the potential Vb at the point b and the potential Vg at the point g become substantially equal.
一方、 この n_MOSトランジスタ Q4の導通 （オン） タイミングと相前後 して該 P- MOSトランジスタ Q 1のソースには a点の電位 Vaが加わる。 こ のとき P- MOSトランジスタ Q 1のゲートは、 その初期状態として零 （0) 電位に保たれており、 出力側である c点に接続されたドレインも零 （0) 電位 に保たれているので、 該 p- MOSトランジスタ Q 1は上記電位 V aがその動 作閾値 Vthpを越えた時点で導通 （オン） する。 この結果、 コイル 20を介し て供給される交流電力の正相成分に対して、 整流回路 30におけるプリッジ回 路の対辺をなす P- MOSトランジスタ Q 1と n- MOSトランジスタ Q4とが それぞれ導通 （オン） することになる。  On the other hand, the potential Va at the point a is applied to the source of the P-MOS transistor Q1 immediately before or after the conduction (on) timing of the n_MOS transistor Q4. At this time, the gate of the P-MOS transistor Q1 is initially kept at zero (0) potential, and the drain connected to point c on the output side is also kept at zero (0) potential. Therefore, the p-MOS transistor Q1 is turned on when the potential Va exceeds the operation threshold Vthp. As a result, the P-MOS transistor Q1 and the n-MOS transistor Q4, which are the opposite sides of the ridge circuit in the rectifier circuit 30, are conductive (on) with respect to the positive phase component of the AC power supplied through the coil 20. ).
この際、 整流回路 30におけるブリッジ回路の他方の対辺をなす P-MOS トランジスタ Q 2と n- MOSトランジスタ Q 3には、 そのゲート ·ソ一ス間 に逆極性の電圧が加わることになるので、 これらの p-MOSトランジスタ Q 2および n- MOSトランジスタ Q 3はそれぞれオフ状態に保たれる。 一方、 制御回路 40における第 1の p- M〇Sトランジスタ Ql 1の第 1の 入力端子 41に接続された電極側には a点の電位 V aが加わり、 その他方には b点の電位 V bが加わる。 このとき n- MOSトランジスタ Q4がォン状態で あって [Va>Vb] なる電位関係を有するので、 上記第 1の p_M〇Sトラ ンジス夕 Q 11の a点側がソースとして機能する。 また n-M〇Sトランジス 夕 Q13のソースには、 前述した n-M〇Sトランジスタ Q 4のオン動作に伴 い、 b点の電位 Vbが加えられる。 しかして上記 a点の電位 V aと b点の電位 Vbとの電位差 [Va— Vb] として与えられる入力電圧 V inが、 直列に接続 された第 1の P- MOSトランジスタ Q 11およびその負荷である n- MOSト ランジスタ Q 13の動作閾値、 即ち、 第 1の p - MOSトランジスタ Q 1 1の 動作閾値 Vthpと n- MOSトランジスタ Ql 3の動作閾値 Vthnとの和 [V thp + Vthn] を越えると、 この時点で上記第 1の p- MOSトランジスタ Q 1 1および n- MOSトランジスタ Q 13がそれぞれ導通動作する。 At this time, the P-MOS transistor Q 2 and the n-MOS transistor Q 3, which are the other side of the bridge circuit in the rectifier circuit 30, are applied with voltages of opposite polarities between the gate and the source. These p-MOS transistor Q2 and n-MOS transistor Q3 are kept off. On the other hand, the potential V a at point a is applied to the electrode side connected to the first input terminal 41 of the first p-M〇S transistor Ql 1 in the control circuit 40, and the potential V at point b is applied to the other side. b is added. At this time, since the n-MOS transistor Q4 is in the ON state and has a potential relationship of [Va> Vb], the point a side of the first p_M〇S transistor Q11 functions as a source. The potential Vb at the point b is applied to the source of the nM〇S transistor Q13 in accordance with the ON operation of the nM〇S transistor Q4 described above. Thus, the input voltage Vin given as the potential difference [Va-Vb] between the potential Va at the point a and the potential Vb at the point b is determined by the first P-MOS transistor Q11 connected in series and its load. It exceeds the operating threshold of a certain n-MOS transistor Q13, that is, the sum [Vthp + Vthn] of the operating threshold Vthp of the first p-MOS transistor Q11 and the operating threshold Vthn of the n-MOS transistor Ql3 At this point, the first p-MOS transistor Q11 and the n-MOS transistor Q13 each conduct.
これらの MOSトランジスタ Ql 1,Q13は、 その導通により所定の導通 (オン） 抵抗 R 11 , R 13を持つ抵抗体としてそれぞれ機能し、 その両端間 (a点と g点との間） に加わる電圧 （入力電圧 Vin) を抵抗分割する。 そして これらの MOSトランジスタ Ql 1,Q13により分割設定された e点の電位 V e、 具体的には上記オン抵抗 R 11, R 13が等しい場合には、 [V aZ 2] なる電位が前記第 2の p- MOSトランジスタ Q 12のゲートに、 また前 記 n- MOSトランジスタ Q 14のゲートにそれぞれ与えられる。  These MOS transistors Ql 1 and Q13 function as resistors having predetermined conduction (on) resistances R 11 and R 13 by their conduction, respectively, and a voltage applied between both ends (between points a and g). (Input voltage Vin) is divided by resistance. The potential V e at the point e divided by the MOS transistors Ql 1 and Q 13, specifically, when the on-resistances R 11 and R 13 are equal, the potential of [V aZ 2] becomes the second potential. To the gate of the p-MOS transistor Q12 and to the gate of the n-MOS transistor Q14.
この結果、 上記 n- MOSトランジスタ Q 13との間でカレントミラ一回路 を構成する n- MOSトランジスタ Ql 4は上記電圧をゲートに受けて導通動 作し、 所定の導通 （オン） 抵抗 R14を持つ抵抗体として機能する。 そして n - MOSトランジスタ Q 14の導通に伴い、 d点には g点の電位 Vg (=V b) が加わることになる。  As a result, the n-MOS transistor Ql4, which constitutes a current mirror circuit with the n-MOS transistor Q13, receives the above voltage at its gate and operates to have a predetermined conduction (on) resistance R14. Functions as a resistor. Then, with the conduction of the n-MOS transistor Q14, the potential Vg (= Vb) at the point g is applied to the point d.
また整流回路 30の P- MOSトランジスタ Q 1は、 前述したように導通 (オン） して間もない状態であり、 コンデンサ 31は殆ど充電されていない状 態である。 従って第 2の P- MOSトランジスタ Q 12のドレインには、 その 出力電圧 Voutとして P- MO Sトランジスタ Q 1のソースに生じた c点の電圧 が加わるだけである。 そしてこの c点から出力される電流はコンデンサ 31の 充電にも供されるので、 交流電力の供給開始時 （初期時） においては上記出力 電圧 Voutは P- MOSトランジスタ Q 1のソースに印加される入力電圧 Vin、 即ち、 a点の電位 Vaよりも低い。 これ故、 第 2の p_MOSトランジスタ Q 12は、 前述した第 1の p - MOSトランジスタ Ql 1と同時に導通動作する ことは殆どない。 また n- MOSトランジスタ Q 14は、 所定のオン抵抗を有 して導通しているので [Vd==Vg = Vb] なる関係となる。 またこのとき電 位差 [Va— Vb] がその動作閾値 [Vthp + Vthn] よりも大きいので、 整流 回路 30の p- M〇Sトランジスタ Qlはオン状態を維持する。 更には a点の 電位 V aの上昇に伴い、 p-MOSトランジスタ Q 1を介して得られる c点の 電位 Vcが上昇し、 第 2の p- MOSトランジスタ Q 12のゲ一ト ·ソース間 に電圧 [Vc— Ve] がその動作閾値 Vthpを越える時点で該第 2の： - MOS トランジスタ Q 12が導通する。 Also, the P-MOS transistor Q1 of the rectifier circuit 30 becomes conductive as described above. It is in a state just after being turned on, and the capacitor 31 is almost not charged. Therefore, only the voltage at point c generated at the source of the P-MOS transistor Q1 is applied to the drain of the second P-MOS transistor Q12 as its output voltage Vout. Since the current output from the point c is also used for charging the capacitor 31, the output voltage Vout is applied to the source of the P-MOS transistor Q1 at the start of the supply of the AC power (at the initial stage). It is lower than the input voltage Vin, that is, the potential Va at the point a. Therefore, the second p_MOS transistor Q12 rarely conducts simultaneously with the above-described first p-MOS transistor Q11. Further, the n-MOS transistor Q14 has a predetermined on-resistance and is conducting, so that the relation [Vd == Vg = Vb] holds. Further, at this time, since the potential difference [Va-Vb] is larger than the operation threshold [Vthp + Vthn], the p-M〇S transistor Ql of the rectifier circuit 30 maintains the ON state. Further, as the potential Va at the point a rises, the potential Vc at the point c obtained through the p-MOS transistor Q1 rises, and the potential between the gate and source of the second p-MOS transistor Q12 becomes When the voltage [Vc-Ve] exceeds its operating threshold Vthp, the second: the MOS transistor Q12 becomes conductive.
そしてこのとき、 第 2の P- MOSトランジスタ Q 12は、 そのソースに加 えられる c点の電圧 Vc (出力電圧 Vout) が、 第 1の p-MOSトランジスタ Q 11のソースに加えられる a点の電圧 Va (入力電圧 Vin) よりも低いこと、 また前述したカレントミラー回路により該第 2の p-MOSトランジスタ Q 1 2に流す電流が規定されることから、 十分に大きなオン抵抗 R 12を有するこ とになる。 この結果、 第 2の P- MOSトランジスタ Q 12のソースである d 点の電位 V dが b点の電位 V bに近い値に維持され、 低い電圧に抑えられる。 即ち、 第 1および第 2の P- MOSトランジスタ Q 11,Q 12にそれぞれ印 加される入力電圧 Vinと出力電圧 Voutが [Va>Vc] なる関係を有するこ とから、 上記各 p - M〇Sトランジスタ Q 11, Q 12のオン抵抗 R 11, R 1 2は [R11<R 12] なる大小関係となり、 第 1の p_M〇Sトランジスタ Q 11側の共通接続点である e点の電位 V eに比較して、 第 2の p- MOSト ランジス夕 Q12側の共通接続点である d点の電位 Vdが低くなる。 この際、 第 2の p- MOSトランジスタ Ql 2の動作特性を適正に設定しておけば、 上 記 d点の電位 V dを実質的に b点の電位 V bと等しくなるように設定すること ができる。 この結果、 整流回路 30の P- MOSトランジスタ Q 1のゲートに 加える制御電圧 Vcontを、 そのソースに加えられる入力電圧 Vinよりも十分に 低く抑えて該 P-MOSトランジスタ Q 1がオン状態を保つことが可能となる。 尚、 整流回路 30の出力によってコンデンサ 31が充電され、 入力電圧 Vin がその最大振幅を越えて低下し始めて上記コンデンサ 31に充電された電荷に より規定される出力電圧 Voutよりも低下すると、 第 1および第 2の p-MOS トランジスタ Ql 1, Q 12にそれぞれ印加される入力電圧 Vinと出力電圧 V outが [Va<Vc] なる関係となる。 すると第 2の p- MOSトランジスタ Q 12のソース ·ゲート間電圧 [Vc— Ve] は、 第 1の p- MOSトランジス 夕 Q 11のソース ·ゲート間電圧 [Va— Ve] よりも大きくなり、 この結果、 該第 1の p-MOSトランジスタ Ql 1のオン抵抗 Rl 1よりも第 2の p- M〇 Sトランジスタ Q 12のオン抵抗 R 12が小さくなる。 Then, at this time, the voltage Vc (output voltage Vout) at the point c applied to the source of the second P-MOS transistor Q12 is changed to the voltage at the point a applied to the source of the first p-MOS transistor Q11. Since the voltage is lower than the voltage Va (input voltage Vin) and the current flowing through the second p-MOS transistor Q12 is regulated by the above-described current mirror circuit, it is necessary to have a sufficiently large on-resistance R12. And As a result, the potential Vd at the point d, which is the source of the second P-MOS transistor Q12, is maintained at a value close to the potential Vb at the point b, and is kept low. That is, since the input voltage Vin and the output voltage Vout applied to the first and second P-MOS transistors Q11 and Q12 respectively have a relationship of [Va> Vc], each of the above p-M〇 ON resistance of S transistor Q11, Q12 R11, R1 2 has a magnitude relationship of [R11 <R12]. Compared with the potential Ve of the point e, which is the common connection point of the first p_M〇S transistor Q11, the second p-MOS transistor Q12 The potential Vd at point d, which is the common connection point on the side, decreases. At this time, if the operating characteristics of the second p-MOS transistor Ql2 are properly set, the potential Vd at the point d is set to be substantially equal to the potential Vb at the point b. Can be. As a result, the control voltage Vcont applied to the gate of the P-MOS transistor Q1 of the rectifier circuit 30 is kept sufficiently lower than the input voltage Vin applied to its source to keep the P-MOS transistor Q1 on. Becomes possible. Note that the capacitor 31 is charged by the output of the rectifier circuit 30, and the input voltage Vin starts to decrease beyond its maximum amplitude and falls below the output voltage Vout defined by the charge charged in the capacitor 31. The input voltage Vin and the output voltage Vout applied to the first and second p-MOS transistors Ql1 and Q12, respectively, have a relationship of [Va <Vc]. Then, the source-gate voltage [Vc-Ve] of the second p-MOS transistor Q12 becomes larger than the source-gate voltage [Va-Ve] of the first p-MOS transistor Q11. As a result, the on-resistance R12 of the second p-M〇S transistor Q12 is smaller than the on-resistance Rl1 of the first p-MOS transistor Ql1.
換言すれば第 1および第 2の P- MOSトランジスタ Q 11, Q 12のオン抵 抗 R 11, R 12は [R 11>R 12] なる大小関係となり、 第 1の p-MOS トランジス夕 Q 11側の共通接続点である e点の電位 V eに比較して、 第 2の P-MOSトランジスタ Q12側の共通接続点である d点の電位 Vdが高くな る。 そして第 2の P- MOSトランジスタ Q 12のソース側の前記 d点の電位 Vdが実質的に c点の電位 Vc (>Va) と等しくなる。  In other words, the on-resistances R11 and R12 of the first and second P-MOS transistors Q11 and Q12 have a magnitude relationship of [R11> R12], and the first p-MOS transistor Q11 The potential Vd at point d, which is the common connection point on the second P-MOS transistor Q12 side, is higher than the potential Ve at point e, which is the common connection point on the side. Then, the potential Vd at the point d on the source side of the second P-MOS transistor Q12 becomes substantially equal to the potential Vc (> Va) at the point c.
このとき、 整流回路 30の p- MOSトランジスタ Q1の c点側が a点より も高電位なので該 p- MOSトランジスタ Q 1の c点側がソースとして機能す る。 そして [Vd = Vc] なる関係が成立するので、 P-MOSトランジスタ Q 1のソース ·ゲート間電圧 [Vc- Vd] が零（0)となり、 該 p-M〇Sトラ ンジス夕 Q1が強制的に遮断 （オフ） 制御されることになる。 そしてコンデン サ 31に充電された電荷の上記 P- MOSトランジスタ Q 1を介する放電が阻 止されることになる。 At this time, the point c of the p-MOS transistor Q1 of the rectifier circuit 30 has a higher potential than the point a, so the point c of the p-MOS transistor Q1 functions as a source. Then, the relationship [Vd = Vc] holds, so the P-MOS transistor The source-gate voltage [Vc-Vd] of Q1 becomes zero (0), and the pM〇S transistor Q1 is forcibly turned off (off). Then, the discharge of the electric charge charged in the capacitor 31 via the P-MOS transistor Q1 is prevented.
尚、 交流電力の逆相成分に対しては、 整流回路 30の p- MOSトランジス 夕 Q 3に対して前述した制御回路 50が上記制御回路 40と同様に作用する。 従ってコンデンサ 31に充電された電荷の上記 p-MOSトランジスタ Q 2を 介する放電も同様に阻止される。  The control circuit 50 described above operates on the p-MOS transistor Q3 of the rectifier circuit 30 in the same manner as the control circuit 40 with respect to the negative phase component of the AC power. Accordingly, the discharge of the charge charged in the capacitor 31 through the p-MOS transistor Q2 is similarly prevented.
ところで上述した制御回路 40の動作は、 前述したように電源装置の各部の 電位が 0 Vに設定されている理想的な条件下のものであるが、 現実的には静電 気等に起因して制御回路 40の基準電位が何等かの電位を持ち、 第 2の p-M OSトランジスタ Q 12のソースの電位 Vdが変位している場合がある。 このような初期状態における制御回路 40の動作について検証すると、 例え ば図 3に示すように d点の電位 Vdが正の電位を有している場合には、 整流回 路 30の P- MOSトランジスタ Q 1のゲートに予め正の値を持つ制御電圧 V contが加えられることになる。 従って a点の電位 V aによって示される入力電 圧 V inが上昇し、 これによつて前述したように n-MOSトランジスタ Q 4が 導通したとしても、 これと相前後して P- MOSトランジスタ Q 1が導通する ことはない。 しかしながら入力電圧 Vinの上昇に伴って制御回路 40における 第 1の P-トランジスタ Q 11が導通し、 更に n- MOSトランジスタ Q 13お よび n_MOSトランジスタ Q 14が導通すると、 これによつて d点の電位 V dが予め規定された電位 （例えば 0v) に設定される。  The operation of the control circuit 40 described above is under ideal conditions in which the potential of each part of the power supply is set to 0 V as described above, but is actually caused by static electricity or the like. In some cases, the reference potential of the control circuit 40 has some potential, and the source potential Vd of the second pMOS transistor Q12 is displaced. When the operation of the control circuit 40 in such an initial state is verified, for example, as shown in FIG. 3, when the potential Vd at the point d has a positive potential, the P-MOS transistor of the rectifier circuit 30 A control voltage V cont having a positive value is applied to the gate of Q1 in advance. Therefore, the input voltage Vin indicated by the potential Va at the point a increases, and even if the n-MOS transistor Q4 becomes conductive as described above, the P-MOS transistor Q 1 never conducts. However, as the input voltage Vin increases, the first P-transistor Q11 in the control circuit 40 conducts, and further, the n-MOS transistor Q13 and the n_MOS transistor Q14 conduct, whereby the potential at the point d is established. Vd is set to a predetermined potential (for example, 0v).
するとこの制御回路 40の作動により、 整流回路 30の p-MOSトランジ スタ Q1のゲートに加えられる制御電圧 Vcontが低く抑えられるので、 該 P- MOSトランジスタ Q 1はこの時点で導通 （オン） する。 そして p-MOSト ランジスタ Q 1の導通に伴って該 P- MOSトランジスタ Q 1のドレイン （c 点） から制御回路 40に対して出力電圧 Voutが加えられることになるので、 この出力電圧 Voutを受けて第 2の P- MOSトランジスタ Q12が動作し、 制 御回路 40が作動することになる。 Then, by the operation of the control circuit 40, the control voltage Vcont applied to the gate of the p-MOS transistor Q1 of the rectifier circuit 30 is kept low, so that the P-MOS transistor Q1 is turned on at this point. Then, with the conduction of the p-MOS transistor Q1, the drain (c From this point, the output voltage Vout is applied to the control circuit 40, so that the second P-MOS transistor Q12 operates in response to the output voltage Vout, and the control circuit 40 operates.
従って制御回路 40に静電気等に起因する正の電位が加わっている状態にお いて電源装置を起動する場合、 該制御回路 40の初期動作においてその出力端 子 44から出力する制御信号 Vcontを一旦、 0vに引き戻すので、 整流回路 3 0における p-MO Sトランジスタ Q 1を確実にオン動作させることができる。 これに対して初期状態において制御回路 40に負の電位がチャージされてい る場合には、 該制御回路 40から整流回路 30の p-MOSトランジスタ Q 1 のゲ一トに、 図 2において細線 V dで示すような負の電位が予め制御電圧 V contとして加えられことになる。 このような状態で電源装置に対する交流電力 の供給が開始され、 a点の電位が僅かに上昇した時点で前述したように整流回 路 30における n- MOSトランジスタ Q 4がオン動作する。 また整流回路 3 0における p-MOSトランジスタ Q 1は、 a点と d点 （負の電位） との間に 加わる電圧 [Vin_Vd] がその動作閾値 Vthpを越えた時点で、 図 2に破線 で示すようにオン動作する。 つまり負の電位 Vdがチャージされている分、 p -MOSトランジスタ Q 1がオン時点が早くなる。 そして d点の電位は、 この P-MOSトランジスタ Q 1がオン時点から徐々に高まり、 また c点の電圧 V c (出力電圧 Vout) も図 2において破線で示すようにこのオン時点から上昇 ·ε>。  Therefore, when the power supply device is started in a state where a positive potential due to static electricity or the like is applied to the control circuit 40, the control signal Vcont output from the output terminal 44 is temporarily output during the initial operation of the control circuit 40. Since the voltage is returned to 0v, the p-MOS transistor Q1 in the rectifier circuit 30 can be reliably turned on. On the other hand, when the control circuit 40 is charged with a negative potential in the initial state, the control circuit 40 applies the gate of the p-MOS transistor Q 1 of the rectifier circuit 30 to the thin line V d in FIG. A negative potential as shown by is applied in advance as the control voltage V cont. In such a state, supply of AC power to the power supply device is started, and when the potential at the point a slightly increases, the n-MOS transistor Q4 in the rectifier circuit 30 is turned on as described above. When the voltage [Vin_Vd] applied between the point a and the point d (negative potential) exceeds the operating threshold Vthp, the p-MOS transistor Q1 in the rectifier circuit 30 is indicated by a broken line in FIG. On operation. In other words, the point at which the p-MOS transistor Q1 is turned on is earlier because the negative potential Vd is charged. Then, the potential at the point d gradually increases from the time when the P-MOS transistor Q1 is turned on, and the voltage Vc (output voltage Vout) at the point c also increases from the time when the P-MOS transistor Q1 is turned on as shown by a broken line in FIG. >.
そしてトランジスタ Q1，Q4がそれぞれォン動作した後には、 前述した理 想的な条件の下での動作と同様に作用することになる。 従って静電気等によつ て制御回路 40に負の電位がチャージされている場合であっても、 上述したよ うに該制御回路 40を確実に作動させることができ、 整流回路 30を安定に起 動することが可能となる。  After the transistors Q1 and Q4 are turned on, they operate in the same manner as the operation under the ideal conditions described above. Therefore, even when the control circuit 40 is charged with a negative potential due to static electricity or the like, the control circuit 40 can be reliably operated as described above, and the rectifier circuit 30 can be started stably. It is possible to do.
かくして上述した如く作動して整流回路 30の p_MOSトランジスタ Q 1, Q 2のゲートに加える電圧を制御する制御回路 40 (50) を備えて構成され る電源装置によれば、 交流電力の供給開始時であって、 コンデンサ 31を介し て平滑化された内部電源が生成されていない初期時においても上記制御回路 4 0 (50) を確実に作動させることができ、 整流回路 30を介してその全波整 流出力を得ることができる。 そして整流回路 30の全波整流出力にてコンデン サ 31を徐々に充電し、 該コンデンサ 31を介して平滑化された直流電圧を安 定に生成することが可能となる。 Thus, the p_MOS transistor Q1, According to the power supply device including the control circuit 40 (50) for controlling the voltage applied to the gate of Q2, the internal power supply smoothed via the capacitor 31 is supplied at the start of the supply of AC power. The control circuit 40 (50) can be reliably operated even at the initial time when no signal is generated, and its full-wave rectified output can be obtained via the rectifier circuit 30. Then, the capacitor 31 is gradually charged by the full-wave rectified output of the rectifier circuit 30, and the smoothed DC voltage can be stably generated through the capacitor 31.
そしてコンデンサ 31を介して平滑化された直流電圧を安定に得る状態に至 つた後には、 図 4にその概略的な動作タイミングを示すように、 入力電圧 V in がその出力電圧 Voutを上回ったときにだけ整流回路 30の p- MOSトランジ スタ Ql (Q3) を導通 （オン） 動作させ、 入力電圧 Vinがその出力電圧 V outを下回ったときには p - MOSトランジスタ Q 1 (Q3) を強制的に遮断 Then, after reaching a state in which a smoothed DC voltage is stably obtained via the capacitor 31, when the input voltage Vin exceeds the output voltage Vout as shown in FIG. Only when the input voltage Vin falls below its output voltage Vout, the p-MOS transistor Q1 (Q3) of the rectifier circuit 30 is turned on.
(オフ） 駆動することになる。 従って、 コンデンサ 31により平滑化された出 力電圧 Voutに比較して、 交流電圧として与えられる入力電圧 V inが低くなり、 p_MOSトランジスタ Q 1 (Q 3) のソース領域とドレイン領域とに加わる 電圧関係が逆転してその機能が入れ替わっても、 p-MOSトランジスタ Q1 (Q3) を強制的に遮断 （オフ） 駆動されるので、 該 p-MOSトランジスタ Q 1 (Q3) がコンデンサ 31に対する放電路として作用することがない。 従 つてコイル 20を介して給電される電力エネルギを効率的に整流して内部電源 を安定に生成することができると言う、 実用上多大なる効果が奏せられる。 特に従来提唱されている電圧比較回路を組み込んだ電源装置のように、 交流 電力の供給開始時において、 如何にして上記電圧比較回路の駆動電源を確保す るか等の問題を招くことがない。 従って電池等の別電源を準備する必要もなく、 例えば球状半導体の電源部として組み込むに好適である等の利点がある。 (OFF) Therefore, the input voltage Vin provided as an AC voltage is lower than the output voltage Vout smoothed by the capacitor 31, and the voltage relationship applied to the source region and the drain region of the p_MOS transistor Q 1 (Q 3) Even if the function is reversed and the function is switched, the p-MOS transistor Q1 (Q3) is forcibly cut off (turned off), so that the p-MOS transistor Q1 (Q3) acts as a discharge path for the capacitor 31. Never do. Therefore, the power energy supplied via the coil 20 can be efficiently rectified, and the internal power supply can be generated stably. In particular, unlike a power supply device incorporating a voltage comparison circuit that has been conventionally proposed, when starting to supply AC power, there is no problem of how to secure a drive power supply for the voltage comparison circuit. Therefore, there is no need to prepare a separate power supply such as a battery, and there are advantages such as being suitable for being incorporated as a power supply section of a spherical semiconductor.
また本発明に係る電源装置においては、 整流回路 30の作動を制御する制御 回路 40 (50) を、 前述した如くコイル 20から求められる入力電圧 Vin、 および前記整流回路 3 0の直流出力であって前記コンデンサ 3 1にて平滑化さ れた出力電圧 Voutをその駆動電源として作動すると共に、 上記入力電圧 V in と出力電圧 Vou tとの大きさに応じて反転動作する 4端子形の電圧比較回路と して実現している。 従ってコンデンサ 3 1に電荷が蓄積されていない状態、 つ まり電力エネルギ （交流電力） の供給開始時においても、 制御回路 4 0 ( 5 0 ) を確実に作動させて該電源装置の作動を立ち上げることができ、 その回路 構成も比較的簡単である等の利点がある。 In the power supply device according to the present invention, the control circuit 40 (50) for controlling the operation of the rectifier circuit 30 includes the input voltage Vin obtained from the coil 20 as described above. And the output voltage Vout, which is the DC output of the rectifier circuit 30 and is smoothed by the capacitor 31, operates as a driving power source, and has the magnitude of the input voltage Vin and the output voltage Vout. It is realized as a four-terminal voltage comparison circuit that inverts in response. Therefore, even in a state where no electric charge is stored in the capacitor 31, that is, even when the supply of the power energy (AC power) is started, the control circuit 40 (50) is reliably operated to start the operation of the power supply device. This has the advantage that the circuit configuration is relatively simple.
尚、 本発明は上述した実施形態に限定されるものではない。 実施形態におい ては、 制御回路 4 0 ( 5 0 ) を用いて正極側の P - MO Sトランジスタ Q 1， Q 3のゲート電圧を制御するように構成したが、 負極側の n_M〇Sトランジス タ Q 2 , Q 4をゲート制御する場合にも同様に構成することができる。 また整 流回路 3 0を構成する MO Sトランジスタの全てを p -M〇Sトランジスタ、 または n-MO Sトランジスタにて構成することも可能である。 またその整流 効率が半減すると言う欠点を有するが、 全波整流回路に代えて半波整流回路を 構成する場合にも同様に適用可能なことは言うまでもない。 更には球状半導体 に見られるように、 コイル 2 0を介する電磁誘導結合により電力エネルギを供 給するもののみならず、 一般的な交流電源から、 MO Sトランジスタを介して その整流出力を得る場合にも本発明を適用可能である。 その他、 本発明はその 要旨を逸脱しない範囲で種々変形して実施することができる。 産業上の利用可能性  Note that the present invention is not limited to the embodiment described above. In the embodiment, the control circuit 40 (50) is used to control the gate voltages of the P-MOS transistors Q1 and Q3 on the positive side, but the n_M〇S transistor on the negative side is controlled. The same configuration can be applied to the case where the gates of Q 2 and Q 4 are controlled. Further, all of the MOS transistors constituting the rectifier circuit 30 can be constituted by p-M〇S transistors or n-MOS transistors. It also has the disadvantage that its rectification efficiency is reduced by half, but it goes without saying that it can be similarly applied to the case where a half-wave rectifier circuit is used instead of a full-wave rectifier circuit. Furthermore, as seen in spherical semiconductors, not only those that supply power energy by electromagnetic induction coupling through coils 20 but also those that obtain their rectified output from a general AC power supply through a MOS transistor The present invention is also applicable. In addition, the present invention can be variously modified and implemented without departing from the gist thereof. Industrial applicability
以上説明したように本発明によれば、 MO Sトランジスタを整流素子として 用いた整流回路を介して交流電力を整流し、 その整流出力をコンデンサを介し て平滑化する電源装置において、 その交流入力電圧と直流出力電圧とをその駆 動源とし、 該交流入力電圧と直流出力電圧とを比較して前記整流回路の MO S トランジスタをゲート制御する制御回路、 即ち、 4端子形の電圧比較回路を備 えるので、 整流回路を介するコンデンサからの逆放電を確実に防止し、 その内 部電源を安定に得ることができる。 しかもその構成が簡単であり、 例えばコィ ルを介する電磁誘導結合により電力エネルギを供給する結合球状半導体に組み 込むに好適である等の優れた効果を奏する。 As described above, according to the present invention, in a power supply device that rectifies AC power through a rectifying circuit using a MOS transistor as a rectifying element and smoothes the rectified output through a capacitor, the AC input voltage And a DC output voltage as its driving source, and a control circuit for comparing the AC input voltage and the DC output voltage to gate-control the MOS transistor of the rectifier circuit, that is, a four-terminal voltage comparison circuit. Therefore, reverse discharge from the capacitor via the rectifier circuit is reliably prevented, and the internal power supply can be obtained stably. In addition, the structure is simple, and excellent effects such as being suitable for being incorporated into a coupled spherical semiconductor that supplies electric power by electromagnetic induction coupling through a coil are obtained.

Claims

請 求 の 範 囲 The scope of the claims
1. MOS卜ランジス夕を整流素子として、 その交流入力端を交流電源に接 続して該交流電源から得られる交流電力を整流する整流回路 （30) と、 この整流回路の直流出力端に接続されて該整流回路からの出力を平滑化する コンデンサ （31) と、  1. A rectifier circuit (30) that rectifies the AC power obtained from the AC power supply by connecting its AC input terminal to an AC power supply using a MOS transistor as a rectifier element, and is connected to the DC output terminal of this rectifier circuit. A capacitor (31) for smoothing the output from the rectifier circuit;
前記交流電源から得られる入力電圧、 および前記整流回路の出力を前記コン デンサにて平滑化した出力電圧をその駆動電源として作動すると共に、 上記入 力電圧と出力電圧との大きさに応じて反転動作して前記出力電圧が入力電圧を 上回るとき前記整流回路を構成する MOSトランジスタを強制的にオフ制御す る制御回路 （40, 50) と  The input voltage obtained from the AC power supply and the output voltage obtained by smoothing the output of the rectifier circuit with the capacitor operate as its drive power supply, and are inverted according to the magnitude of the input voltage and the output voltage. A control circuit (40, 50) for forcibly turning off the MOS transistor constituting the rectifier circuit when the output voltage exceeds the input voltage by operating;
を具備したことを特徴とする電源装置。 A power supply device comprising:
2. 前記整流回路は、 ブリッジ接続された 4個の MOSトランジスタ （Q1, Q2,Q3,Q4) からなり、 ブリッジの対辺をなす 2個の MOSトランジスタ を対として交流入力電圧に応じてゲート制御して上記 MO Sトランジスタの対 毎に選択的に導通させて前記交流電源から得られる交流電力を全波整流する全 波整流回路からなる請求項 1に記載の電源装置。  2. The rectifier circuit consists of four MOS transistors (Q1, Q2, Q3, Q4) connected in a bridge, and gate-controls two MOS transistors on the opposite sides of the bridge as a pair according to the AC input voltage. 2. The power supply device according to claim 1, comprising a full-wave rectifier circuit for selectively conducting each pair of the MOS transistors to perform full-wave rectification on AC power obtained from the AC power supply.
3. 前記制御回路は、 前記プリッジの対辺をなす MO トランジス夕の対に それぞれに対応して設けられるものである請求項 1に記載の電源装置。  3. The power supply device according to claim 1, wherein the control circuit is provided corresponding to each of a pair of MO transistors forming the opposite side of the bridge.
4. 前記制御回路は、 ダイオード接続されて前記入力電圧を駆動電源として 作動する第 1の M〇Sトランジスタ （Q1 1) と、 前記出力電圧を駆動電源と して作動する第 2の MOSトランジスタ （Q12) とを備え、  4. The control circuit includes a first MOS transistor (Q11) that is diode-connected and operates using the input voltage as a drive power supply, and a second MOS transistor (Q11) that operates using the output voltage as a drive power supply. Q12) and
上記第 1および第 2の M〇 Sトランジス夕の各ゲートを共通接続して前記入 力電圧と前記出力電圧とを比較動作し、 前記入力電圧よりも出力電圧が上回つ たときに前記第 2の MOSトランジスタを導通させてその出力を反転させるも のである請求項 1に記載の電源装置。  The gates of the first and second MS transistors are connected in common, and the input voltage and the output voltage are compared to perform an operation.When the output voltage exceeds the input voltage, the second 2. The power supply device according to claim 1, wherein the second MOS transistor is turned on to invert its output.
5. 前記制御回路は、 第 1の入力端子を兼ねる第 1の電源端子 （41) 、 第 2の入力端子を兼ねる第 2の電源端子 （4 2 ) 、 共通電源端子 （4 3 ) 、 およ び出力端子 （4 4 ) を備えた 4端子形の電圧比較回路を形成してなることを特 徵とする請求項 1または 4に記載の電源装置。 5. The control circuit includes: a first power supply terminal (41) also serving as a first input terminal; A four-terminal voltage comparison circuit including a second power terminal (42), a common power terminal (43), and an output terminal (44) also serving as the input terminal of (2). The power supply device according to claim 1 or 4, wherein
6 . 前記全波整流回路および制御回路をそれぞれ構成する複数の MO トラ ンジス夕は、 半導体基板上に同時集積されるものである請求項 1に記載の電源  6. The power supply according to claim 1, wherein the plurality of MO transistors constituting the full-wave rectifier circuit and the control circuit are simultaneously integrated on a semiconductor substrate.
7 . 前記交流電源は、 電磁誘導結合により外部装置から給電される電力 Xネ ルギを入力するコイルからなる請求項 1に記載の電源装置。 7. The power supply device according to claim 1, wherein the AC power supply includes a coil for inputting electric power X energy supplied from an external device by electromagnetic induction coupling.
8 . 前記半導体基板は、 その表面に交流電源をなすコイルを実装した球状の 半導体からなる請求項 6に記載の電源装置。  8. The power supply device according to claim 6, wherein the semiconductor substrate is made of a spherical semiconductor having a coil serving as an AC power supply mounted on a surface thereof.
PCT/JP2000/005376 2000-08-10 2000-08-10 Power supply unit WO2002015377A1 (en)

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EP2740208B2 (en) † 2011-08-02 2023-06-07 Sew-Eurodrive GmbH & Co. KG Electronic device, in particular transmitter head, and system for wireless energy transfer

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AU2000264741A1 (en) 2002-02-25

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