JPH11233730A - Mosfet with rectifying circuit and bias supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rectifying circuit to control voltage drop in MOSFET and prevent drop of rectifying efficiency even when a MOSFET is used as a rectifying element. SOLUTION: In this rectifying circuit, a second p-channel MOS transistor Tr2 connecting the source to an input terminal P1 and the gate to an output terminal O1 and a third p-channel MOS transistor Tr3 connecting the source to the output terminal O1 and the gate to the input terminal, P1 are provided for supplying a back bias voltage to a first p-channel MOS transistor Tr1 as the rectifying element and the drains of both transistors are connected in common to the N well of the first p-channel MOS transistor Tr1. Thereby, the potential of N well is always kept at the value higher than that of the input/ output terminals P1, O1 to prevent the rise of threshold voltage and generation of a leak current from parasitic diodes D1, D2, D3, D4 of the MOS transistors Tr1 to Tr3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rectifier circuit for converting an AC signal into a DC signal and a MOSF with a bias supply circuit.
More particularly, the present invention relates to a rectifier circuit using a MOSFET as a rectifier.

[0002]

2. Description of the Related Art Diodes are known as rectifiers used in general rectifier circuits. However, when the rectifier circuit is formed on the same substrate as other semiconductor circuits,
Transistors formed at the same time may be used as rectifying elements due to ease of fabrication.

In particular, in a non-contact type IC card which has been rapidly developed in recent years, in order to cover internal power, a rectifying element for rectifying an electromagnetic wave received by an antenna coil is provided.
MOSFETs are connected by diodes. FIG. 9 shows an example of a rectifier circuit configured by connecting the MOSFETs with diodes.

In FIG. 9, of the four n-channel transistors Tr41 to Tr44, which are rectifiers, transistors Tr41 and Tr44 have drains connected to the input terminal P.
The source of the transistor Tr41 is connected to the output terminal O1, and the source of the transistor Tr44 is connected to the output terminal O2. Also, the transistor T
The gate of r41 is connected to the drain, and the transistor T41
The gate of r44 is connected to the source.

On the other hand, transistors Tr42 and Tr43
Has a source connected to the input terminal P2, a drain of the transistor Tr42 connected to the output terminal O1, and a drain of the transistor Tr43 connected to the output terminal O2. Further, a capacitor C constituting a smoothing circuit is connected between the output terminals O1 and O2. The gate of the transistor Tr42 is connected to the source, and the gate of the transistor Tr44 is connected to the drain.

When the potential of the input terminal P1 is higher than that of the input terminal P2, the rectifier circuit described above uses the transistor Tr41, the capacitor C and the transistor Tr41 from the input terminal P1.
A current flows through a route returning to the input terminal P2 through 43,
A voltage corresponding to the electric charge stored in the capacitor C is taken out from the output terminals O1 and O2 as a rectified voltage.

On the other hand, the input terminal P2 is connected to the input terminal P1.
In the case of a higher potential, the transistor Tr
42, a current flows through a route returning to the input terminal P1 through the capacitor C and the transistor Tr44, and the output terminal O
1. A rectified voltage is extracted from O2. The rectification efficiency in the rectifier circuit is mainly determined by the transistors Tr41 to Tr41.
It depends on the voltage drop at 44.

Accordingly, the transistors Tr41 to Tr41
In the case where the driving capability of the transistor Tr44 is sufficient and it is operated in the linear region, the transistors Tr41 to Tr44
Can be approximated to the threshold voltage, so that the smaller the threshold voltage, the more efficiently the voltage can be taken out.

[0009]

However, in a conventional rectifying circuit, for example, a transistor Tr is used as a rectifying element.
Focusing on 41, since its source is connected to the output terminal O1, the source potential becomes higher than the reference potential (P-well potential), a back bias effect occurs, the threshold voltage of the transistor Tr41 increases, and the rectification efficiency increases. Will get worse.

In order to prevent the back bias effect,
Instead of the transistor Tr41, as shown in FIG.
When a transistor Tr45 configured to supply a back bias voltage from the source to the P well is used as a rectifier, when the potential of the input terminal P1 falls below the potential of the output terminal O1, the potential of the P well exceeds the drain potential. As a result, the parasitic diode D5 between the P well and the drain is turned on, and the electric charge stored in the smoothing capacitor C leaks through the diode D5. As a result, a voltage drop corresponding to the leakage is caused to lower the output voltage, and as a result, the rectification efficiency is deteriorated.

On the other hand, when power is supplied to a built-in IC of an IC card, it is necessary to rectify a very small alternating current, so that high rectification efficiency is required. Therefore, when such a rectification method is used as a method for supplying power to the built-in IC of the IC card, the rise in the threshold voltage and the voltage drop due to the leak from the parasitic diode deteriorate the rectification efficiency, and the built-in IC is There was a problem that sufficient power could not be supplied.

It is an object of the present invention to provide a rectifier circuit that suppresses a voltage drop in a transistor even when a MOSFET is used as a rectifier, and prevents a decrease in rectification efficiency.

[0013]

In order to solve the above problems, a rectifier circuit according to the present invention comprises a first p-channel MOSFET having a source connected to an input terminal, a drain and a gate connected to output terminals, A smoothing capacitor connected to an output terminal, wherein the first p-channel MOSFET is connected to a high potential terminal of the input terminal and output terminal voltages.
Bias means for supplying a back bias voltage to the power supply.

The bias means includes a second p-channel MOSFET having a source connected to the input terminal and a gate connected to the output terminal, a gate connected to the input terminal, a source connected to the output terminal, and a drain connected to the output terminal. Is the second M
A third p-channel M connected to the drain of the OSFET
An OSFET may be used, and means for supplying a back bias voltage to the first to third MOSFETs from a connection point between the drain of the second MOSFET and the drain of the third MOSFET may be used. The first to third p-channel MOSFETs can be formed in a common N well.

As another example of the bias means, a first Schottky diode having an anode terminal connected to the input terminal, an anode terminal connected to the output terminal, and a cathode terminal connected to the cathode terminal of the first Schottky diode. And a second Schottky diode connected to the MOS transistor from a connection point between the cathode of the first Schottky diode and the cathode of the second Schottky diode.
Means for supplying a back bias voltage to the FET can be used. The cathodes of the first p-channel MOSFET and the first and second Schottky diodes can be formed in a common N-well.

Further, even if these bias means are not used, means for making the potential of the N well of the first p-channel MOSFET higher than the potential of the source or drain may be used.

The same means can be used when an n-channel MOSFET is used as the rectifier. That is,
A rectifier circuit using an n-channel MOSFET as a rectifier has a first n-channel MOSFET having a source connected to an input terminal and a drain and a gate connected to output terminals.
ET and a smoothing capacitor connected to the output terminal, and a bias means for supplying a back bias voltage to the first n-channel MOSFET from a terminal having a lower potential among the voltages of the input terminal and the output terminal.

As the bias means, a second n-channel transistor having a source connected to the input terminal and a gate connected to the output terminal is provided.
A channel MOSFET, a gate connected to the input terminal, a source connected to the output terminal, and a drain connected to the second M
A third n-channel M connected to the drain of the OSFET
An OSFET may be used, and means for supplying a back bias voltage to the first to third MOSFETs from a connection point between the drain of the second MOSFET and the drain of the third MOSFET may be used. The first to third n-channel MOSFETs can be formed in a common P well.

As another example of the bias means, a first Schottky diode having a cathode terminal connected to an input terminal, a cathode terminal connected to an output terminal, and an anode terminal connected to the anode terminal of the first Schottky diode And a second Schottky diode connected to the anode of the first Schottky diode and the anode of the second Schottky diode.
Means for supplying a back bias voltage to the OSFET can be used.

Further, even if these bias means are not used, a means may be used in which the potential of the P well of the first n-channel MOSFET becomes lower than the potential of the source and drain.

According to the present invention, the rectifying element MOS
Means for supplying a back bias voltage to the FET,
N if the MOSFET is a p-channel MOSFET
By supplying a back bias voltage so that the potential of the well is equal to or higher than the potential of the two terminals and, if the MOSFET is an n-channel MOSFET, the potential of the P well is equal to or lower than the potential of the two terminals, the threshold voltage of the MOSFET In addition, the parasitic diodes formed between the source and drain of the MOSFET and the well can be prevented from being forward biased, and leakage through the parasitic diode can be prevented. As a result, a voltage drop in the MOSFET can be prevented, and the rectification efficiency is improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a rectifier circuit according to a first embodiment of the present invention.
FIG. 3 is a view showing an element structure of the MOS transistor portion. As shown in FIG. 1, a p-channel MO that is a rectifying element
The source of the S transistor Tr1 is the input terminal P1
The drain and the gate are connected to the output terminal O1. The smoothing capacitor C is connected to the output terminal O1.

On the other hand, the two Schottky diodes SD1 and SD2 for supplying the back bias voltage to the MOS transistor Tr1 have anode terminals connected to the input terminal P1 and output terminal O1, respectively, and a cathode terminal commonly used for the substrate of the MOS transistor Tr1. It is connected to the.

As shown in FIG. 2, ap ⁺ layer as a source and a drain of a MOS transistor Tr1 is formed in an N well provided in a p-type silicon substrate. Metal wirings serving as anodes of the Schottky diodes SD1 and SD2 are formed.

Also, the p and p generated between the source and drain (p ⁺ ) of the MOS transistor Tr1 and the N well, respectively.
The n-junction diodes (parasitic diodes) are shown as D1 and D2 in FIGS. In FIGS. 1 and 2, a smoothing capacitor to be connected to the output terminal is not shown.

Next, the operation of the rectifier circuit of this embodiment will be described. In FIG. 2, when the potential of the input terminal P1 is higher than the potential of the output terminal O1, the MOS transistor Tr1 is turned on and a current flows from the source to the drain, and a smoothing capacitor C connected to the output terminal O1 (see FIG. 1). The electric charge is accumulated.

In this case, the anode is connected to the input terminal P1, the Schottky diode SD1 having the N well as the cathode operates, and the potentials of the source and the N well become equal. Therefore, the threshold voltage rises due to the back bias effect and the parasitic diode D between the source and the N well.
1 can be prevented from leaking.

On the other hand, the potential of the input terminal P1 is
Becomes lower than the potential of the MOS transistor Tr1.
FF. In this case, the anode is connected to the output terminal O1, and the Schottky diode SD2 using the N well as the cathode operates to keep the potential of the N well equal to the potential of the drain. Thereby, the parasitic diode D
2 can be prevented.

In short, in this embodiment, the input terminal P
1 and the output terminal O1 as anodes, respectively, and Schottky diodes SD1 and SD
2, only the Schottky diode connected to the higher one of the source and the drain of the two diodes operates, and the potential of the N-well is always maintained at the source or drain potential or higher. Can be.

Therefore, it is possible to prevent the threshold voltage of MOS transistor Tr1 from rising, and to reduce the parasitic diode D1,
Since the output current can be prevented from lowering by preventing the leakage current due to D2, the rectification efficiency is improved. It should be noted that the Schottky diodes SD1 and S1
The area required for the rectifier circuit increases due to the addition of D2. However, the driving capability of the Schottky diodes SD1 and SD2 may be low,
It is possible to reduce the area of D1 and SD2.

Next, FIG. 3 shows a circuit configuration of a rectifier circuit according to a second embodiment of the present invention, and FIG.
4 shows an element structure of a transistor portion. As shown in FIG. 3, the first p-channel MOS transistor Tr1 as a rectifier has a source connected to the input terminal P1, and a drain and a gate connected to the output terminal O1. The smoothing capacitor C is connected to the output terminal O1.

On the other hand, a second p-channel MOS for supplying a back bias voltage to the first MOS transistor Tr1
The transistor Tr2 has a source connected to the input terminal P1, and a gate connected to the output terminal O1. Similarly, the source of the third p-channel MOS transistor Tr3 for supplying the back bias voltage to the first MOS transistor Tr1 is connected to the output terminal O1,
The gate is connected to the input terminal P1. Further, both drains are connected in common, and the first p-channel MO is connected.
It is connected to the substrate of S transistor Tr1.

As shown in FIG. 4, p ⁺ layers serving as sources and drains of the first to third MOS transistors Tr1 to Tr3 and n ⁺ for supplying a back bias are provided in an N well provided on a p-type silicon substrate. A layer is formed.

The drain of the first MOS transistor Tr1 and the source of the third MOS transistor Tr3,
Since the sources of the first and second MOS transistors Tr1 and Tr2 each use a common p ⁺ layer, three M
Four p ⁺ layers may be formed for the OS transistor. Second and third MOS transistors Tr2, Tr3
The p ⁺ layer, which is the drain of the gate electrode, and the n ⁺ layer for supplying a back bias adjacent thereto are commonly connected by wiring.
The gates of the first to third MOS transistors Tr1 to Tr3 are formed on the second and substrate.

The MOS transistors Tr1 to Tr3
A pn junction diode (parasitic diode) generated between the source and drain (p ⁺ ) and the N well of FIG.
4 and D1, D2, D3, and D4, respectively. In FIG. 4, the illustration of the smoothing capacitor C to be connected to the output terminal O1 is omitted.

The operation of the rectifier circuit in the present embodiment is as follows.
In the first embodiment described with reference to FIG. 2, the Schottky diode SD1 is used as the second MOS transistor Tr2, and the Schottky diode SD2 is used as the third MO transistor.
What is necessary is just to consider it as having replaced with S transistor Tr3.

That is, the potential of the input terminal P1 is
1, the first MOS transistor Tr
1 and the second MOS transistor Tr2 are turned on, and the potential of the N well is kept equal to the source potential of the first MOS transistor Tr1, so that the threshold voltage rise due to the back bias effect and the leakage current in the parasitic diode D1 are reduced. High output voltage can be obtained without impairing the rectification efficiency.

The potential of the input terminal P1 is changed to the output terminal O1.
Is lower than the potential of the first MOS transistor Tr1.
Turns off. At this time, the third MOS transistor Tr
3 is turned on, and the potential of the N well is kept equal to the drain potential of the first MOS transistor Tr1, so that a leak current in the parasitic diode D2 can be prevented, and a high output voltage can be obtained without impairing the rectification efficiency.

The second and third MOS transistors T
Since the drain potentials of r2 and Tr3 are always equal to the N-well potential, it is clear that there is no leakage from the parasitic diodes D3 and D4.

In short, in the present embodiment, the source is connected to the input terminal P1, the gate is connected to the second p-channel MOS transistor Tr2 connected to the output terminal O1, the source is connected to the output terminal O1, and the gate is connected to the output terminal O1. Input terminal P1
-Channel third MOS transistor Tr connected to
3 and both drains are connected to a first p-channel MOS.
By connecting to the N well of the transistor Tr1, only the transistor whose gate is connected to the lower one of the input terminal and the output terminal of the second and third transistors operates, and the N well Can always be kept above the source and drain potentials.

Thus, the threshold voltage of the MOS transistor Tr1 is prevented from rising, and the parasitic diodes D1, D2, D3,
Since the leakage current due to D4 can be prevented and the output voltage can be prevented from lowering, the rectification efficiency is improved. It should be noted that the rectifier has a second and third MOS transistors T
With the addition of r2 and Tr3, the area required for the rectifier circuit increases.

However, since the driving capability of the second and third MOS transistors Tr2 and Tr3 may be low, their area can be made smaller than that of the first MOS transistor Tr1. In addition, since the first to third MOS transistors Tr1 to Tr3 can share the N well, the source, and the drain, the rectifier circuit of the present embodiment can be manufactured without a significant increase in the number of steps.

Next, FIG. 5 shows an element structure of a MOS transistor portion of a rectifier circuit according to a third embodiment of the present invention. The circuit configuration of the rectifier circuit in the present embodiment is shown in FIG.
In the first embodiment described above, the anode terminals of the Schottky diodes SD1 and SD2 are replaced with cathode terminals, the cathode terminals are replaced with anode terminals, respectively, and the p-channel MOS transistor Tr1 is replaced with an n-channel MOS transistor Tr4. The illustration is omitted.

As shown in FIG. 5, an n ⁺ layer serving as a source and a drain of a MOS transistor Tr4 and a p ⁺ layer for supplying a back bias are formed in a P well provided in an n-type silicon substrate. A gate is formed above. An n ⁻ layer serving as a cathode of the Schottky diodes SD3 and SD4 is formed in a region other than the P well, and a metal wiring serving as an anode is formed on the substrate. Note that the Schottky diode SD is passed through the substrate.
A p ^- layer is formed so as to surround the n ⁺ layer serving as a cathode so that the cathodes of SD3 and SD4 are not connected.

Further, p generated between the source and drain (n ⁺ ) of the MOS transistor Tr4 and the P well, respectively.
In FIG. 5, an n-junction diode (parasitic diode) is shown.
Shown as D5 and D6, respectively. In this figure, the illustration of the smoothing capacitor C to be connected to the output terminal O1 is omitted.

The operation of the rectifier circuit in the present embodiment is as follows.
In the first embodiment shown in FIG.
The OS transistor Tr1 is replaced with an n-channel MOS transistor Tr4, and the Schottky diode SD1
It may be considered that the connection of SD2 is replaced in the opposite direction.

That is, the potential of the input terminal P1 is
When the potential is higher than 1, that is, when the MOS transistor Tr4 is OFF, the second Schottky diode SD4 operates to keep the potential of the P well equal to the drain potential of the MOS transistor Tr4. Leak current can be prevented.

The potential of the input terminal P1 is changed to the output terminal O1.
Is lower than the potential of the MOS transistor T,
When r4 is ON, the first Schottky diode SD3 operates to keep the potential of the P well equal to the source potential of the MOS transistor Tr4.
5 can be prevented. Therefore, a high output voltage can be obtained without impairing the rectification efficiency.

In short, in this embodiment, the input terminal P
By providing Schottky diodes SD3 and SD4 having cathodes 1 and the output terminal O1, respectively, and having an anode commonly connected to the P well, the two diodes are connected to the lower potential of the source and the drain of the two diodes. Only the active Schottky diode operates, and the potential of the P well can always be kept below the potential of the source and drain.

As a result, an increase in the threshold voltage of the MOS transistor Tr4 can be prevented, a leakage current due to the parasitic diodes D5 and D6 of the MOS transistor Tr4 can be prevented, and a decrease in the output voltage can be prevented. Efficiency is improved. In addition, the area required for the rectifier circuit increases by adding Schottky diodes SD3 and SD4 to the rectifier element as compared with the related art. However, the driving capability of the Schottky diodes SD3 and SD4 may be low, so that the area of the Schottky diodes SD3 and SD4 can be reduced.

Next, FIG. 6 shows an element structure of a MOS transistor portion of a rectifier circuit according to a fourth embodiment of the present invention. The circuit configuration of the rectifier circuit in the present embodiment is shown in FIG.
In the second embodiment described above, the first to third p-channel MOS transistors Tr1 to Tr3 are replaced with n-channel MOS transistors Tr4 to Tr6, respectively, and are not shown.

As shown in FIG. 6, n ⁺ layers serving as sources and drains of the first to third MOS transistors Tr4 to Tr6 and p ⁺ for supplying a back bias are provided in a P well provided in an n type silicon substrate. A layer is formed. First
And the sources of the second and third MOS transistors Tr4 and Tr5, and the drain of the first MOS transistor Tr4 and the source of the third MOS transistor Tr6 each use a common n ⁺ layer. In contrast, four n ⁺ layers may be formed.

Second and third MOS transistors Tr
2. The n ⁺ layer, which is the drain of Tr3, and the p ⁺ layer for back bias supply adjacent thereto are commonly connected by wiring. The gates of the first to third MOS transistors Tr4 to Tr6 are formed on the substrate.

The MOS transistors Tr4 to Tr6
6, pn junction diodes (parasitic diodes) generated between the source and drain (n ⁺ ) and the P well are shown as D5, D6, D7, and D8 respectively in FIG. In this figure, the illustration of the smoothing capacitor C to be connected to the output terminal O1 is omitted.

The operation of the rectifier circuit in the present embodiment is as follows.
In the second embodiment described with reference to FIG.
To the third p-channel MOS transistors Tr1 to Tr
3 may be replaced with n-channel MOS transistors Tr4 to Tr6.

That is, the potential of the input terminal P1 is
1, the first n-channel M
When the OS transistor Tr4 is OFF, the third M
Since the OS transistor Tr6 is turned on and the potential of the P well is kept equal to the drain potential of the first MOS transistor Tr4, it is possible to prevent a leakage current in the parasitic diode D6.

Further, the potential of the input terminal P1 is changed to the output terminal O1.
, Ie, the first n-channel MO
When the S transistor is turned on, the second MOS transistor Tr5 is turned on, and the potential of the P well is changed to the first MO transistor.
In order to keep it equal to the source potential of the S transistor Tr4,
It is possible to prevent an increase in threshold voltage due to the back bias effect and a leak current in the parasitic diode D5.

Therefore, a high output voltage can be obtained without impairing the rectification efficiency. Since the drain potentials of the second and third MOS transistors Tr5 and Tr6 are always equal to the P-well potential, it is clear that there is no leakage from the parasitic diodes D7 and D8.

In short, in the present embodiment, the second n-channel MOS transistor Tr5 whose source is connected to the input terminal P1 and whose gate is connected to the output terminal O1, the source is connected to the output terminal O1, and the gate is Input terminal P1
N-channel MOS transistor Tr connected to
6 and both drains are connected to the first n-channel MOS.
By connecting to the P well of the transistor Tr4, only the transistor whose gate is connected to the higher potential of the input terminal and the output terminal of the second and third transistors operates, and the P well Can always be kept below the source and drain potentials.

This prevents an increase in the threshold voltage of the MOS transistor Tr4, and prevents the parasitic diodes D5, D6, D7,
Since the leakage current due to D8 can be prevented and the output voltage can be prevented from lowering, the rectification efficiency is improved.

Note that the rectifying element has a second and third
By adding the MOS transistors Tr5 and Tr6, the area required for the rectifier circuit increases. However, since the driving capability of the second and third MOS transistors Tr5 and Tr6 may be low, their area can be made smaller than that of the first MOS transistor Tr4. Also,
The first to third MOS transistors Tr4 to Tr6 are:
Since the N well, the source, and the drain can be shared, the rectifier circuit of the present embodiment can be manufactured without a significant increase in the number of steps.

Further, as a fifth embodiment of the present invention,
As shown in FIG. 7, transistors BTr1 and BTr2 with a bias supply circuit in which the smoothing capacitor C is removed from the rectifier circuit described in the second embodiment of the present invention, and a fourth embodiment of the present invention.
Transistor BTr with a bias supply circuit obtained by removing the smoothing capacitor C from the rectifier circuit described in the embodiment.
It is also possible to configure a full-wave rectifier circuit by using the devices 3 and 4 and connecting them in a bridge type as diodes.

Although the rectifier circuit of the second embodiment and the rectifier circuit of the third embodiment are used in combination in FIG. 7, the rectifier circuits shown in the first to fourth embodiments are used. Of these, any four may be combined.

Further, the transistor BTr1 with a bias supply circuit can be used not only in a rectifier circuit but also in a portion where threshold voltage modulation of a transistor due to a back bias effect must be minimized. For example, as shown in FIG. 8 as a sixth embodiment of the present invention, the gate of the first p-channel MOS transistor Tr1 is connected to the output of the driver 1, the source is connected to VDD, and the drain is connected to the output terminal O1 and the ground. By connecting, the output of the driver 1 can be efficiently extracted.

It should be noted that the present invention is not intended to be limited to the above embodiment. For example, in the fourth embodiment, n
Various design changes are possible within the gist of the present invention, such as using a so-called triple well structure in which a p-type substrate is used instead of a mold substrate and an n-well is formed so as to surround the p-well.

[0066]

As described above, according to the present invention,
Even when a MOSFET is used as a rectifying element, a rectifying circuit that suppresses a rise in threshold voltage and a leak due to a parasitic diode, prevents a voltage drop in the MOSFET, and prevents a reduction in rectifying efficiency can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an element structure of the rectifier circuit of FIG.

FIG. 3 is a circuit diagram illustrating a configuration of a rectifier circuit according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing an element structure of the rectifier circuit of FIG.

FIG. 5 is a sectional view showing an element structure of a rectifier circuit according to a third embodiment of the present invention.

FIG. 6 is a sectional view illustrating an element structure of a rectifier circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a rectifier circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a rectifier circuit according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional rectifier circuit.

FIG. 10 is a circuit diagram showing a configuration of a conventional rectifier.

[Description of Signs] P1, P2 input terminals O1, O2 output terminals Tr1 to Tr4 p-channel MOS transistors Tr5 to Tr8 n-channel MOS transistors D1 to D8 parasitic diodes SD1 to SD4 Schottky diodes C smoothing capacitors

Claims (13)

[Claims] 1. A p-channel MOSF having a source connected to an input terminal and a drain and a gate connected to an output terminal.
ET and a smoothing capacitor connected to an output terminal, comprising: a means for supplying a back bias voltage from the high potential terminal of the input terminal and the output terminal to the p-channel MOSFET. Rectifier circuit. 2. A first p-channel transistor having a source connected to the input terminal and a drain and gate connected to the output terminal.
An OSFET and a second p-channel MOS transistor having a source connected to the input terminal and a gate connected to the output terminal
An FET, a gate connected to the input terminal, a source connected to the output terminal, and a drain connected to the second MOS
Third p-channel MOS connected to the drain of the FET
An FET, and a smoothing capacitor connected to the output terminal, wherein a connection point between the drain of the second p-channel MOSFET and the drain of the third p-channel MOSFET is connected to the first to third MOSFETs. A rectifier circuit to which a bias voltage is supplied. 3. The first to third p-channel MOSFs
The rectifier circuit according to claim 2, wherein the ET is formed in a common N-well. 4. A p-channel MOSF having a source connected to the input terminal and a drain and a gate connected to the output terminal.
ET and a first terminal having an anode terminal connected to the input terminal.
A second Schottky diode having an anode terminal connected to the output terminal and a cathode terminal connected to the cathode terminal of the first Schottky diode; and a smoothing capacitor connected to the output terminal. A rectifier circuit, wherein a back bias voltage is supplied to the p-channel MOSFET from a connection point between the cathode of the first Schottky diode and the cathode of the second Schottky diode. 5. The p-channel MOSFET and the first
And the second Schottky diode have a common N
The rectifier circuit according to claim 4, wherein the rectifier circuit is formed in a well. 6. An n-channel MOSF having a source connected to the input terminal and a drain and a gate connected to the output terminal.
ET, a smoothing capacitor connected to the output terminal, and a means for supplying a back bias voltage to the n-channel MOSFET from a low potential terminal of the input terminal and the output terminal. Rectifier circuit. 7. A first n-channel transistor having a source connected to the input terminal and a drain and a gate connected to the output terminal.
An OSFET and a second n-channel MOS transistor having a source connected to the input terminal and a gate connected to the output terminal
An FET, a gate connected to the input terminal, a source connected to the output terminal, a drain connected to the drain of the second n-channel MOSFET, a third n-channel MOSFET connected to the output terminal; And a back bias voltage is supplied from the drain of the second n-channel MOSFET and the drain of the third n-channel MOSFET to the first to third n-channel MOSFETs. Rectifier circuit. 8. The first to third n-channel MOSFs
The rectifier circuit according to claim 7, wherein the ET is formed in a common P well. 9. An n-channel MOSF having a source connected to the input terminal, and a drain and a gate connected to the output terminal.
ET and a first terminal having a cathode terminal connected to the input terminal.
A second Schottky diode having a cathode terminal connected to the output terminal and an anode terminal connected to the anode terminal of the first Schottky diode; and a smoothing capacitor connected to the output terminal. A rectifier circuit, wherein a back bias voltage is supplied to the MOSFET from a connection point between the anode of the first Schottky diode and the anode of the second Schottky diode. 10. A p-channel MOS having a source connected to an input terminal and a drain and a gate connected to an output terminal.
An FET and a smoothing capacitor connected to an output terminal; and a bias voltage supply means for setting the N-well potential of the p-channel MOSFET to be equal to or higher than the potentials of the source and the drain. Rectifier circuit. 11. An n-channel MOS having a source connected to the input terminal and a drain and a gate connected to the output terminal.
An FET and a smoothing capacitor connected to an output terminal; and a bias voltage supply means for setting a P-well potential of the n-channel MOSFET to be equal to or lower than a potential of the source and the drain. Rectifier circuit. 12. The p-channel MOSFET according to claim 1, further comprising:
MOSF with a bias supply circuit, comprising means for supplying a bias voltage to an N well of an ET.
ET. 13. A MOSFET with a bias supply circuit, comprising: means for supplying a bias voltage from a low potential region of a source and a drain of an n-channel MOSFET to a P-well of the MOSFET.