JP2000092846A - Rectifying circuit and rectifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly efficient rectifying circuit enabling integration, by connecting the sources/drains of NMOS transistors with first and second input terminals and negative-pole output terminals, and connecting the first and second input terminals with the gates of the third and fourth NMOS transistors, respectively. SOLUTION: A first input terminal 105 is connected with the gate of a fourth NMOS transistor 4 and the drain of a third NMOS transistor 3. A second input terminal 106 is connected with the gate of the third NMOS transistor 3 and the drain of the fourth NMOS transistor 4. The sources of the NMOS transistors 3 and 4 and sub-electrodes are connected with a negative input terminal 108. When an alternating-current signal is inputted to the first and second input terminals 105 and 106, as mentioned above, the third and fourth NMOS transistors 3 and 4 are repeatedly and alternately turned on and off in conformity with the frequency of the alternating-current signal according to the voltage levels of the input terminals 105 and 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a rectifier circuit.

[0002]

2. Description of the Related Art Conventionally, when rectifying an AC voltage into a DC voltage, a full-wave rectifier circuit or a half-wave rectifier circuit has been used. Particularly, when priority is given to the efficiency of rectification, a full-wave rectifier circuit is used, and a bridge type rectifier circuit composed of four diodes is used as a typical circuit.

However, with the recent trend toward smaller and thinner devices or lower costs, a method of integrating a rectifier circuit on a single chip is becoming widespread. In particular, for an IC card that rectifies radio waves and uses it as driving power for the IC, it is essential that the IC card be thin, and using an external diode outside the IC does not satisfy the card thickness specification.

Therefore, it is important to integrate a rectifier circuit inside an IC. For example, whether the characteristics of a diode that can be manufactured in a CMOS manufacturing process show the characteristics required for the rectifier circuit is determined. Another problem is that the number of manufacturing steps does not increase in order to manufacture required characteristics.

FIG. 12A shows the characteristics of a general commercially available rectifier diode, and FIG. 12B shows the characteristics of a diode manufactured in a CMOS manufacturing process. Back recovery time becomes a problem in these characteristic diagrams. That is, when the bias voltage applied to the diode is switched from the forward bias to the reverse bias at the timing of time ta in the drawing, a reverse bias current flows for a certain time (ts), and the time until the current converges is called a back recovery time. . All the reverse bias current flowing during this period not only reduces the rectification efficiency as power loss, but also causes the device to generate heat, which leads to a reduction in the life of the device.

When these characteristics are compared in FIG. 12, FIG.
It can be seen that the diode manufactured in the CMOS manufacturing process 2 (b) has a very long back recovery time, and it is difficult to realize a highly efficient rectifier circuit. The cause is that when a forward bias is applied to the pn junction, a large number of holes (minority carriers) are accumulated in the n region, and when a reverse bias is applied, the holes diffuse from the n region to the p region and are wiped out of the n region. . The movement of minority carriers at this time is the cause of the problem. In order to solve this problem, in order to realize a diode for high-speed switching operation such as rectification, a method is employed in which holes are recombined with impurities such as gold before the holes diffuse into the p region.
However, a pn manufactured by a general MOS process
The junction does not use the impurity and requires a dedicated process to realize it. Further, when a rectifier diode and a CMOS transistor are integrated, even if an impurity is implanted, great care must be taken to suppress the influence on the MOS transistor in the manufacturing process.
For the above reasons, a diode is difficult to integrate a rectifier circuit and other functions on one chip.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly efficient rectifier circuit that can be integrated in a semiconductor integrated circuit.

[0008]

According to the first aspect of the present invention,
First and second input terminals for inputting an AC signal, a smoothing capacitor for smoothing the rectified current, a positive output and a negative output connected to the capacitor, the first input terminal and the positive output A first rectifier element connected between the first input terminal and the negative electrode output; a second rectifier element connected between the second input terminal and the positive electrode output; A third rectifying element connected between the second rectifying element and the second rectifying element;
And a fourth rectifier connected between the negative input terminal and the negative output, the third and fourth rectifiers are respectively formed by third and fourth NMOS transistors. The source and drain of each NMOS transistor are connected to first and second input terminals and a negative output terminal, respectively, and the first input terminal is connected to the fourth input terminal.
Connected to the gate of the NMOS transistor
Is connected to the gate of the third NMOS transistor.

Therefore, according to the rectifier circuit of the first aspect, when an AC signal is input to the first and second input terminals, the third and fourth NMOs depend on the voltage level of the input terminal.
The S transistor is alternately turned on in accordance with the frequency of the AC signal.
Repeat N-OFF. At this time, generation and annihilation of the electron inversion layer are repeated in the channel region of the NMOS transistor. However, when the annihilation electron is discharged to the source or drain, a rectifying device having a high-speed switching function can be configured. The element becomes a rectifying element to the negative output which is indispensable for the rectifying circuit. Note that the first and second rectifying elements are required to have a high-speed switching function.

According to a second aspect of the present invention, in the first aspect, the first and second rectifying elements are also respectively a first and a second NMOS.
The source and drain of each NMOS transistor are connected to a first and second input terminal and a negative output terminal, respectively, and a first N
This is achieved by connecting the gate of the MOS transistor to the first input terminal and connecting the gate of the second NMOS transistor to the second input terminal.

Therefore, according to the rectifier circuit of the second aspect, when an AC signal is input to the first and second input terminal terminals, the first and second NMOs are changed according to the voltage level of the input terminal.
The S transistor is alternately turned on in accordance with the frequency of the AC signal.
Repeat N-OFF. The NMOS transistor also becomes a rectifying element having a high-speed switching function as described above, and this element becomes a rectifying element for a positive output which is indispensable for a rectifying circuit. With these configurations, a full-wave rectifier circuit composed of NMOS transistors is realized.

According to a third aspect of the present invention, in the second aspect, the first and second NMOS transistors are third and fourth N-type transistors.
This is achieved by having a thinner gate oxide thickness than the gate oxide thickness of the MOS transistor.

According to the rectifier circuit of the third aspect, the ON resistance of the first and second NMOS transistors can be reduced by reducing the thickness of the gate oxide film. Rectification efficiency is improved.

According to a fourth aspect of the present invention, in the second aspect, the first and second NMOS transistors are third and fourth N-type transistors.
This is achieved by having an NMOS transistor with a low threshold voltage relative to the threshold voltage of the MOS transistor.

Therefore, according to the rectifier circuit of the fourth aspect, the voltage loss caused by the threshold voltages of the first and second NMOS transistors is improved.

According to a fifth aspect of the present invention, in the first aspect, the first and second rectifying elements are respectively a first and a second NM.
The source and drain of each NMOS transistor are connected to first and second input terminals and a positive output terminal, respectively.
A bias circuit that always keeps the difference between the gate voltage of the first NMOS transistor and the input voltage of the input terminal of the first NMOS terminal at a voltage difference corresponding to the threshold voltage of the NMOS transistor. N
This is achieved by having a bias circuit that always keeps the difference between the gate voltages of the MOS transistors at a voltage difference corresponding to the threshold voltage of the NMOS transistor.

Therefore, according to the rectifier circuit of claim 5, since the gate voltages of the first and second NMOS transistors are always biased by the threshold voltage, the threshold voltage is apparently equivalent to 0V. Therefore, the voltage loss caused by the threshold voltage is improved.

[0018]

Embodiments of the present invention will be described below. FIG. 1 shows a specific circuit according to the first embodiment of the present invention, and the operation of the rectifier on the negative output side of the full-wave rectifier circuit will be described.

In FIG. 1, reference numerals 103 and 104 denote third and fourth NMOS transistors, respectively (hereinafter referred to as Tr transistors, respectively).
3, the threshold voltage of each transistor is denoted as Vth3, Vth4), the first input terminal 105 is connected to the gate of Tr4 and the drain of Tr3, and the second input terminal Reference numeral 106 is connected to the gate of Tr3 and the drain of Tr4.
The sources and sub-electrodes of Tr3 and Tr4 are connected to the negative output terminal 108. Now, input terminals 105 and 106
To the input terminal 10
6 and the voltage of the input terminal 105 (hereinafter, V106, V105
V106> V105 + Vth)
3, Tr3 keeps ON state and Tr4 becomes O
Hold the FF state.

FIG. 2 shows the operation of Tr3 in this state in detail. In this state, the load current 202 of the rectifier circuit flows from the negative output terminal 108 to the input terminal 105. The path of this current is that the parasitic diode 201 of the drain of Tr3 exists in addition to the channel of Tr3. become. Since the diode is a silicon diode manufactured by a MOS process and high-speed operation is difficult, it is necessary to design the ON resistance of Tr3 so that the diode does not turn on. That is, Tr
Under the condition that the voltage drop due to the ON resistance of No. 3 is smaller than the forward current of the diode, Tr3 functions as a good rectifying element. From the above, V106> V105 +
Under the condition of Vth3, the voltage of the negative output terminal is V10
5+ [voltage drop]. Similarly, V105> V106 +
Under the condition of Vth4, the voltage of the negative output terminal is V10
6+ [voltage drop].

In order to clarify the above operation, the circuit shown in FIG.
), The voltage of the negative output terminal 108 (V10
8) is shown in FIG. According to FIG.
It is understood from FIG. 5 that Tr3 and Tr4 alternately repeat ON-OFF.

<Embodiment 2> FIG. 4 shows a specific circuit according to Embodiment 2 of the present invention, and the operation of the rectifier on the positive output side of the full-wave rectifier circuit will be described.

In FIG. 4, reference numerals 401 and 402 denote first and second NMOS transistors, respectively (hereinafter referred to as Tr transistors, respectively).
1, the threshold voltage of each transistor is denoted by Vth1 and Vth2), and the first input terminals 105 and 106 are connected to the gate of Tr1 and the drain of Tr2, respectively.

Here, for ease of explanation, it is assumed that the initial voltage Vout is supplied to the smoothing capacitor 110. Focusing on Tr1, the input terminal 105,
An AC signal for power supply is supplied to the input terminal 106 and the voltage of the input terminal 106 and the voltage of the input terminal 105 are relatively V105.
When −V106 ≦ Vout + Vth1, the gate bias (Vgs1) of Tr1 is 0 V, indicating an OFF state. However, when V105−V106> Vout + Vth1, a gate bias is applied but indicates an ON state. The gate bias Vgs1 in this state is as follows: Vgs1 = V105−V106−Vout− [voltage drop]. Similarly for Tr2, V106-V10
When 5 ≦ Vout + Vth2, the OFF state is indicated.
O when V106-V105> Vout + Vth2
Shows the N state.

As described above, the operation of the rectifier circuit of FIG.
Table 1 shows the states of 2, Tr3, and Tr4.

[0026]

[Table 1]

According to Table 1, the positive output 107 and the negative output 10
8 is supplied when Tr1 and Tr4 are simultaneously turned on, that is, V105−V106> Vout +
Vth1 and when Tr2 and Tr3 are simultaneously turned on, that is, V106−V105> Vout + V
two conditions for th2. This condition exists twice in one cycle of the input AC signal and indicates that the full-wave rectification function is performed.

In order to clarify the above operation, the circuit shown in FIG.
V107 and V108 in the case of FIG.
Shown in According to the figure, when the AC waveform V105 is input, there are two charging periods of the smoothing capacity within one cycle, and V107-V108 show a constant voltage depending on the capacity.

FIG. 6 shows a cross-sectional structure of the rectifier shown in FIG. T
r1 is an N-type diffusion region 606, 605 formed on a P-type substrate.
And a gate electrode 607. Similarly, Tr
2, Tr3 and Tr4 are composed of respective N-type diffusion regions 608 and 609, 602 and 603, 611 and 612 and respective gate electrodes 610, 604 and 613. The P-type substrate is electrically connected to the negative output terminal 108 by a P-type diffusion region 617. Suppose an NMOS transistor is a P-type diffusion region (P-type WEL) on an N-type substrate.
L) If it is made above, the NMOS transistor N
There is a vertical parasitic NPN-type bipolar transistor composed of a p-type source or drain, a p-type well and an n-type substrate. The bipolar transistor is a PW
When the current from the external terminal flows into the ELL, that is, the base region, the transistor is turned on. Replacing this phenomenon with a rectifier circuit means that the positive and negative output terminals of the rectifier circuit are short-circuited.

Therefore, in the embodiment of FIG. 6, the use of the NMOS transistor on the P-type substrate avoids the formation of the vertical parasitic bipolar transistor. However, the source and drain of all the NMOS transistors and the P-type substrate constitute horizontal NPN-type bipolar transistors 614, 615 and 616. The bipolar transistor also risks short-circuiting the positive and negative output terminals of the rectifier circuit.

Therefore, by arranging the P-type diffusion region 617 between each NMOS transistor in an annular shape in each NMOS transistor, the base potential of the bipolar transistor can be increased at the same time as the substrate potential is stabilized, and the short circuit is achieved by lowering the current amplification factor. Avoid danger.

With the configuration as in the second embodiment, a rectifier circuit including an NMOS transistor can be provided.

<Embodiment 3> FIG. 7A is a sectional view of an element of a rectifier circuit according to Embodiment 3 of the present invention. The feature of the cross-sectional view lies in the difference between the oxide film thickness of Tr1 (707) and Tr2 (710) and the oxide film thickness of Tr3 (704) and Tr4 (713). In order to facilitate the explanation of the basic concept, the condition “V105−V
106> Vout + Vth1 ", a more detailed operation will be described, but the same applies to other charging periods. Under these conditions, Tr2 and Tr3 are in the OFF state, and the equivalent circuit showing the operation is as shown in FIG. 7B.

When considering the cause of the decrease in the rectification efficiency, the smoothing capacitor 110 is charged via Tr1 and Tr4. However, the ON resistance of the transistor converts a part of the input power into thermal energy. Things are the main cause. Let the ON resistance of the transistor be r and the load resistance of the rectifier circuit be R
When L, the efficiency η of the rectifier circuit is expressed by equation (1).

[0035]

(Equation 1)

From equation (1), it can be seen that the ON resistance of the transistor causes the rectification efficiency to deteriorate. On the other hand, M
It is known that the ON resistance of the OS transistor is inversely proportional to (Vgs-Vth). 7B, when Tr1 and Tr4 are compared from the viewpoint of the gate bias voltage (Vgs), in the case of Tr4, the gate bias voltage of Tr1 is smaller than the input voltage E becomes the gate bias voltage.
E-Vout. In other words, if the conditions such as the shape of the transistor and the device structure are the same, Tr1 has a higher ON resistance than Tr4. From this, the rectification efficiency η
In order to improve the resistance, it is necessary to reduce the ON resistance of Tr1. Equation (2) shows the ON resistance of Tr1.

[0037]

(Equation 2)

[0038]

(Equation 3)

From equation (2), it is understood that the ON resistance of Tr1 is reduced by increasing β in the equation.
The following method can be considered to increase the value from Equation (3).

1) Increase W (channel width).

2) L (channel length) is shortened.

However, 1) is unsuitable for a semiconductor integrated circuit due to an increase in size, and 2) is difficult due to problems in manufacturing and processing and deterioration in breakdown voltage. Therefore, it is possible to reduce the ON resistance by reducing the thickness of the insulating oxide film Tox. Therefore, as shown in FIG. 7, the ON resistance of Tr1 and Tr2 can be reduced by making the oxide film thickness of Tr1 and Tr2 smaller than the oxide film thickness of Tr3 and Tr4.

With the configuration as in the third embodiment, a rectifier circuit with improved conversion efficiency can be provided and a rectifier with a small area can be realized.

<Embodiment 4> FIG. 8 is a sectional view of an element of a rectifier circuit according to Embodiment 4 of the present invention. The feature of the cross-sectional view is that the transistor regions 817 and 8 are used to reduce threshold voltages Vth1 and Vth2 of Tr1 and Tr2.
18 is doped with a phosphorus element.

As can be seen from equation (2), as Vth decreases, the ON resistance decreases.

Equations (4), (5), and (6) show general theoretical equations for Vth.

[0047]

(Equation 4)

[0048]

(Equation 5)

[0049]

(Equation 6)

The symbols in the above formula have the following meanings.

Φf (Fermi potential), φMS (work function between gate and silicon), Qss (interface potential between silicon and oxide film, εo (dielectric constant of vacuum), εsi (relative dielectric constant of silicon), εox (oxide film The relative dielectric constant of the substrate, Nsub (impurity concentration of the substrate), and Vsb (source-substrate potential) What is important in equation (4) is that as Vsb increases, Vth increases and ON resistance increases. 8, Vsb is Vout itself, that is, if the rectified output Vout increases, Vsb also increases at the same time and Vt
h will also increase. Therefore, in order to cancel the increase in Vth, the Vth of Tr1 and Tr2 is made low in advance, which has the effect of alleviating the phenomenon. It should be noted that the increase in Vth due to Vbs is also effective when the oxide film thickness Tox is reduced, and it is also effective to combine the two.

With the configuration as in the fourth embodiment, a rectifier circuit with improved conversion efficiency can be provided and a rectifier having a small area can be realized.

<Fifth Embodiment> FIG. 9 shows an example of a rectifier circuit according to a fifth embodiment of the present invention. In the circuit diagram, 909, 9
Reference numeral 10 denotes a bias circuit for performing ON / OFF control of Tr1 and Tr2.
By always increasing the first input terminal 105 or the second input terminal 106 by a constant voltage value, Tr1 and T1
It is possible to prevent a decrease in rectification efficiency due to the threshold voltage of r2. Hereinafter, the operation of the bias circuits 909 and 910 will be described in detail.

The potential of the first input terminal 105 is relatively lower than the potential of the second input terminal 106, Tr2 and Tr3 are ON, and Tr1 and Tr4 are OFF.
In the initial state where no charge is stored in the smoothing capacitor 907 under the condition that
5 is forward biased. As a result, the smoothing capacitor 907 starts to charge, and the output terminal 10
7, 108 potential difference (Vout) and rectifier diode 90
5, a value determined by the value of the forward voltage Vf (Vout−V
F). When the current flowing through Tr 901 and Tr 902 is sufficiently small with respect to the charge amount of the smoothing conductor 907, the potential of the terminal 911 is always higher than the first input terminal by Vout−Vf. That is, the terminal 911 functions as an output of a rectifier circuit including the rectifier diode 905 and the smoothing capacitor 907. In other words, the series circuit of the NMOS transistors 901 and 902 is driven by the output 911 of the rectifier circuit. Β of NMOS transistors 901 and 902
It is a well-known fact that when β901 and β902 are respectively set to (see Expression (3)) and β902 is sufficiently larger than β901, the source-drain voltage of Tr902 is equal to the threshold voltage of Tr902. That is, when the element structures of Tr902 and Tr1 are made equal and the threshold voltages are designed to be equal, the gate voltage of Tr1 is always higher than the first input terminal 105 by the threshold voltage.

The bias circuit 910 operates in the same manner, and the gate voltage of Tr2 is always higher than the second input terminal 106 by the threshold voltage. As described above, the input terminals 105 or 106 of the Tr1 and Tr2 are switched between the ON and OFF states based on the voltage of the positive electrode output 107 by the bias circuits 909 and 910. In other words, in the fifth embodiment, the effect of lowering the threshold voltages of Tr1 and Tr2 in the fourth embodiment is realized by circuit means. When the threshold voltages of Tr1 and Tr2 are set to 0V in the fourth embodiment, the voltage may become depletion Tr due to manufacturing variations. In this case, the charge of the smoothing capacitor 110 is discharged to the input terminals 105 and 106. This leads to lower efficiency. However, Embodiment 5
Is effective in canceling the loss due to Vth in a self-alignment manner even when there is element variation in manufacturing, and a highly efficient rectifier circuit with good mass productivity can be realized.

FIG. 11 shows a sectional structure of the bias circuit 910. The rectifier diode 906 is formed on an N substrate.
It is composed of a type WELL region and a P-type region formed on the region. The capacitor 908 is configured using a Tr gate material (for example, a polysilicon gate material) and an N-type region formed in a P substrate with a gate oxide film below the gate material as an electrode.

FIG. 11 shows another example of the fifth embodiment.
In this embodiment, the rectifier circuits of the bias circuits 1109 and 1110 are composed of rectifier transistors 1105 and 1106 and smoothing capacitors 1107 and 1108.

[0058]

As described in the above embodiment, by applying the present invention, the rectifying element built in the IC can be
Efficiency can be increased by using an S transistor.

Further, a decrease in efficiency due to the ON resistance and the threshold voltage, which is a problem when using a MOS transistor as a rectifying element, can be prevented by reducing the ON resistance and the threshold voltage of the rectifying transistor. A gate bias circuit is used as a measure against the threshold voltage. Thus, an IC having a highly efficient rectifier circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a basic conceptual diagram of Embodiment 1 according to the present invention.

FIG. 2 is a conceptual diagram of the operation of the first embodiment according to the present invention.

FIG. 3 is an operation waveform and operation condition diagram according to the first embodiment of the present invention.

FIG. 4 is a basic conceptual diagram of a second embodiment according to the present invention.

FIG. 5 is an operation waveform diagram and an operation condition diagram according to a second embodiment of the present invention.

FIG. 6 is a sectional structural view of a second embodiment according to the present invention.

FIG. 7 is a sectional structural view of a third embodiment according to the present invention.

FIG. 8 is a sectional structural view of a fourth embodiment according to the present invention.

FIG. 9 is a circuit diagram of an example of a fifth embodiment according to the present invention.

FIG. 10 is a sectional structural view of a fifth embodiment according to the present invention.

FIG. 11 is a circuit diagram of one example of a fifth embodiment according to the present invention;

FIG. 12 is a comparison diagram of voltage-current characteristics of die auto.

[Explanation of symbols]

101, 102 Rectifying element 103, 104, 401, 402 Rectifying transistor 105, 106 AC signal input terminal 107, 108 Positive output terminal, negative output terminal 110 Smoothing capacitor 909, 910, 1109, 1110 Bias circuit

Claims (5)

[Claims] A first input terminal for inputting an AC signal; a smoothing capacitor for smoothing a rectified current; a positive output and a negative output connected to the capacitor; and a first input. A first rectifying element connected between a terminal and the positive output, a second rectifying element connected between the second input terminal and the positive output, and the first input terminal. In a rectifier circuit including a third rectifier connected between the negative output and a fourth rectifier connected between the second input terminal and the negative output, The fourth rectifying element is formed of an NMOS transistor. The source and the drain of each NMOS transistor are respectively connected to the first and second input terminals and the negative output terminal, and the first input terminal is connected to the first input terminal. Fourth NMOS transistor Are connected to the gate of the data,
A rectifier circuit, wherein the second input terminal is connected to a gate of a third NMOS transistor. 2. The first and second rectifiers according to claim 1 are constituted by first and second NMOS transistors, respectively, and the source and the drain of each NMOS transistor are first and second inputs, respectively. And the gate of the first NMOS transistor is connected to the first input terminal, and the gate of the second NMOS transistor is connected to the second input terminal. Rectifier circuit characterized. 3. The rectifier according to claim 2, wherein the first and second NMOS transistors have a smaller gate oxide film thickness than the gate oxide film thickness of the third and fourth NMOS transistors. . 4. The first and second NMOS transistors according to claim 2, wherein the threshold voltage of the NM is lower than the threshold voltage of the third and fourth NMOS transistors.
A rectifier having an OS transistor. 5. The first and second rectifiers according to claim 1 are composed of first and second NMOS transistors, respectively, and the source and the drain of each NMOS transistor are first and second inputs, respectively. And a gate voltage of the first NMOS transistor with respect to an input voltage of the second input terminal.
A bias circuit for maintaining a voltage difference corresponding to a threshold voltage of the transistor, and a bias for constantly maintaining a gate voltage of the second NMOS transistor at a voltage difference corresponding to a threshold voltage of the NMOS transistor with respect to an input voltage of the first input terminal; A rectifier circuit characterized by having a circuit.