JP2013533122A - 平坦構造の電子部品及びその製造方法 - Google Patents
平坦構造の電子部品及びその製造方法 Download PDFInfo
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- JP2013533122A JP2013533122A JP2013510581A JP2013510581A JP2013533122A JP 2013533122 A JP2013533122 A JP 2013533122A JP 2013510581 A JP2013510581 A JP 2013510581A JP 2013510581 A JP2013510581 A JP 2013510581A JP 2013533122 A JP2013533122 A JP 2013533122A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R19/00—Electrostatic transducers
- H04R19/005—Electrostatic transducers using semiconductor materials
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/02—Casings; Cabinets ; Supports therefor; Mountings therein
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
Abstract
【選択図】図1
Description
・基板を貫通する切欠を備える基板を提供するステップ,
・第1チップを提供するステップ,
・前記基板をサポートフィルム上に配置するステップ,
・前記第1チップを前記切欠内部に配置するステップ,及び
・前記第1チップを前記切欠内部に固定するステップ。
・カバーフィルムを提供するステップ,
・前記カバーフィルムから蓋を構成するステップ,及び
・前記蓋を,前記基板又は前記チップの一部の上に配置するステップ。
AD: カバー
AU: 切欠
BD: ボンディングワイヤ
BE: コーティング
CH1: 第1チップ
DE: 蓋
DK: スルーコンタクト
DS: 誘電体層
EB: 電子部品
EK: 外部コンタクト面
HFO: サポートフィルム
IE: インダクタンス素子
KE: キャパシタンス素子
KL: 接着剤
KS: 接着剤層
LB: 導体路
ME: メンブレン
MS: メタライジング層
OC: チップ表面
OT: 基板表面
RP: バックプレート
RV: 背面容積
SEO: 音波入力開口部
SP: 開口部
TR: 基板
Claims (10)
- 平坦構造を有する電子部品(EB)であって,
・切欠(AU)と,第1チップ(CH1)と,外部コンタクト面(EK)とを有する基板(TR)を備え,
・前記切欠(AH)が前記基板(TR)を貫通し,
・前記第1チップ(CH1)が前記切欠(AU)内部に配置され,
・前記外部コンタクト面(EK)が,前記第1チップ(CH1)を外部スイッチ手段に接続するために設けられている電子部品。 - 請求項1に記載の電子部品であって,更に接着剤(KL)を備え,該接着剤(KL)が,前記第1チップ(CH1)と前記切欠(AU)との間の開口部(SP)内部に配置されて前記第1チップ(CH1)を前記基板(TR)に結合する電子部品。
- 請求項1又は2に記載の電子部品であって,更にコーティング(BE)を備え,該コーティング(BE)が,前記基板(TR)の表面(OT)又は前記第1チップの表面(OC)の一部に施されて,該表面(OT,OC)の前記一部に対する前記接着剤(KL)の塗布を支援する電子部品。
- 請求項1から3の何れか一項に記載の電子部品であって,更に蓋(DE)を備え,該蓋(DE)が,前記基板(TR)の上側の一部,又は前記第1チップ(CH1)の上側の一部を覆う電子部品。
- 請求項1から4の何れか一項に記載の電子部品であって,
・前記基板(TR)が,2層の誘電体層(DS)と,これら誘電体層(DS)の間に配置されたメタライジング層(MS)とを有する多層構造であり,
・前記メタライジング層(MS)に導体路(LB)又はインピーダンス素子(IE,KE)が構造化され,
・前記第1チップ(CH1),前記インピーダンス素子(IE,KE)及び前記外部コンタクト面(EK)が内部接続により接続される電子部品。 - 請求項1から5の何れか一項に記載の電子部品であって,更にASICチップ(AC)を備え,該ASICチップ(AC)が,前記基板(TR)に固定され,かつ,内部接続により前記第1チップ(CH1)と接続する電子部品。
- 請求項1から6の何れか一項に記載の電子部品であって,
・前記第1チップ(CH1)がメンブレン(ME)及びバックプレート(RP)を備えるMEMSチップであり,
・前記基板(TR)又は前記MEMSチップ(CH1)内部に背面容積(RV)が配置され,
・前記電子部品がマイクロフォンである電子部品。 - 平坦構造を有する電子部品を製造する方法であって,
・切欠(AU)を貫通させた基板(TR)を準備するステップと,
・第1チップ(CH1)を準備するステップと,
・前記基板(TR)を支持フィルム(HFO)上に配置するステップと,
・前記第1チップ(CH1)を前記切欠(AU)内部に配置するステップと,
・前記第1チップ(CH1)を前記切欠(AU)内部に固定するステップと,
を含む方法。 - 請求項8に記載の方法であって,
前記支持フィルム(HFO)が,前記基板(TR)及び前記チップ(CH1)に対向する側に接着剤層(KS)を備える方法。 - 請求項9に記載の方法であって,更に,
・カバーフィルムを準備するステップと,
・該カバーフィルムから蓋(DE)を構造化するステップと,
・該蓋(DE)を,前記基板(TR)又は前記チップ(CH1)の一部の上に配置するステップとを含む方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010022204.6 | 2010-05-20 | ||
DE102010022204.6A DE102010022204B4 (de) | 2010-05-20 | 2010-05-20 | Elektrisches Bauelement mit flacher Bauform und Herstellungsverfahren |
PCT/EP2011/057889 WO2011144570A1 (de) | 2010-05-20 | 2011-05-16 | Elektrisches bauelement mit flacher bauform und herstellungsverfahren |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013533122A true JP2013533122A (ja) | 2013-08-22 |
JP5903094B2 JP5903094B2 (ja) | 2016-04-13 |
Family
ID=44486433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013510581A Expired - Fee Related JP5903094B2 (ja) | 2010-05-20 | 2011-05-16 | 平坦構造の電子部品及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9084366B2 (ja) |
JP (1) | JP5903094B2 (ja) |
KR (1) | KR101761967B1 (ja) |
CN (1) | CN102893632B (ja) |
DE (1) | DE102010022204B4 (ja) |
WO (1) | WO2011144570A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016521036A (ja) * | 2013-03-28 | 2016-07-14 | ノールズ エレクトロニクス,リミテッド ライアビリティ カンパニー | 後方容量を増やしたmems装置 |
WO2018021096A1 (ja) * | 2016-07-29 | 2018-02-01 | 国立大学法人東北大学 | マイクロフォン、電子機器及びパッケージング方法 |
JP2021047203A (ja) * | 2020-12-10 | 2021-03-25 | ローム株式会社 | 電子部品 |
CN112973814A (zh) * | 2021-03-03 | 2021-06-18 | 北京理工大学 | 一种用于多层微流控芯片的层间自动对准键合装置及方法 |
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US8542850B2 (en) | 2007-09-12 | 2013-09-24 | Epcos Pte Ltd | Miniature microphone assembly with hydrophobic surface coating |
DE102007058951B4 (de) | 2007-12-07 | 2020-03-26 | Snaptrack, Inc. | MEMS Package |
DE102010006132B4 (de) | 2010-01-29 | 2013-05-08 | Epcos Ag | Miniaturisiertes elektrisches Bauelement mit einem Stapel aus einem MEMS und einem ASIC |
CN103545303B (zh) * | 2012-07-17 | 2018-02-09 | 马维尔国际贸易有限公司 | 集成电路封装体组件、用于组装印刷电路板的方法 和集成电路封装体 |
DE102018216282A1 (de) * | 2018-09-25 | 2020-03-26 | Robert Bosch Gmbh | Verfahren zur Herstellung eines MEMS-Sensors |
CN113573220B (zh) * | 2021-07-28 | 2023-01-03 | 杭州安普鲁薄膜科技有限公司 | 一种带有防尘透声膜组件的mems复合件 |
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2010
- 2010-05-20 DE DE102010022204.6A patent/DE102010022204B4/de active Active
-
2011
- 2011-05-16 CN CN201180024653.8A patent/CN102893632B/zh not_active Expired - Fee Related
- 2011-05-16 JP JP2013510581A patent/JP5903094B2/ja not_active Expired - Fee Related
- 2011-05-16 US US13/698,350 patent/US9084366B2/en active Active
- 2011-05-16 KR KR1020127033168A patent/KR101761967B1/ko active IP Right Grant
- 2011-05-16 WO PCT/EP2011/057889 patent/WO2011144570A1/de active Application Filing
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2016521036A (ja) * | 2013-03-28 | 2016-07-14 | ノールズ エレクトロニクス,リミテッド ライアビリティ カンパニー | 後方容量を増やしたmems装置 |
WO2018021096A1 (ja) * | 2016-07-29 | 2018-02-01 | 国立大学法人東北大学 | マイクロフォン、電子機器及びパッケージング方法 |
JPWO2018021096A1 (ja) * | 2016-07-29 | 2019-08-08 | 国立大学法人東北大学 | マイクロフォン、電子機器及びパッケージング方法 |
JP2021168497A (ja) * | 2016-07-29 | 2021-10-21 | 国立大学法人東北大学 | マイクロフォンと電子機器 |
JP7551806B2 (ja) | 2016-07-29 | 2024-09-17 | スカイワークス ソリューションズ,インコーポレイテッド | マイクロフォンと電子機器 |
JP2021047203A (ja) * | 2020-12-10 | 2021-03-25 | ローム株式会社 | 電子部品 |
JP6991300B2 (ja) | 2020-12-10 | 2022-01-12 | ローム株式会社 | 電子部品 |
CN112973814A (zh) * | 2021-03-03 | 2021-06-18 | 北京理工大学 | 一种用于多层微流控芯片的层间自动对准键合装置及方法 |
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Publication number | Publication date |
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US9084366B2 (en) | 2015-07-14 |
US20130121523A1 (en) | 2013-05-16 |
WO2011144570A1 (de) | 2011-11-24 |
KR20130113339A (ko) | 2013-10-15 |
CN102893632A (zh) | 2013-01-23 |
DE102010022204A1 (de) | 2011-11-24 |
DE102010022204B4 (de) | 2016-03-31 |
KR101761967B1 (ko) | 2017-08-04 |
CN102893632B (zh) | 2016-11-02 |
DE102010022204A8 (de) | 2012-05-16 |
JP5903094B2 (ja) | 2016-04-13 |
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