JP2013533122A - Flat structure electronic component and manufacturing method thereof - Google Patents
Flat structure electronic component and manufacturing method thereof Download PDFInfo
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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Abstract
本発明は,電子部品及びその製造方法を提案する。本発明に係る電子部品は基板を備え,この基板は,基板を貫通する切欠と,第1チップと,外部コンタクト面とを有する。第1チップは,基板の切欠内部に配置する。第1チップを外部のスイッチ環境と接続するために,外部コンタクト面が設けられている。
【選択図】図1The present invention proposes an electronic component and a manufacturing method thereof. The electronic component according to the present invention includes a substrate, and the substrate includes a notch penetrating the substrate, a first chip, and an external contact surface. The first chip is disposed inside the notch of the substrate. An external contact surface is provided to connect the first chip to an external switch environment.
[Selection] Figure 1
Description
本発明は平坦構造の電子部品及びその製造方法に関するものである。 The present invention relates to an electronic component having a flat structure and a method for manufacturing the same.
電子部品に対しては,小型化やコスト削減等の要求が高まっている。最新の電子部品は,多面取りプロセスにより,及び/又はウエハを使用することにより,高い費用対効果をもって製造することができる。このような電子部品はマイクロフォン,例えばMEMSマイクロフォンとして使用可能である。 For electronic parts, there are increasing demands for downsizing and cost reduction. Modern electronic components can be manufactured cost-effectively by a multi-chamfer process and / or by using wafers. Such an electronic component can be used as a microphone, for example, a MEMS microphone.
ウエハを使用する場合,多面取りでウエハ上に配置する電子部品数を増加させるほど,電子部品をより効率的に製造することができる。特に平坦な電子部品にあっては,1枚のウエハから製造可能な部品総数を増加させるために,薄く大口径のウエハが必要とされる。このようなウエハは,薄膜化又は大口径化するほど機械的に不安定となるため,一定の限度を超えた薄膜化は不可能である。特に,薄いウエハは,欠陥,凹凸及び破損を生じ易い。 When a wafer is used, the electronic components can be manufactured more efficiently as the number of electronic components arranged on the wafer is increased by multi-cavity. Particularly in the case of flat electronic components, a thin and large-diameter wafer is required in order to increase the total number of components that can be manufactured from a single wafer. Since such a wafer becomes mechanically unstable as the film thickness or diameter increases, it is impossible to reduce the film thickness beyond a certain limit. In particular, thin wafers are prone to defects, irregularities and breakage.
特許文献1(米国特許第6781231号明細書)は,MEMSチップが基板上に支持され,キャップで覆われたMEMSマイクロフォンを開示している。 Patent Document 1 (US Pat. No. 6,781,231) discloses a MEMS microphone in which a MEMS chip is supported on a substrate and covered with a cap.
特許文献2(米国特許第6088463号明細書)及び特許文献3(米国特許第6522762号明細書)は,MEMSチップを備える電子部品を開示している。この電子部品においては,基板の両面にチップが配置されている。 Patent Document 2 (US Pat. No. 6,088,463) and Patent Document 3 (US Pat. No. 6,522,762) disclose an electronic component including a MEMS chip. In this electronic component, chips are arranged on both sides of the substrate.
特許文献4(米国特許出願公開第20080279407号公報)は,構造高さを減少させたMEMSマイクロフォンを開示している。 Patent Document 4 (US Patent Application Publication No. 20080279407) discloses a MEMS microphone having a reduced structural height.
上記の特許文献に記載された電子部品の高さは,少なくとも,MEMSチップの高さと,そのMEMSチップを支持する基板の高さとの和に相当する。 The height of the electronic component described in the above patent document corresponds to the sum of at least the height of the MEMS chip and the height of the substrate that supports the MEMS chip.
既知の電子部品,特にMEMS素子の問題点は,しばしば構造高さが過大となることである。 A problem with known electronic components, especially MEMS devices, is that the structural height is often excessive.
従って本発明の課題は,平坦構造の電子部品を,優れた費用対効果をもって製造可能とすることである。特に,電子部品の製造は,部品単価を低減する上で合理的な多面取りプロセスと両立させる必要がある。 Accordingly, an object of the present invention is to make it possible to manufacture an electronic component having a flat structure with excellent cost effectiveness. In particular, the manufacture of electronic components must be compatible with a rational multi-chamfer process in order to reduce the unit cost.
この課題は,本発明に従って,請求項1に記載の電子部品により,又は請求項8に記載の製造方法により解決される。なお,本発明の有利な実施形態は従属請求項に記載したとおりである。 This problem is solved according to the invention by the electronic component according to claim 1 or by the manufacturing method according to claim 8. Advantageous embodiments of the invention are as described in the dependent claims.
電子部品は,切欠と,第1チップと,第1コンタクト面とを有する基板を備える。切欠は基板を貫通し,チップは切欠内部に配置される。外部コンタクト面は,第1チップを外部スイッチ手段と接続するために設けられるものである。 The electronic component includes a substrate having a notch, a first chip, and a first contact surface. The notch penetrates the substrate and the chip is placed inside the notch. The external contact surface is provided to connect the first chip to the external switch means.
電子部品が切欠を有する基板を備え,切欠内部にチップが配置される場合には,機械的安定性を相対的に高めると同時に構造高さを低減することが可能であることを確認した。すなわち,電子部品の全高を算出するために,基板の高さをチップ構成要素の高さに加える必要が無くなる。基板を貫通する切欠内部にチップを配置することにより,本発明に係る電子部品全体の構造高さは,基板及びチップの内,より高い構成要素の高さのみにより規定されるからである。 When the electronic component has a substrate with a notch and the chip is placed inside the notch, it has been confirmed that it is possible to relatively increase the mechanical stability and simultaneously reduce the structural height. That is, it is not necessary to add the height of the substrate to the height of the chip component in order to calculate the total height of the electronic component. This is because the structural height of the entire electronic component according to the present invention is defined only by the height of the higher component of the substrate and the chip by arranging the chip inside the notch penetrating the substrate.
例えば,チップの構造高さが基板の構造高さより高い場合,電子部品の全高がチップの構造高さにより規定される。このような素子は,従来の素子と比較してより厚みのある基板を備えることが可能になる。基板の構造高さが増大しても,基板の全高がチップの全高を下回っている限り,基板の高さは電子部品の全高に対して悪影響を及ぼさないためである。従って,全高の低い構造形態にも関わらず,電子部品の機械的安定性を維持することができる。 For example, when the structural height of the chip is higher than the structural height of the substrate, the total height of the electronic component is defined by the structural height of the chip. Such an element can be provided with a thicker substrate as compared to a conventional element. This is because even if the structural height of the substrate increases, the height of the substrate does not adversely affect the total height of the electronic component as long as the total height of the substrate is lower than the total height of the chip. Accordingly, the mechanical stability of the electronic component can be maintained despite the low-height structure.
原則的には,基板を貫通する切欠により,切欠の無い基板又は切欠が設けられているが貫通していない基板と比較して基板が脆弱化する。これを補償するために基板を厚くし,増加した基板の高さによって,切欠に起因する構造的脆弱性を補償し,電子部品の機械的安定性を高めることが可能である。製造過程における薄膜化工程に関しても,例えば基板及び/又はチップのエッチングにより基板素材が構造的に脆弱化する可能性があるが,このような薄膜化工程を大幅に,又は完全に省くことができる。これは,電子部品が可及的に平坦であるためである。 In principle, a notch that penetrates the substrate weakens the substrate compared to a substrate that has no notch or that has a notch but does not penetrate. In order to compensate for this, it is possible to increase the mechanical stability of the electronic component by increasing the thickness of the substrate and compensating for the structural weakness caused by the notch by the increased substrate height. Regarding the thinning process in the manufacturing process, for example, the substrate material may be structurally weakened by etching the substrate and / or the chip. However, such a thinning process can be greatly or completely omitted. . This is because the electronic component is as flat as possible.
また,薄膜化工程が必要な場合でも,その工程を簡便かつ迅速に行うことが可能である。本発明に係る平坦な電子部品の場合には,初期厚がより厚いために構造的な脆弱化が問題とならず,これにより製造コストを低下させることが可能である。 Further, even when a thinning process is necessary, the process can be performed easily and quickly. In the case of the flat electronic component according to the present invention, since the initial thickness is thicker, structural weakening does not pose a problem, and this can reduce the manufacturing cost.
外部コンタクト面は,チップ表面又は基板表面に配置することが可能である。 The external contact surface can be disposed on the chip surface or the substrate surface.
本発明の一実施形態において,電子部品は接着剤を備え,その接着剤は第1チップと切欠との間の開口部中に塗布されて第1チップを基板に接続する。 In one embodiment of the present invention, the electronic component includes an adhesive, which is applied in an opening between the first chip and the notch to connect the first chip to the substrate.
第1チップは,切欠内に隙間無く適合させることができる。しかし,切欠をチップより大きく形成し,基板とチップの間に開口部を配置しても差し支えない。その場合には,接着剤によって基板をチップに結合する。これにより,機械的な力がチップにより受け止められ,かつ,伝達可能となるため,原則的には基板における構造的弱点である切欠が,チップによって機械的に安定化される。従って,前述した構成に対応する電子部品は,切欠が貫通しているにも関わらず,驚くほど高い機械的安定性を有する。その場合にも,基板を特に厚く形成する必要がある訳ではない。 The first tip can be fitted in the notch without a gap. However, the notch may be formed larger than the chip and an opening may be disposed between the substrate and the chip. In that case, the substrate is bonded to the chip by an adhesive. As a result, mechanical force is received by the chip and can be transmitted, so that the notch, which is a structural weak point in the substrate in principle, is mechanically stabilized by the chip. Therefore, an electronic component corresponding to the above-described configuration has a surprisingly high mechanical stability despite the penetration of the notch. Even in that case, it is not necessary to form the substrate to be particularly thick.
接着剤としては,重合後の最終的な素材特性及び接着特性が,固体の成形剤となる液体樹脂が適用可能である。この場合,硬化剤の添加,加温又は紫外線照射などによって硬化を開始させることも可能である。液体樹脂としては,エポキシ樹脂,シリコン樹脂,フェノール樹脂,ウレタン樹脂,アクリル樹脂などが適用可能である。基板をチップに接続する接着剤としては,ホットメルト接着剤を適用することも可能であるが,その場合には基板及びチップを十分な耐熱性を有する素材で構成する。更に,溶剤系接着剤も接着剤として適当である。 As the adhesive, it is possible to apply a liquid resin that becomes a solid molding agent in terms of final material characteristics and adhesive characteristics after polymerization. In this case, curing can be started by adding a curing agent, heating, or ultraviolet irradiation. As the liquid resin, epoxy resin, silicon resin, phenol resin, urethane resin, acrylic resin, etc. can be applied. As an adhesive for connecting the substrate to the chip, a hot melt adhesive can be applied. In that case, the substrate and the chip are made of a material having sufficient heat resistance. Furthermore, solvent-based adhesives are also suitable as adhesives.
しかしながら,接着剤を使用せず,切欠を施した基板とチップとを機械的に安定した一個の構成素材として接続することも可能である。そのためには,接続前に基板をチップよりも高温に加熱し,熱膨張によって切欠をチップよりも拡げるか,又はチップをより低温に冷却し,同様に縮めるかする。いずれの場合でも,基板の温度をチップの温度よりも高めることとし,その後チップを切欠内部に挿入する。基板とチップの温度が同じになった時点で,切欠内部におけるチップの「座り」が機械的に安定する。
However, it is also possible to connect the notched substrate and the chip as one mechanically stable constituent material without using an adhesive. For this purpose, the substrate is heated to a temperature higher than that of the chip before connection, and the notch is expanded from the chip by thermal expansion, or the chip is cooled to a lower temperature and similarly contracted. In either case, the substrate temperature is set higher than the chip temperature, and then the chip is inserted into the notch. When the temperature of the substrate and the chip becomes the same, the “sitting” of the chip inside the notch is mechanically stabilized.
一実施形態において,電子部品の基板表面又は第1チップ表面の一部分には,コーティングが施される。コーティングは,表面でコーティングが施された部分に,接着剤の塗布が支援されるよう配置される。前述の表面の一部分とは,特に基板をチップに接続するための接着剤が塗布される表面部分が対象となる。 In one embodiment, a coating is applied to a portion of the substrate surface of the electronic component or the first chip surface. The coating is placed on the surface where the coating is applied to assist in applying the adhesive. The above-mentioned part of the surface is particularly a surface portion to which an adhesive for connecting the substrate to the chip is applied.
接着剤として,粘着剤を第1チップと基板の間の開口部に塗布してもよい。基板とチップとの間に配された開口部は,チップの周囲を環状に囲む。しかし,チップを一箇所又は二箇所以上で基板に接触させ,チップと基板との接触部分に開口部を配置し,該接触部分のみに接着剤を塗布してもよい。 As an adhesive, an adhesive may be applied to the opening between the first chip and the substrate. An opening disposed between the substrate and the chip surrounds the chip in a ring shape. However, the chip may be brought into contact with the substrate at one place or two or more places, an opening may be disposed at the contact portion between the chip and the substrate, and the adhesive may be applied only to the contact portion.
チップはカバーを備えてもよい。カバーは基板側,即ち取り付け側に配置するか,又はチップの基板とは反対側に配置することもできる。このようなカバーは,MEMSチップのメンブレン又はバックプレートを保護する。特にMEMSチップの基板側に配されたカバーは,例えば接着剤と接触する前のメンブレン又はバックプレートなどのMEMS機構を保護する。 The chip may include a cover. The cover can be arranged on the substrate side, i.e. on the mounting side, or on the opposite side of the chip from the substrate. Such a cover protects the membrane or back plate of the MEMS chip. In particular, a cover disposed on the substrate side of the MEMS chip protects a MEMS mechanism such as a membrane or a back plate before contacting the adhesive.
接着剤は,例えば直接塗布するか又は噴射してもよい。その際,接着剤をカニューレ又は管などを用いて貯蔵容器から押し出し,又は噴射して基板又はチップ表面の該当部分に塗布することができる。 The adhesive may be applied directly or sprayed, for example. In this case, the adhesive can be applied to a corresponding portion of the substrate or chip surface by extruding or spraying the adhesive from a storage container using a cannula or a tube.
電子部品はコーディングを施される。コーティングによって表面への接着剤の塗布が助長され,接着剤を開口部内で均一に配分することができる。接着剤の配分は,このようなプロセスにより促進する以外に,加熱によっても促進可能である。 Electronic components are coded. The coating facilitates the application of adhesive to the surface and allows the adhesive to be evenly distributed within the opening. In addition to being promoted by such a process, the distribution of adhesive can be promoted by heating.
追加の接着剤貯留部を,更なるチップの取り付け位置に設けてもよい。 Additional adhesive reservoirs may be provided at additional chip attachment locations.
一実施形態において電子部品は蓋を備えており,基板上側の一部分,特に切欠部分,又は第1チップ上側の一部分を覆う。蓋によって基板の上側全体を覆い,それにより第1チップの上側全体を覆うことも可能である。基板は更に,チップを囲んで突出する縁部を備え,蓋は該縁部の上に取り付けられる。従って,蓋と基板の縁部によって空洞が構成され,該空洞内部にチップが配置され,閉鎖される。これによりチップの上側はカプセル封入される。チップの下側も下蓋によって覆われるため,チップは完全にカプセル内部に封入される。 In one embodiment, the electronic component includes a lid and covers a part on the upper side of the substrate, in particular, a notch part or a part on the upper side of the first chip. It is also possible to cover the entire upper side of the substrate with a lid, thereby covering the entire upper side of the first chip. The substrate further comprises an edge projecting around the chip, and the lid is mounted on the edge. Therefore, a cavity is formed by the edge of the lid and the substrate, and the chip is disposed inside the cavity and closed. As a result, the upper side of the chip is encapsulated. Since the lower side of the chip is also covered with the lower lid, the chip is completely enclosed inside the capsule.
蓋は硬質のフィルムを備えてもよく,該フィルムは素子製造の際に,例えばシンプルパネルプロセスにおいて,ラミネート加工される。ハウジング体が平坦である場合,又はチップが基板より高い場合,基板又はチップ表面の該当部分を,キャップ状のカバーで覆うこともできる。 The lid may comprise a hard film, which is laminated during device fabrication, for example in a simple panel process. When the housing body is flat, or when the chip is higher than the substrate, the corresponding part of the substrate or chip surface can be covered with a cap-shaped cover.
一実施形態においては,基板は2層又は複数の誘電体層及びその間に配置されたメタライジング層からなる多層構造とする。メタライジング層上には導体路又はインピーダンス素子を構成する。内部接続によって,第1チップ,インピーダンス素子又は導体路,及び外部コンタクト面が接続される。 In one embodiment, the substrate is a multilayer structure comprising two or more dielectric layers and a metalizing layer disposed therebetween. A conductor path or an impedance element is formed on the metalizing layer. By the internal connection, the first chip, the impedance element or the conductor path, and the external contact surface are connected.
誘電体層は,HTCC(高温共焼成セラミックス多層基板)又はLTCC(低温共焼成セラミックス多層基板)を備えることができる。 The dielectric layer can comprise HTCC (high temperature co-fired ceramic multilayer substrate) or LTCC (low temperature co-fired ceramic multilayer substrate).
多層構造である基板は,更なるコンタクト面を備え,該コンタクト面を介して,導体路又は基板のインピーダンス素子はチップのコンタクト面と接続できる。1面,又は複数の外部コンタクト面を,外部のスイッチ環境との接続のために実装してもよい。 A substrate having a multilayer structure has an additional contact surface, through which the conductor path or the impedance element of the substrate can be connected to the contact surface of the chip. One or more external contact surfaces may be implemented for connection to an external switch environment.
電子部品は,HF(高周波)信号用として構成することができる。その際,多層構造の基板内部におけるインピーダンス素子は,外部コンタクト面又は外部スイッチ手段と,第1チップにおけるその都度該当するスイッチング素子との間でインピーダンス整合又はインピーダンス変換を行うことができる。 Electronic components can be configured for HF (high frequency) signals. At that time, the impedance element inside the multilayer substrate can perform impedance matching or impedance conversion between the external contact surface or the external switch means and the corresponding switching element in the first chip each time.
この場合に内部接続は,導体路に加えてボンディングワイヤ,バンプ接続及びスルーコンタクトを含むことができる。 In this case, the internal connections can include bonding wires, bump connections and through contacts in addition to the conductor tracks.
一実施形態において,電子部品は第1チップに加えて,少なくとも更なる1基のチップを備える。更なるチップは,例えばASICチップ(Application Specific Integrated Circuit)で構成してもよい。一実施形態において,電子部品は基板に固定されたASICチップを備え,内部接続により第1チップと接続する。更なるチップも,更なる切欠の内部に配置される。しかし,通常ICチップは構造高さが例えばMEMSチップよりも低いため,追加されたICチップの高さによって素子の全高が実際に高くなることはない。 In one embodiment, the electronic component comprises at least one additional chip in addition to the first chip. The further chip may be composed of, for example, an ASIC chip (Application Specific Integrated Circuit). In one embodiment, the electronic component includes an ASIC chip fixed to the substrate and is connected to the first chip by an internal connection. A further tip is also placed inside the further notch. However, since the structure height of the IC chip is usually lower than that of the MEMS chip, for example, the total height of the element is not actually increased by the height of the added IC chip.
第1チップは,MEMS素子構造を有するMEMSチップで構成することができる。この場合にASICチップは,素子構造調整のため,又は素子構造から発生するデータ信号の評価のための接続を実装できる。 The first chip can be a MEMS chip having a MEMS element structure. In this case, the ASIC chip can be equipped with a connection for adjusting the element structure or for evaluating a data signal generated from the element structure.
一実施形態において,第1チップはメンブレン及びバックプレートを備えたMEMSチップである。基板又はMEMSチップの内部には,背面容積が配置される。電子部品はマイクロフォンすることが可能であり,従ってこのようなMEMSマイクロフォンは,メンブレンとバックプレートを備えることになり,メンブレンとバックプレートの間は,通常はバイアス電圧が印加される。ASICチップは,バイアス電圧を調整可能とした接続,又は音響信号をコード化する電気信号を評価可能な接続を有する。 In one embodiment, the first chip is a MEMS chip with a membrane and a back plate. A back volume is disposed inside the substrate or MEMS chip. The electronic component can be a microphone, and thus such a MEMS microphone includes a membrane and a back plate, and a bias voltage is usually applied between the membrane and the back plate. The ASIC chip has a connection capable of adjusting a bias voltage or a connection capable of evaluating an electric signal encoding an acoustic signal.
通常MEMSマイクロフォンは,バックプレート又はメンブレンに隣接する背面容積を備えなければならない。通常は,このような背面容積によってMEMSマイクロフォンの構造形状が大型化してしまう。本発明においては,MEMSマイクロフォンの構造形状を平坦とし,例えば閉鎖された容積内部でMEMSチップに実質的に隣接して背面容積を配置するため,特に背面容積が存在することで,MEMSマイクロフォンの全高が必然的に高くなることはない。 Usually the MEMS microphone must have a back volume adjacent to the backplate or membrane. Normally, the structure shape of the MEMS microphone becomes large due to such a back volume. In the present invention, the structure shape of the MEMS microphone is flattened, for example, the back volume is disposed substantially adjacent to the MEMS chip inside the closed volume, and therefore, the total height of the MEMS microphone is obtained particularly by the presence of the back volume. Will not necessarily be high.
三次元の成形体に導体路を設けたデバイス,いわゆるMID(Molded Interconnected Devices)には,素子に内部接続を配置するという更なる可能性がある。基板には,例えばFR4などの有機ラミネートを更に実装可能である。基板の下側又は上側には,例えばSMD(表面実装部品)はんだパッド又はボンディングワイヤパッドなどを外部コンタクト面として配置することができる。 In a device in which a conductor path is provided on a three-dimensional molded body, so-called MID (Molded Interconnected Devices), there is a further possibility that an internal connection is arranged in the element. For example, an organic laminate such as FR4 can be further mounted on the substrate. On the lower side or upper side of the substrate, for example, an SMD (surface mount component) solder pad or a bonding wire pad can be disposed as an external contact surface.
第1チップ又は更なるチップは,例えばASICチップと同様に,ワイヤボンド技術又はフリップチップ技術により内部接続と接続可能である。第1チップを基板と接続する接着剤の残りの接着剤貯留部を基板上の位置に留めて更なるチップを受容可能とすることができる。 The first chip or the further chip can be connected to the internal connection by wire bond technology or flip chip technology, for example, like an ASIC chip. The remaining adhesive reservoir for the adhesive connecting the first chip to the substrate can be held in place on the substrate to accept additional chips.
基板をサポートフィルム上に配置し,次に切欠部分にあってカバーされていないサポートフィルム部分に接着剤を塗布し,その後に切欠内部で接着剤上に第1チップを配置して,基板と第1チップの間の開口部を接着剤で埋めることも可能である。 Place the substrate on the support film, then apply adhesive to the uncovered part of the support film that is in the notch, and then place the first chip on the adhesive inside the notch, It is also possible to fill the opening between one chip with an adhesive.
平坦構造を有する電子部品を製造するための本発明に係る製造方法は,以下のステップを含む:
・基板を貫通する切欠を備える基板を提供するステップ,
・第1チップを提供するステップ,
・前記基板をサポートフィルム上に配置するステップ,
・前記第1チップを前記切欠内部に配置するステップ,及び
・前記第1チップを前記切欠内部に固定するステップ。
A manufacturing method according to the present invention for manufacturing an electronic component having a flat structure includes the following steps:
Providing a substrate with a notch penetrating the substrate;
Providing a first chip,
-Placing the substrate on a support film;
Placing the first tip inside the notch; and fixing the first tip inside the notch.
この方法の一実施形態において,フィルムは,基板及びチップに面した側に,連続するか又は必要に応じて構造化した接着剤層を備える。 In one embodiment of this method, the film comprises a continuous or optionally structured adhesive layer on the side facing the substrate and chip.
これによって,基板及び第1チップをフィルム上で正確に配置し易くなり,特に配置後にずれを生じるリスクが低減される。 This facilitates accurate placement of the substrate and the first chip on the film, and particularly reduces the risk of deviation after placement.
前記方法の一実施形態は,更に以下のステップを含む:
・カバーフィルムを提供するステップ,
・前記カバーフィルムから蓋を構成するステップ,及び
・前記蓋を,前記基板又は前記チップの一部の上に配置するステップ。
One embodiment of the method further includes the following steps:
・ Providing a cover film,
• constructing a lid from the cover film; and • placing the lid on a portion of the substrate or chip.
製造の際に使用されたサポートフィルムは,電子部品の製造後も残留させてもよいが,再び除去してもよい。 The support film used in the manufacture may remain after the electronic component is manufactured, but may be removed again.
基板に適当な溝,貯留部,管又はそれらに類する構造を付与することにより,接着剤を開口部により容易に塗布することができ,開口部内で容易に分散せることができる。 By providing the substrate with appropriate grooves, reservoirs, tubes or similar structures, the adhesive can be easily applied through the openings and can be easily dispersed within the openings.
マイクロフォンの音波入力開口部は,マスキングしたプラズマエッチングによって構成することが可能である。レーザ穴あけの場合,特に斜め方向に照射することでも,音波入力開口部を構成できる。斜め方向照射によって照射レーザが,破損しやすいメンブレンを貫通することを回避することができる。 The sound wave input opening of the microphone can be formed by masked plasma etching. In the case of laser drilling, the sound wave input opening can also be configured by irradiating in an oblique direction. By irradiating in an oblique direction, the irradiation laser can be prevented from penetrating through a membrane that is easily damaged.
以下に本発明に係る電子部品の具体的詳細を,実施形態及びその略図に基づいて詳説する。 Hereinafter, specific details of the electronic component according to the present invention will be described in detail based on the embodiment and its schematic diagram.
図1は,基板TR及び第1チップCH1を備えた電子部品EBを示す。基板TRには切欠AUが設けられており,切欠AUは基板TRを貫通する。更に電子部品EBは,第1チップCH1を外部のスイッチ環境と接続するための外部コンタクト面EKを備える。図1の実施形態に示された第1チップCH1は,MEMSマイクロフォンチップである。第1チップが基板TRを貫通する切欠内部に配置されるため,既知の電子部品と比較して電子部品全体の構造高さが低減され,かつ機械的な安定性は低減されずに済む。 FIG. 1 shows an electronic component EB having a substrate TR and a first chip CH1. The substrate TR is provided with a notch AU, and the notch AU penetrates the substrate TR. Furthermore, the electronic component EB includes an external contact surface EK for connecting the first chip CH1 to an external switch environment. The first chip CH1 shown in the embodiment of FIG. 1 is a MEMS microphone chip. Since the first chip is arranged inside the notch penetrating the substrate TR, the structural height of the entire electronic component is reduced as compared with a known electronic component, and the mechanical stability is not reduced.
図2は,電子部品の基板TRを示し,基板TRには垂直方向に基板TRを貫通する切欠AUが施される。基板TRは表面OTを備える。特に切欠AUを囲む縁部分は,表面OTの垂直方向に屹立する一部によって限定される。切欠AUを限定する基板TRの表面の意義は以下の図において詳説されるものであり,基板TRとチップCH1とを結合する意味合いを持つ。 FIG. 2 shows a substrate TR of an electronic component, and the substrate TR is provided with a notch AU penetrating the substrate TR in the vertical direction. The substrate TR includes a surface OT. In particular, the edge portion surrounding the notch AU is limited by a portion standing upright in the vertical direction of the surface OT. The significance of the surface of the substrate TR that defines the notch AU is described in detail in the following drawings, and has the meaning of coupling the substrate TR and the chip CH1.
図3は基板TRを示し,基板TRはサポートフィルムHFO上に配置される。図3は,製造過程において第1チップCH1が切欠AU内部にまさに挿入される瞬間を示す。第1チップCH1はメンブレンME,バックプレートRPを備える。更にサポートフィルムHFO上には薄い接着剤層KSが配され,接着剤層KSは,基板TR及び第1チップCH1をサポートフィルムHF1上へ配置するのを補助する。第1チップは表面OCを備える。第1チップCHが切欠内部に配置される際,第1チップの表面OC及び基板TRの表面OTの平行部分が,切欠内部で互いに向かい合って屹立する。 FIG. 3 shows the substrate TR, which is disposed on the support film HFO. FIG. 3 shows the moment when the first chip CH1 is just inserted into the notch AU during the manufacturing process. The first chip CH1 includes a membrane ME and a back plate RP. Further, a thin adhesive layer KS is disposed on the support film HFO, and the adhesive layer KS assists in arranging the substrate TR and the first chip CH1 on the support film HF1. The first chip has a surface OC. When the first chip CH is arranged inside the notch, the parallel portions of the surface OC of the first chip and the surface OT of the substrate TR stand up against each other inside the notch.
図4は第1チップCH1を示し,第1チップは基板TRの切欠内部に配置する。第1チップCH1と基板TRとはサポートフィルムHFO上に配置する。第1チップCH1は,基板TRと第1チップCH1との間の開口部SPが,第1チップCH1を閉鎖パスに沿ってとり囲むよう,切欠内部に配置される。 FIG. 4 shows the first chip CH1, and the first chip is arranged inside the cutout of the substrate TR. The first chip CH1 and the substrate TR are disposed on the support film HFO. The first chip CH1 is disposed inside the notch so that the opening SP between the substrate TR and the first chip CH1 surrounds the first chip CH1 along the closed path.
図5は,基板TRをチップに接続する接着剤KLの塗布状況を示す。チップと基板TRは,サポートフィルムHFO上に配置する。チップと基板TRの表面の該当部分は,切欠内部で向かい合って屹立し,コーティングBEを備える。コーティングBEにより,基板TRとチップの表面の対応部分への接着剤KLの塗布が助長される。その際,接着剤KLの硬化後にチップが基板TRと摩擦結合するよう接着剤KLが塗布される。コーティングにより,表面の対応部分への接着剤の塗布が助長される。 FIG. 5 shows the state of application of the adhesive KL that connects the substrate TR to the chip. The chip and the substrate TR are arranged on the support film HFO. Corresponding portions of the surface of the chip and the substrate TR face up in the notch and are provided with a coating BE. The coating BE facilitates the application of the adhesive KL to the corresponding portions of the substrate TR and the surface of the chip. At this time, the adhesive KL is applied so that the chip is frictionally bonded to the substrate TR after the adhesive KL is cured. The coating facilitates the application of adhesive to the corresponding part of the surface.
図6の電子部品においては,チップを囲む閉鎖パスに沿って接着剤KLがチップを基板TRと接続している。電子部品の全構造高さが低減されており,チップが機械的な力を受け,それを伝達可能であるため,同時に機械的安定性も低減されずに済む。 In the electronic component of FIG. 6, the adhesive KL connects the chip to the substrate TR along a closed path that surrounds the chip. The overall structural height of the electronic component is reduced, and the chip receives the mechanical force and can transmit it, so that the mechanical stability is not reduced at the same time.
カバーADは,チップの下側に配置されており,それによって,部品構成,又は例えばメンブレン,背面容積,又はバックプレートといったチップの他の部品が保護される。特に素子構成又は接着剤KLと接触する部品が保護される。また,チップの上側を保護カバーで覆うことも可能である。 The cover AD is located on the underside of the chip, thereby protecting the component configuration or other parts of the chip, such as the membrane, back volume, or back plate. In particular, the component configuration or the parts that come into contact with the adhesive KL are protected. It is also possible to cover the upper side of the chip with a protective cover.
図7は電子部品を示し,第1チップCH1の横に,更なるチップACが備わる。更なるチップACは,ASICチップである。ASICチップは,接着剤KLによって基板と接着する。第1チップCH1及びASICチップACは,ボンディングワイヤBDによって接続される。 FIG. 7 shows an electronic component, and a further chip AC is provided beside the first chip CH1. The further chip AC is an ASIC chip. The ASIC chip is bonded to the substrate with the adhesive KL. The first chip CH1 and the ASIC chip AC are connected by a bonding wire BD.
図8に示した電子部品においては,MEMSチップ及び更なるチップの上側が蓋DEで覆われる。蓋DEは,背面容積RVも覆っている。背面容積RVは,蓋,基板,接着剤及び第1チップにより完全に包囲されているため,電子部品の周囲に対して密閉される。MEMSチップである第1チップは,その下側に音波入力開口部SEOを備える。第1チップCH1がメンブレンME及びバックプレートRPを有することにより,電子部品は,構造高さが平坦で,かつ機械的安定性に優れたMEMSマイクロフォンとなる。 In the electronic component shown in FIG. 8, the upper side of the MEMS chip and the further chip is covered with a lid DE. The lid DE also covers the rear volume RV. Since the back volume RV is completely surrounded by the lid, the substrate, the adhesive, and the first chip, it is sealed against the periphery of the electronic component. The first chip, which is a MEMS chip, includes a sound wave input opening SEO on its lower side. Since the first chip CH1 includes the membrane ME and the back plate RP, the electronic component becomes a MEMS microphone having a flat structure height and excellent mechanical stability.
図9に示した電子部品の配置において,基板TRは多層構造であり,誘電体層DSを備える。誘電体層の間にはメタライジング層MEを配置する。メタライジング層ME上にはキャパシタンス素子KE及びインダクタンス素子IEを構成する。第1チップのコンタクト面は,ボンディングワイヤBDにより基板TRのコンタクト面と接続する。基板TRの内部に配置されたインダクタンス素子IE及びキャパシタンス素子KEは,スルーコンタクトDK又は導体路LBにより,基板TRの下側で外部コンタクト面EKと接続し,ASICチップACとも接続する。多層構造の基板TR内部に配置されたボンディングワイヤBD,インピーダンス素子IE,KE,ASICチップACと基板TR間のバンプ接続と,更に備えられたメタライジングラインとによって電子部品の内部接続が実現される。 In the arrangement of the electronic components shown in FIG. 9, the substrate TR has a multilayer structure and includes a dielectric layer DS. A metallizing layer ME is disposed between the dielectric layers. A capacitance element KE and an inductance element IE are formed on the metalizing layer ME. The contact surface of the first chip is connected to the contact surface of the substrate TR by a bonding wire BD. The inductance element IE and the capacitance element KE arranged inside the substrate TR are connected to the external contact surface EK on the lower side of the substrate TR by the through contact DK or the conductor path LB, and also to the ASIC chip AC. Internal connection of the electronic components is realized by the bonding wires BD, the impedance elements IE, KE, the ASIC chip AC arranged in the multilayer substrate TR, the bump connection between the ASIC chip AC and the substrate TR, and the metallizing line further provided. .
本発明に係る電子部品は,上述した実施形態に限定されるものではない。例えば,更なる接続素子,チップ又は切欠などを含む異なる特徴及び変形の組み合わせも,本発明の実施形態に含まれる。 The electronic component according to the present invention is not limited to the above-described embodiment. For example, combinations of different features and modifications including additional connecting elements, chips or notches are also included in embodiments of the present invention.
AC: ASICチップ
AD: カバー
AU: 切欠
BD: ボンディングワイヤ
BE: コーティング
CH1: 第1チップ
DE: 蓋
DK: スルーコンタクト
DS: 誘電体層
EB: 電子部品
EK: 外部コンタクト面
HFO: サポートフィルム
IE: インダクタンス素子
KE: キャパシタンス素子
KL: 接着剤
KS: 接着剤層
LB: 導体路
ME: メンブレン
MS: メタライジング層
OC: チップ表面
OT: 基板表面
RP: バックプレート
RV: 背面容積
SEO: 音波入力開口部
SP: 開口部
TR: 基板
AC: ASIC chip AD: Cover AU: Notch BD: Bonding wire BE: Coating CH1: First chip DE: Lid DK: Through contact DS: Dielectric layer EB: Electronic component EK: External contact surface HFO: Support film IE: Inductance Element KE: Capacitance element KL: Adhesive KS: Adhesive layer LB: Conductor path ME: Membrane MS: Metalizing layer OC: Chip surface OT: Substrate surface RP: Back plate RV: Back volume SEO: Sound wave input opening SP: Opening part TR: substrate
Claims (10)
・切欠(AU)と,第1チップ(CH1)と,外部コンタクト面(EK)とを有する基板(TR)を備え,
・前記切欠(AH)が前記基板(TR)を貫通し,
・前記第1チップ(CH1)が前記切欠(AU)内部に配置され,
・前記外部コンタクト面(EK)が,前記第1チップ(CH1)を外部スイッチ手段に接続するために設けられている電子部品。 An electronic component (EB) having a flat structure,
A substrate (TR) having a notch (AU), a first chip (CH1), and an external contact surface (EK);
The notch (AH) penetrates the substrate (TR),
The first chip (CH1) is disposed inside the notch (AU),
An electronic component in which the external contact surface (EK) is provided to connect the first chip (CH1) to external switch means.
・前記基板(TR)が,2層の誘電体層(DS)と,これら誘電体層(DS)の間に配置されたメタライジング層(MS)とを有する多層構造であり,
・前記メタライジング層(MS)に導体路(LB)又はインピーダンス素子(IE,KE)が構造化され,
・前記第1チップ(CH1),前記インピーダンス素子(IE,KE)及び前記外部コンタクト面(EK)が内部接続により接続される電子部品。 An electronic component according to any one of claims 1 to 4,
The substrate (TR) has a multilayer structure including two dielectric layers (DS) and a metallizing layer (MS) disposed between the dielectric layers (DS);
A conductor path (LB) or impedance element (IE, KE) is structured in the metalizing layer (MS),
An electronic component in which the first chip (CH1), the impedance element (IE, KE), and the external contact surface (EK) are connected by internal connection.
・前記第1チップ(CH1)がメンブレン(ME)及びバックプレート(RP)を備えるMEMSチップであり,
・前記基板(TR)又は前記MEMSチップ(CH1)内部に背面容積(RV)が配置され,
・前記電子部品がマイクロフォンである電子部品。 The electronic component according to any one of claims 1 to 6,
The first chip (CH1) is a MEMS chip including a membrane (ME) and a back plate (RP);
A rear volume (RV) is disposed inside the substrate (TR) or the MEMS chip (CH1);
-An electronic component in which the electronic component is a microphone.
・切欠(AU)を貫通させた基板(TR)を準備するステップと,
・第1チップ(CH1)を準備するステップと,
・前記基板(TR)を支持フィルム(HFO)上に配置するステップと,
・前記第1チップ(CH1)を前記切欠(AU)内部に配置するステップと,
・前記第1チップ(CH1)を前記切欠(AU)内部に固定するステップと,
を含む方法。 A method of manufacturing an electronic component having a flat structure,
-Preparing a substrate (TR) having a notch (AU) penetrated;
-Preparing a first chip (CH1);
Placing the substrate (TR) on a support film (HFO);
Arranging the first chip (CH1) inside the notch (AU);
Fixing the first chip (CH1) inside the notch (AU);
Including methods.
前記支持フィルム(HFO)が,前記基板(TR)及び前記チップ(CH1)に対向する側に接着剤層(KS)を備える方法。 9. A method according to claim 8, comprising:
A method in which the support film (HFO) includes an adhesive layer (KS) on the side facing the substrate (TR) and the chip (CH1).
・カバーフィルムを準備するステップと,
・該カバーフィルムから蓋(DE)を構造化するステップと,
・該蓋(DE)を,前記基板(TR)又は前記チップ(CH1)の一部の上に配置するステップとを含む方法。 The method of claim 9, further comprising:
-A step of preparing a cover film;
Structuring the lid (DE) from the cover film;
Disposing the lid (DE) on a part of the substrate (TR) or the chip (CH1).
Applications Claiming Priority (3)
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DE102010022204.6 | 2010-05-20 | ||
DE102010022204.6A DE102010022204B4 (en) | 2010-05-20 | 2010-05-20 | Electric component with flat design and manufacturing process |
PCT/EP2011/057889 WO2011144570A1 (en) | 2010-05-20 | 2011-05-16 | Electric component having a shallow physical shape, and method of manufacture |
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JP5903094B2 JP5903094B2 (en) | 2016-04-13 |
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US (1) | US9084366B2 (en) |
JP (1) | JP5903094B2 (en) |
KR (1) | KR101761967B1 (en) |
CN (1) | CN102893632B (en) |
DE (1) | DE102010022204B4 (en) |
WO (1) | WO2011144570A1 (en) |
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US9084366B2 (en) | 2015-07-14 |
CN102893632B (en) | 2016-11-02 |
DE102010022204B4 (en) | 2016-03-31 |
KR101761967B1 (en) | 2017-08-04 |
CN102893632A (en) | 2013-01-23 |
DE102010022204A1 (en) | 2011-11-24 |
KR20130113339A (en) | 2013-10-15 |
US20130121523A1 (en) | 2013-05-16 |
JP5903094B2 (en) | 2016-04-13 |
DE102010022204A8 (en) | 2012-05-16 |
WO2011144570A1 (en) | 2011-11-24 |
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