JP4478312B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4478312B2
JP4478312B2 JP2000311901A JP2000311901A JP4478312B2 JP 4478312 B2 JP4478312 B2 JP 4478312B2 JP 2000311901 A JP2000311901 A JP 2000311901A JP 2000311901 A JP2000311901 A JP 2000311901A JP 4478312 B2 JP4478312 B2 JP 4478312B2
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semiconductor element
resin material
electrode
semiconductor device
wiring surface
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JP2002118206A (en
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憲一 山本
和也 後川
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子と回路形成体とが直接に対向して電気的接続を図りかつ対向する上記半導体素子と上記回路形成体との隙間に樹脂材を供給して上記半導体素子と上記回路形成体とを接合した半導体装置、及び該半導体装置の製造方法に関する。
【０００２】
【従来の技術】
回路基板に半導体素子を搭載して構成される半導体装置の構造として、図１３に示す構造が知られている。
図１３において符号１は半導体素子を示している。図示していないが、この半導体素子１の配線面１ａには集積回路を構成する配線パターンが形成されている。さらにこの半導体素子１上には、予めボールボンディング法あるいはめっき法により突起状の電極３が形成されており、該電極３を回路基板２上の相対する電極４に相向かい合わせし、さらに位置決めして、半導体素子１を回路基板２上に載置する。載置後、樹脂材５を半導体素子１と回路基板２の間隙に注入し、加熱するなどの手法により樹脂５を硬化させる。これにより、半導体素子１を回路基板２に固定し、かつ電極３、４の電極部を保護し、半導体装置６を形成する。
【０００３】
【発明が解決しようとする課題】
近年、特に情報通信の分野においては、通信情報量の増大により、電子機器の処理速度の高速化かつ上記電子機器の高周波動作が要求されており、従って、これらの機器に用いられるキーデバイスである半導体素子そのものを、安定して高速動作及び高周波動作させる必要がある。この一つの解法として、上述のように、半導体素子を回路基板と相向かい合わせにして直接に固定する方法が採られてきた。
【０００４】
しかしながら、上述したような、半導体素子１と回路基板２との間隙に樹脂材５を注入して満たし半導体素子１を回路基板２に固定して半導体装置６の構成を得る従来の方法では、半導体素子１の配線面１ａにおける回路構成部分と樹脂材５とが直接に接触することで、半導体素子１を設計した際に想定している、比誘電率を１にする点が保証されなくなってしまう。従って、半導体素子１のインピーダンスが崩れ、信号の反射が多くなり信号の損失を招き半導体素子１の性能を低下させてしまう。さらに又、誘電正接がゼロではなくなるために、誘電損が発生し、信号の損失、減衰となることから、半導体素子１の性能を低下させ高周波及び高速動作の防げとなるという問題を有していた。
本発明はこのような問題点を解決するためになされたもので、半導体素子と回路形成体とが直接に対向して電気的接続を図りかつ対向する上記半導体素子と上記回路形成体との隙間に樹脂材を供給して上記半導体素子と上記回路形成体とを接合した半導体装置であって、半導体素子の性能低下を防止可能な半導体装置、及び該半導体装置の製造方法を提供することを目的とする。
【０００５】
【課題を解決するための手段】
上記目的を達成するために、本発明は以下のように構成する。
本発明の第１態様の半導体装置は、配線面の周囲に電極を有する半導体素子の上記配線面と回路形成体の装着面とを互いに対向させて、上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接続した半導体装置において、
互いに対向する上記配線面と上記装着面との隙間に対して、上記配線面の上記電極を覆い設けられる樹脂材と、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれて不活性ガスが封入されている性能低下防止空間と、
を備えたことを特徴とする。
【０００７】
又、本発明の別態様の半導体装置は、配線面の周囲に電極を有する半導体素子の上記配線面と回路形成体の装着面とを互いに対向させて、上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接続した半導体装置において、
互いに対向する上記配線面と上記装着面との隙間に対して、上記配線面の上記電極を覆い設けられる樹脂材と、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれて真空状態である性能低下防止空間と、
を備えたことを特徴とする。
【０００８】
上記隙間に設けられ、上記性能低下防止空間を形成する枠体をさらに備えることもできる。
【０００９】
又、本発明の第２態様における半導体装置の製造方法は、配線面の周囲に電極を有する半導体素子の上記配線面と回路形成体の装着面とを直接に対向させた後、上記半導体素子の周囲に樹脂材を設けて上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接合した半導体装置を製造する、半導体装置の製造方法において、
上記半導体素子の周囲に樹脂材を設ける前に、上記半導体素子及び上記回路形成体を真空下に配置し、その後、該真空下にて上記半導体素子の全周囲から上記隙間に向かって上記配線面の上記電極を覆うように同時に上記樹脂材を注入し、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれた真空状態の真空空間を形成する、
ことを特徴とする。
【００１１】
又、本発明の別態様の半導体装置の製造方法は、配線面の周囲に電極を有する半導体素子の上記配線面と回路形成体の装着面とを直接に対向させた後、上記半導体素子の周囲に樹脂材を設けて上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接合した半導体装置を製造する、半導体装置の製造方法において、
上記半導体素子の周囲に樹脂材を設ける前に、上記半導体素子及び上記回路形成体を不活性ガス雰囲気内に配置し、その後、該不活性ガス雰囲気内にて上記半導体素子の全周囲から上記隙間に向かって上記配線面の上記電極を覆うように同時に上記樹脂材を注入し、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれ不活性ガスを封入した不活性ガス空間を形成する、
ことを特徴とする。
【００１２】
上記半導体素子と上記回路形成体とを対向させる前に、上記性能低下防止空間を形成する枠体を上記配線面又は上記装着面に設け、その後、上記半導体素子と上記回路形成体とを対向させ、さらに上記半導体素子の周囲に上記樹脂材を設けて上記隙間に注入して、上記枠体に囲まれた上記性能低下防止空間を形成することもできる。
【００１４】
【発明の実施の形態】
第１実施形態；
本発明の実施形態である半導体装置、及び該半導体装置を製造するための製造方法について、図を参照しながら以下に説明する。尚、各図において、同じ構成部分については同じ符号を付している。又、この明細書で回路形成体とは、樹脂基板、紙−フェノール基板、セラミック基板、ガラス・エポキシ（ガラエポ）基板、フィルム基板等の回路基板、単層基板若しくは多層基板などの回路基板、部品、筐体、又は、フレーム等、回路が形成されている対象物を意味する。
【００１５】
図１及び図２に示す、本実施形態の半導体装置１０１は、いわゆるベアチップの形態にてなる半導体素子１０２と、回路形成体１０３とを突起電極１０４を介在させて接合したものである。該半導体装置１０１では、集積回路が形成されている半導体素子１０２の配線面１０２ａと、上記回路形成体１０３の装着面１０３ａとが互いに対向し、上記配線面１０２ａに形成されている電極１０２１と、上記装着面１０３ａに形成されている電極部１０５とが互いに対向するように、半導体素子１０２と回路形成体１０３とが位置決めされる。又、電極１０２１と電極部１０５との間には、これらを電気的に接続する上記突起電極１０４が設けられている。又、上記配線面１０２ａと上記装着面１０３ａとの間には、隙間１０８が形成される。
【００１６】
このように隙間１０８を介して接合された半導体素子１０２及び回路形成体１０３に対して、さらに両者を固定し、かつ上記電極１０２１、突起電極１０４、及び電極部１０５にてなる接合部を補強及び保護するため、エポキシ系の樹脂材１０６が半導体素子１０２の周囲及び上記隙間１０８に設けられる。又、上記隙間１０８に存在する樹脂材１０６は、上記配線面１０２ａを露出させ半導体素子１０２の性能低下を防止する密閉された性能低下防止空間１０７を有する。
【００１７】
性能低下防止空間１０７は、隙間１０８の内、半導体素子１０２上の配線領域即ち半導体素子１０２の外周部に整列して外部との電気信号の入出力を担う上記電極１０２１よりも内側の領域１０２ｂに存在し、上述のように配線面１０２ａを露出させる。上記内側領域１０２ｂとは、上記電極１０２１よりも内側の領域であって、上記配線面１０２ａにてトランジスタが形成されている領域である。具体的には、本実施形態では、上記トランジスタが形成されている領域が上記電極１０２１よりも約１００μｍ内側に存在することから、上記電極１０２１よりも約１００μｍ内側の領域に相当する。尚、図２は、概略的に上記内側領域１０２ｂを図示したもので、実際の場合に則したものではない。
【００１８】
即ち、上記配線面１０２ａにおける上記内側領域１０２ｂは、性能低下防止空間１０７により、直接に樹脂材１０６と接触しなくなる。つまり、上記内側領域１０２ｂは、性能低下防止空間１０７内の気体と接触する。よって、性能低下防止空間１０７は、従来、半導体素子１の配線面１ａに樹脂材５が直接接触することで生じた、（１）半導体素子１を設計した際に想定している比誘電率を１にする点が保証できず、半導体素子１のインピーダンスが崩れ、信号の反射が多くなり信号の損失を招き半導体素子１の性能を低下させる、（２）半導体素子１の誘電正接がゼロではなくなるために、誘電損が発生し、信号の損失、減衰を起こし半導体素子１の性能を低下させ高周波及び高速動作の防げとなる、という問題を解消することができる。したがって、半導体素子１０２の設計時に想定されている状態すなわち、比誘電率＝１と誘電正接＝０を実現することができ、半導体素子１０２の設計性能を引き出した装着構造を提供することが可能となり、高い性能を有した半導体装置１０１を構成することができる。
【００１９】
このように構成される半導体装置１０１の製造方法について、図３から図５を参照して説明する。
半導体素子１０２に対して、本実施形態では、上記突起電極１０４は、半導体素子１０２の上記電極１０２１上にボールボンディング法やメッキ法等により形成され、上記ボールボンディング法によれば、純度９９％以上の金よりなる線径２５μｍ程度の線材を用いて形成されている。尚、突起電極１０４は、上記電極１０２１上に代えて回路形成体１０３の電極部１０５上に形成してもよい。
【００２０】
このように突起電極１０４を有する半導体素子１０２は、図３及び図４に示すように、半導体素子１０２の電極１０２１と、回路形成体１０３の電極部１０５とが互いに対向するように、即ち突起電極１０４と上記電極部１０５とが対向するように半導体素子１０２と回路形成体１０３とが位置決めされた後、半導体素子１０２が回路形成体１０３に押圧され、上記突起電極１０４と上記電極部１０５とが接合される。このようにして半導体素子１０２と回路形成体１０３とが接合された状態において、２０μｍ〜８０μｍ程度の上記間隙１０８が形成される。
【００２１】
このとき、接合用構造としては図示していないが、回路形成体１０３の電極部１０５上に半田等を予めコーティングしておき、半田の融点以上の温度、一般的には２００℃以上に上記半田を加熱し溶融させ、半導体素子１０２と回路形成体１０３との接合を得ることができる。又、超音波を突起電極１０４と上記電極部１０５との接触部に作用させることでも接合を得ることは可能である。
【００２２】
回路形成体１０３上に上記隙間１０８を介して半導体素子１０２が装着された後、図５に示すように、上記樹脂材１０６を供給する樹脂剤供給装置に備わる注入ノズル１６１にて、半導体素子１０２の周囲から隙間１０８へ樹脂材１０６が供給される。このとき、半導体素子１０２の周囲の４辺から同時に樹脂材１０６を隙間１０８へ注入することで、該隙間１０８の内、半導体素子１０２上の配線領域即ち半導体素子１０２の外周部に整列して外部との電気信号の入出力を担う上記電極１０２１よりも内側の領域１０２ｂに対応して性能低下防止空間１０７を形成することができる。上述のように半導体素子１０２の周囲の４辺から同時に樹脂材１０６が隙間１０８へ注入されることから、形成される性能低下防止空間１０７は、密封された空間となる。
上述の樹脂材注入動作について、半導体素子１０２の大きさが例えば１０ｍｍ角の場合では、樹脂材１０６の塗布開始から５秒程度で注入は完了することができる。
【００２３】
樹脂材１０６の供給を行なうとき、互いに接合された回路形成体１０３及び半導体素子１０２が大気圧の気体中に設けられている場合、半導体素子１０２の周囲の４辺から同時に樹脂材１０６が隙間１０８へ注入されることで、上記隙間１０８にて逃げ場を失った上記気体が封入されて上記性能低下防止空間１０７が形成される。よって、大気圧下の空気中にて樹脂材１０６の供給を行なったときには、上記性能低下防止空間１０７内には上記空気が封入され、例えば窒素等の不活性ガス雰囲気にて樹脂材１０６の供給を行なったときには、上記性能低下防止空間１０７内には上記不活性ガスが封入される。尚、性能低下防止空間１０７内に空気が封入される場合、該空気は、許容量以下に湿気を除去した少なくとも乾燥空気である。
又、上記不活性ガスを封入する場合、例えば、互いに接合された回路形成体１０３及び半導体素子１０２を容器内に設け、該容器内を大気圧の５％以下にまで減圧した後に、例えば窒素等の不活性ガスを上記容器内にパージする方法等を採ることができる。
【００２４】
又、図６に示すように、互いに接合された回路形成体１０３及び半導体素子１０２を真空容器１６５内に設け、真空容器１６５内を真空ポンプ１６６にて真空状態とした状態にて、樹脂材１０６の供給を行なったときには、上記性能低下防止空間１０７内は真空状態とすることができる。尚、この場合、性能低下防止空間１０７内は圧力がほとんどないことから、性能低下防止空間１０７を形成するためには、例えば大気圧のように圧力が存在する場合に比べて、隙間１０８に注入する樹脂材１０６の量の制御をより厳しく行なう必要がある。
又、性能低下防止空間１０７内は、上述のようなほとんど圧力のない真空状態でなくても良く、上記真空容器１６５内を大気圧の１０％以下程度に減圧した状態で性能低下防止空間１０７を形成してもよい。つまり性能低下防止空間１０７内の圧力が大気圧の１０％以下程度でも、上述した効果を得ることが可能である。
【００２５】
上述のように、上記隙間１０８に樹脂材１０６が注入された状態で、特に性能低下防止空間１０７内が真空の場合には真空下にて、例えばエポキシ系の樹脂材１０６の硬化温度である１５０℃程度に加熱することにより樹脂材１０６を硬化させ、突起電極１０２１及び上記電極部１０５部分にてなる接合部を樹脂材１０６により補強、保護し、半導体素子１０２を回路形成体１０３に固定する。
【００２６】
上述のように性能低下防止空間１０７内を不活性ガスや真空状態としたとき、空気を封入した場合に比べて、半導体素子１０２の配線面１０２ａに対して悪影響、例えば空気中の酸素による上記接合部の酸化の進行や水分による腐食を与える可能性が低いことから、より半導体素子１０２の装着信頼性を高めることができる。又、性能低下防止空間１０７内を真空状態としたときには、半導体装置１０１を大気圧で圧縮していることになるので、上記接合部をより強固に保持することが可能となる。
【００２７】
第２実施形態；
上述の第１実施形態では、性能低下防止空間１０７の領域の大きさは、性能低下防止空間１０７内に封入される気体の圧力や、樹脂材１０６の供給量によって制御可能であるが、厳密に規定することは困難である。そこで第２実施形態では、図７に示す半導体装置１１１のように、性能低下防止空間１０７の領域を規定するための枠体１１２を設けて枠体１１２の内側には樹脂材１０６が物理的に進入できないようにした。尚、その他の構造は、上述の半導体装置１０１における構造と変わるところはない。以下に詳しく説明する。
【００２８】
上記半導体装置１１１では、半導体素子１０２上の配線領域即ち該半導体素子１０２の外周部に整列し外部との電気信号の入出力を担う電極１０２１よりも内側の領域である上記内側領域１０２ｂに上記性能低下防止空間１０７が対応するように、図８に示すように、半導体素子１０２の配線面１０２ａ、又は回路形成体１０３の装着面１０３ａ上に枠体１１２を形成する。尚、図８では、装着面１０３ａ上に枠体１１２を形成した場合を示している。
【００２９】
上記枠体１１２は、配線面１０２ａ及び装着面１０３ａと電気的な導通を得ない、エポキシやポリイミド等の樹脂による絶縁材料にてなり、例えば印刷法により、例えば幅１００μｍ程度にて図８に示すように４角の平面形状にて形成される。又、枠体１１２の高さは、半導体素子１０２上に形成した突起電極１０４の高さと同じ、又はその１０％程度まで低い高さを有する。具体的には、ボールボンディング法により形成した突起電極１０４の高さは約５０μｍであることから、枠体１１２の高さは５０μｍ〜４５μｍ程度が好適である。このような高さを有する枠体１１２は、図７に示すように回路形成体１０３上に半導体素子１０２が装着されたとき、上記配線面１０２ａに一端１１２ａが接する。よって枠体１１２の内側、つまり性能低下防止空間１０７は、枠体１１２の外側と遮断される。
尚、枠体１１２の平面形状は、上記４角に限定されず例えば環状等でもよく、上記内側領域１０２ｂに一致若しくは内側領域１０２ｂを超える大きさにて上記性能低下防止空間１０７を形成可能な形状であればよい。
【００３０】
上述のように構成される第２実施形態の半導体装置１１１は、図１０から図１２に示す方法にて製造される。尚、ここでは、上述のように枠体１１２は、回路形成体１０３の装着面１０３ａ上に形成し、突起電極１０４は半導体素子１０２に形成した場合を例に採っている。又、以下の動作説明では、第２実施形態にて特徴的構成部分である上記枠体１１２が関係する動作について述べ、その他の動作については上述の第１実施形態の場合と同様であるので、略説又は説明を省略する。
【００３１】
まず、図１０及び図１１に示すように、装着面１０３ａに予め枠体１１２を形成した回路形成体１０３に対して、半導体素子１０２の突起電極１０４と、回路形成体１０３の電極部１０５とが互いに対向するように、半導体素子１０２が位置決めされる。その後、半導体素子１０２が回路形成体１０３に押圧され、突起電極１０４と上記電極部１０５とが接合される。尚、突起電極１０４と上記電極部１０５とが接合された状態にて、本実施形態では半導体素子１０２側に位置する端部である、枠体１１２の一端１１２ａは、上記配線面１０２ａに接する。
【００３２】
次に、図１２に示すように、上記樹脂材１０６を供給する樹脂剤供給装置に備わる注入ノズル１６１にて、半導体素子１０２の周囲から隙間１０８へ樹脂材１０６が供給される。このとき、本第２実施形態では枠体１１２を設けていることから、該枠体１１２は、性能低下防止空間１０７への樹脂材１０６の進入を妨げるダムの効果を奏し、隙間１０８に対して選択的に樹脂材１０６を注入することが可能になる。よって、上述した第１実施形態の場合のように、半導体素子１０２の周囲の４辺から同時に樹脂材１０６を隙間１０８へ注入する必要は必ずしもない。このように、上記樹脂材１０６の供給により、半導体素子１０２の上記内側領域１０２ｂへ樹脂材１０６を進入させることなく、半導体素子１０２の配線面１０２ａに対して選択的に性能低下防止空間１０７を形成することができる。
尚、樹脂材１０６の注入開始から完了までに要する時間は、半導体素子１０２の大きさが１０ｍｍ角の場合、５秒程度とすることができる。
【００３３】
又、第１実施形態にて説明した真空状態下や不活性ガスの雰囲気にて、半導体素子１０２を回路形成体１０３上に装着して、上述の樹脂材１０６の供給を行なうことで、性能低下防止空間１０７内を、大気圧の空気以外に、真空状態や、不活性ガスとすることもできる。この場合、第１実施形態の半導体装置１０１にて述べたと同様の効果を当該半導体装置１１１も奏することができる。
【００３４】
そして、樹脂材１０６を供給した状態下で、第１実施形態の場合と同様にして樹脂材１０６を硬化させることで、半導体素子１０２の突起電極１０４と回路形成体１０３の電極部１０５との接合部を樹脂材１０６により補強、保護し、半導体素子１０２を回路形成体１０３に固定する。
【００３５】
以上説明したように第２実施形態の半導体装置１１１によれば、枠体１１２を備えたことで半導体装置１０１に比べて、半導体素子１０２の配線面１０２ａに対して選択的に性能低下防止空間１０７を形成することができるとともに、性能低下防止空間１０７の大きさを厳密に規定することができる。よって、半導体装置１０１に比べて、より厳密に比誘電率＝１及び誘電正接＝０を実現可能とする性能低下防止空間１０７を形成することができる。したがって、半導体素子１０２の設計性能をより引き出した装着構造を提供することが可能となり、より実装信頼性が高く、より高い性能を有した半導体装置を構成することが可能となる。
【００３６】
尚、上述した第１実施形態及び第２実施形態の両者において、図１及び図７に示すように、樹脂材１０６は、半導体素子１０２の周囲から塗布が開始されおり半導体素子１０２の全体を覆うように塗布していないが、半導体素子１０２の全体を覆い封止する形で塗布しても良い。
【００３７】
又、上述した第１実施形態及び第２実施形態の両者においては、半導体素子１０２と回路形成体１０３とは突起電極１０４を介して電気的接続を図っているが、該形態に限定されるものではない。即ち、上述のように従来における問題点の発生原因は、半導体素子に形成されている回路部分に樹脂材が直接接触していた点であることから、要するに、上記回路部分に樹脂材が直接に接触するのを防止するように性能低下防止空間を設ければよく、半導体素子１０２と回路形成体１０３との電気的接続の形態は問わない。
【００３８】
【発明の効果】
以上詳述したように本発明の第１態様の半導体装置、及び第２態様の半導体装置の製造方法によれば、半導体素子と回路形成体との隙間に供給される樹脂材に性能低下防止空間を有することで、上記半導体素子に形成された回路部分と上記樹脂材とが直接に接触することはなくなり、上記回路部分は性能低下防止空間に露出する。よって、上記性能低下防止空間を真空状態又は気体状態とすることで、上記半導体素子の特に高速高周波動作時において、上記半導体素子のインピーダンス整合を保証し、インピーダンス不整合による信号の反射や誘電損による信号の損失、減衰を抑制することが可能になる。これにより上記半導体素子の設計性能を発揮した装着性能を実現する装着構造を実現することができる。
【００３９】
上記性能低下防止空間に不活性ガスを封入したり、真空状態とすることで、大気圧の空気を封入している場合に比べて、上記半導体素子の上記回路部分に対して悪影響を与える可能性が低いことから、より半導体素子の装着信頼性を高めることができる。
【００４０】
又、上記性能低下防止空間を形成する枠体をさらに備えることで、上記性能低下防止空間の範囲を厳密に規定することができる。よって、上記枠体を有しない場合に比べて、さらに、上記信号の反射や誘電損による上記信号の損失を抑制することが可能となる。
【図面の簡単な説明】
【図１】 本発明の第１実施形態にかかる半導体装置の縦断面図である。
【図２】 図１に示す半導体装置の横断面図である。
【図３】 図１に示す半導体装置の製造動作を示す図であって、半導体素子を回路形成体へ装着する直前の状態を示す図である。
【図４】 図１に示す半導体装置の製造動作を示す図であって、半導体素子を回路形成体へ装着した状態を示す図である。
【図５】 図１に示す半導体装置の製造動作を示す図であって、半導体素子と回路形成体との隙間へ樹脂材を供給している状態を示す図である。
【図６】 図１に示す半導体装置に備わる性能低下防止空間の内部を真空状態とするための装置構成を説明するための図である。
【図７】 本発明の第２実施形態にかかる半導体装置の縦断面図である。
【図８】 図７に示す半導体装置に備わり回路形成体上に形成された枠体の平面形状を説明するための図である。
【図９】 図７に示す半導体装置の横断面図である。
【図１０】 図７に示す半導体装置の製造動作を示す図であって、半導体素子を回路形成体へ装着する直前の状態を示す図である。
【図１１】 図７に示す半導体装置の製造動作を示す図であって、半導体素子を回路形成体へ装着した状態を示す図である。
【図１２】 図７に示す半導体装置の製造動作を示す図であって、半導体素子と回路形成体との隙間へ樹脂材を供給している状態を示す図である。
【図１３】 従来の半導体装置の横断面図である。
【符号の説明】
１０１…半導体装置、１０２…半導体素子、１０２ａ…配線面、
１０３…回路形成体、１０３ａ…装着面、１０４…突起電極、
１０６…樹脂材、１０７…性能低下防止空間、１０８…隙間、
１１１…半導体装置、１１２…枠体。[0001]
BACKGROUND OF THE INVENTION
According to the present invention, the semiconductor element and the circuit forming body are directly opposed to achieve electrical connection, and a resin material is supplied to a gap between the facing semiconductor element and the circuit forming body to thereby form the semiconductor element and the circuit forming body. The present invention relates to a semiconductor device joined to a body and a method for manufacturing the semiconductor device.
[0002]
[Prior art]
As a structure of a semiconductor device configured by mounting a semiconductor element on a circuit board, a structure shown in FIG. 13 is known.
In FIG. 13, reference numeral 1 denotes a semiconductor element. Although not shown, a wiring pattern constituting an integrated circuit is formed on the wiring surface 1 a of the semiconductor element 1. Further, a protruding electrode 3 is formed in advance on the semiconductor element 1 by a ball bonding method or a plating method. The electrode 3 is opposed to the opposing electrode 4 on the circuit board 2 and further positioned. Then, the semiconductor element 1 is placed on the circuit board 2. After mounting, the resin material 5 is cured by a technique such as injecting the resin material 5 into the gap between the semiconductor element 1 and the circuit board 2 and heating. Thereby, the semiconductor element 1 is fixed to the circuit board 2 and the electrode portions of the electrodes 3 and 4 are protected to form the semiconductor device 6.
[0003]
[Problems to be solved by the invention]
In recent years, especially in the field of information communication, due to an increase in the amount of communication information, there has been a demand for higher processing speed of electronic devices and higher-frequency operation of the electronic devices. Therefore, this is a key device used for these devices. The semiconductor element itself needs to be stably operated at high speed and high frequency. As one solution to this problem, as described above, a method of directly fixing a semiconductor element facing a circuit board has been adopted.
[0004]
However, in the conventional method for obtaining the configuration of the semiconductor device 6 by filling the resin material 5 into the gap between the semiconductor element 1 and the circuit board 2 and filling the semiconductor element 1 to the circuit board 2 as described above, Since the circuit components on the wiring surface 1a of the element 1 and the resin material 5 are in direct contact with each other, it is not guaranteed that the relative dielectric constant is assumed to be 1 when the semiconductor element 1 is designed. . Therefore, the impedance of the semiconductor element 1 is collapsed, signal reflection is increased, signal loss is caused, and the performance of the semiconductor element 1 is deteriorated. Furthermore, since the dielectric loss tangent is no longer zero, dielectric loss occurs, resulting in signal loss and attenuation. This has the problem of reducing the performance of the semiconductor element 1 and preventing high frequency and high speed operation. It was.
The present invention has been made to solve such a problem, and the semiconductor element and the circuit forming body are directly opposed to each other to achieve electrical connection and the gap between the facing semiconductor element and the circuit forming body. An object of the present invention is to provide a semiconductor device in which a resin material is supplied to join the semiconductor element and the circuit forming body, and a semiconductor device capable of preventing performance degradation of the semiconductor element, and a method for manufacturing the semiconductor device. And
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
In the semiconductor device according to the first aspect of the present invention, the wiring surface of the semiconductor element having an electrode around the wiring surface and the mounting surface of the circuit forming body face each other, and the electrode of the semiconductor element and the circuit forming body are arranged. in the semi-conductor device connecting the electrode portion electrical manner,
Relative gap between the wiring surface and the instrumentation Chakumen we face each other, and resin material is provided to cover the electrode of the wiring surface,
A performance deterioration prevention space surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material and filled with an inert gas ,
It is provided with.
[0007]
According to another aspect of the present invention, there is provided a semiconductor device in which the wiring surface of the semiconductor element having electrodes around the wiring surface and the mounting surface of the circuit forming body are opposed to each other to form the electrode and the circuit of the semiconductor element. in the semi-conductor device connected to the electrode portion of the body electrical manner,
Relative gap between the wiring surface and the instrumentation Chakumen we face each other, and resin material is provided to cover the electrode of the wiring surface,
A performance degradation preventing space that is surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material, and in a vacuum state ,
It is provided with.
[0008]
A frame body provided in the gap and forming the performance deterioration preventing space may be further provided.
[0009]
In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the wiring surface of the semiconductor element having electrodes around the wiring surface and the mounting surface of the circuit forming body are directly opposed to each other. the resin material is provided for manufacturing a semiconductor device electrically connected to the electrode portion of the electrode and the circuit forming body of the semiconductor device around, in the method of manufacturing a semiconductor device,
Before around the upper Symbol semiconductor device provided resin material, the semiconductor element and the circuit forming body was placed under vacuum, then the wiring from the entire periphery of the semiconductor element in the vacuum under towards the gap Injecting the resin material at the same time so as to cover the electrode of the surface ,
Forming a vacuum vacuum space surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material ;
It is characterized by that.
[0011]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein the wiring surface of a semiconductor element having electrodes around the wiring surface and the mounting surface of the circuit forming body are directly opposed to each other, the resin material is provided for manufacturing a semiconductor device electrically connected to the electrode portion of the electrode and the circuit forming body of the semiconductor device, method of manufacturing a semiconductor device,
Before around the upper Symbol semiconductor device provided resin material, the semiconductor element and the circuit forming body was placed in an inert gas atmosphere, then the the whole periphery of the semiconductor element in the inert gas atmosphere Injecting the resin material at the same time so as to cover the electrode on the wiring surface toward the gap ,
Forming an inert gas space surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material and enclosing an inert gas ;
It is characterized by that.
[0012]
Before the semiconductor element and the circuit forming body are opposed to each other, a frame body that forms the performance deterioration preventing space is provided on the wiring surface or the mounting surface, and then the semiconductor element and the circuit forming body are opposed to each other. Further, the resin material may be provided around the semiconductor element and injected into the gap to form the performance deterioration preventing space surrounded by the frame.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
1st Embodiment;
A semiconductor device according to an embodiment of the present invention and a manufacturing method for manufacturing the semiconductor device will be described below with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected about the same component. In this specification, the circuit forming body means a resin substrate, a paper-phenol substrate, a ceramic substrate, a glass / epoxy (glass epoxy) substrate, a circuit substrate such as a film substrate, a circuit substrate such as a single layer substrate or a multilayer substrate, and a component. Means an object on which a circuit is formed, such as a housing or a frame.
[0015]
A semiconductor device 101 of this embodiment shown in FIGS. 1 and 2 is obtained by joining a semiconductor element 102 in the form of a so-called bare chip and a circuit forming body 103 with protruding electrodes 104 interposed therebetween. In the semiconductor device 101, the wiring surface 102a of the semiconductor element 102 on which the integrated circuit is formed and the mounting surface 103a of the circuit forming body 103 are opposed to each other, and the electrode 1021 formed on the wiring surface 102a; The semiconductor element 102 and the circuit forming body 103 are positioned so that the electrode portions 105 formed on the mounting surface 103a face each other. Further, the protruding electrode 104 is provided between the electrode 1021 and the electrode portion 105 to electrically connect them. A gap 108 is formed between the wiring surface 102a and the mounting surface 103a.
[0016]
In this way, the semiconductor element 102 and the circuit forming body 103 joined together through the gap 108 are further fixed, and the joining portion composed of the electrode 1021, the protruding electrode 104, and the electrode portion 105 is reinforced and In order to protect, an epoxy resin material 106 is provided around the semiconductor element 102 and in the gap 108. The resin material 106 present in the gap 108 has a sealed performance deterioration prevention space 107 that exposes the wiring surface 102 a and prevents the performance degradation of the semiconductor element 102.
[0017]
The performance degradation preventing space 107 is arranged in a region 102 b inside the gap 102, which is aligned with the wiring region on the semiconductor element 102, that is, the outer periphery of the semiconductor element 102, and which is in charge of input / output of electric signals to / from the outside. Exists and exposes the wiring surface 102a as described above. The inner region 102b is a region inside the electrode 1021, and is a region where a transistor is formed on the wiring surface 102a. Specifically, in this embodiment, since the region where the transistor is formed is located about 100 μm inside the electrode 1021, it corresponds to a region about 100 μm inside the electrode 1021. Note that FIG. 2 schematically illustrates the inner region 102b, and does not conform to an actual case.
[0018]
That is, the inner region 102 b on the wiring surface 102 a does not directly contact the resin material 106 due to the performance deterioration preventing space 107. That is, the inner region 102b comes into contact with the gas in the performance deterioration prevention space 107. Therefore, the performance degradation preventing space 107 is generated by the resin material 5 being in direct contact with the wiring surface 1a of the semiconductor element 1, and (1) the relative dielectric constant assumed when the semiconductor element 1 is designed. 1 cannot be guaranteed, the impedance of the semiconductor element 1 collapses, the signal reflection increases, the signal is lost, and the performance of the semiconductor element 1 is degraded. (2) The dielectric tangent of the semiconductor element 1 is not zero Therefore, it is possible to solve the problem that dielectric loss occurs, signal loss and attenuation occur, the performance of the semiconductor element 1 is lowered, and high frequency and high speed operation is prevented. Therefore, the state assumed at the time of designing the semiconductor element 102, that is, the relative permittivity = 1 and the dielectric loss tangent = 0 can be realized, and it is possible to provide a mounting structure that draws out the design performance of the semiconductor element 102. Thus, the semiconductor device 101 having high performance can be configured.
[0019]
A method for manufacturing the semiconductor device 101 configured as described above will be described with reference to FIGS.
In contrast to the semiconductor element 102, in the present embodiment, the protruding electrode 104 is formed on the electrode 1021 of the semiconductor element 102 by a ball bonding method, a plating method, or the like. According to the ball bonding method, the purity is 99% or more. It is formed using a wire rod having a wire diameter of about 25 μm made of gold. The protruding electrode 104 may be formed on the electrode portion 105 of the circuit forming body 103 in place of the electrode 1021.
[0020]
As shown in FIGS. 3 and 4, the semiconductor element 102 having the protruding electrode 104 is formed so that the electrode 1021 of the semiconductor element 102 and the electrode portion 105 of the circuit forming body 103 face each other, that is, the protruding electrode. After the semiconductor element 102 and the circuit forming body 103 are positioned so that the electrode 104 and the electrode portion 105 face each other, the semiconductor element 102 is pressed against the circuit forming body 103, and the protruding electrode 104 and the electrode portion 105 are Be joined. Thus, in the state where the semiconductor element 102 and the circuit forming body 103 are joined, the gap 108 of about 20 μm to 80 μm is formed.
[0021]
At this time, although not shown as a bonding structure, solder or the like is coated on the electrode portion 105 of the circuit forming body 103 in advance, and the solder is heated to a temperature equal to or higher than the melting point of the solder, generally 200 ° C. or higher. The semiconductor element 102 and the circuit forming body 103 can be joined by heating and melting. It is also possible to obtain bonding by applying an ultrasonic wave to the contact portion between the protruding electrode 104 and the electrode portion 105.
[0022]
After the semiconductor element 102 is mounted on the circuit forming body 103 through the gap 108, as shown in FIG. 5, the semiconductor element 102 is injected by an injection nozzle 161 provided in a resin agent supply device for supplying the resin material 106. The resin material 106 is supplied to the gap 108 from the periphery. At this time, by simultaneously injecting the resin material 106 into the gap 108 from the four sides around the semiconductor element 102, the gap 108 is aligned with the wiring region on the semiconductor element 102, that is, the outer periphery of the semiconductor element 102. The performance deterioration preventing space 107 can be formed corresponding to the region 102b inside the electrode 1021 that is responsible for input / output of the electrical signal. As described above, since the resin material 106 is simultaneously injected into the gap 108 from the four sides around the semiconductor element 102, the formed performance degradation prevention space 107 is a sealed space.
Regarding the above-described resin material injection operation, when the size of the semiconductor element 102 is, for example, 10 mm square, the injection can be completed in about 5 seconds from the start of application of the resin material 106.
[0023]
When supplying the resin material 106, when the circuit formation body 103 and the semiconductor element 102 bonded to each other are provided in a gas at atmospheric pressure, the resin material 106 is simultaneously spaced from the four sides around the semiconductor element 102. As a result, the gas that has lost its escape from the gap 108 is sealed, and the performance degradation preventing space 107 is formed. Therefore, when the resin material 106 is supplied in air under atmospheric pressure, the air is sealed in the performance deterioration prevention space 107, and the resin material 106 is supplied in an inert gas atmosphere such as nitrogen, for example. Is performed, the inert gas is sealed in the performance deterioration prevention space 107. In addition, when air is enclosed in the performance deterioration prevention space 107, the air is at least dry air from which moisture has been removed to an allowable amount or less.
When the inert gas is sealed, for example, the circuit forming body 103 and the semiconductor element 102 bonded to each other are provided in a container, and the container is depressurized to 5% or less of the atmospheric pressure. A method of purging the inert gas into the container can be employed.
[0024]
In addition, as shown in FIG. 6, the circuit forming body 103 and the semiconductor element 102 bonded to each other are provided in a vacuum vessel 165, and the resin material 106 in a state where the vacuum vessel 165 is evacuated by a vacuum pump 166. When the above is supplied, the inside of the performance deterioration preventing space 107 can be in a vacuum state. In this case, since there is almost no pressure in the performance deterioration prevention space 107, in order to form the performance deterioration prevention space 107, it is injected into the gap 108 as compared with the case where pressure exists, for example, at atmospheric pressure. It is necessary to control the amount of the resin material 106 to be strictly controlled.
The performance deterioration prevention space 107 may not be in a vacuum state with almost no pressure as described above, and the performance deterioration prevention space 107 is formed in a state where the inside of the vacuum vessel 165 is reduced to about 10% or less of the atmospheric pressure. It may be formed. That is, even if the pressure in the performance deterioration prevention space 107 is about 10% or less of the atmospheric pressure, the above-described effect can be obtained.
[0025]
As described above, in the state where the resin material 106 is injected into the gap 108, particularly when the inside of the performance deterioration prevention space 107 is vacuum, the curing temperature of the epoxy resin material 106 is 150, for example. The resin material 106 is cured by heating to about 0 ° C., the joint portion including the protruding electrode 1021 and the electrode portion 105 is reinforced and protected by the resin material 106, and the semiconductor element 102 is fixed to the circuit formation body 103.
[0026]
As described above, when the inside of the performance deterioration prevention space 107 is set to an inert gas or a vacuum state, compared with the case where air is sealed, the wiring surface 102a of the semiconductor element 102 is adversely affected, for example, the above-described bonding due to oxygen in the air Since there is a low possibility of causing oxidation of the portion and corrosion due to moisture, the mounting reliability of the semiconductor element 102 can be further improved. In addition, when the inside of the performance degradation preventing space 107 is in a vacuum state, the semiconductor device 101 is compressed at atmospheric pressure, so that the joint portion can be held more firmly.
[0027]
A second embodiment;
In the first embodiment described above, the size of the area of the performance deterioration prevention space 107 can be controlled by the pressure of the gas sealed in the performance deterioration prevention space 107 and the supply amount of the resin material 106. It is difficult to specify. Therefore, in the second embodiment, as in the semiconductor device 111 shown in FIG. 7, a frame body 112 for defining the area of the performance deterioration prevention space 107 is provided, and the resin material 106 is physically disposed inside the frame body 112. Made it impossible to enter. Other structures are not different from those in the semiconductor device 101 described above. This will be described in detail below.
[0028]
In the semiconductor device 111, the performance is added to the wiring region on the semiconductor element 102, that is, the inner region 102 b that is an inner region of the electrode 1021 that is aligned with the outer peripheral portion of the semiconductor element 102 and performs input / output of electric signals to / from the outside. As shown in FIG. 8, a frame body 112 is formed on the wiring surface 102 a of the semiconductor element 102 or the mounting surface 103 a of the circuit forming body 103 so as to correspond to the reduction preventing space 107. FIG. 8 shows the case where the frame body 112 is formed on the mounting surface 103a.
[0029]
The frame body 112 is made of an insulating material made of a resin such as epoxy or polyimide that does not obtain electrical continuity with the wiring surface 102a and the mounting surface 103a, and is shown in FIG. Thus, it is formed in a quadrangular planar shape. The height of the frame body 112 is the same as the height of the protruding electrode 104 formed on the semiconductor element 102 or about 10% of the height. Specifically, since the height of the protruding electrode 104 formed by the ball bonding method is about 50 μm, the height of the frame body 112 is preferably about 50 μm to 45 μm. The frame body 112 having such a height has one end 112a in contact with the wiring surface 102a when the semiconductor element 102 is mounted on the circuit forming body 103 as shown in FIG. Therefore, the inside of the frame body 112, that is, the performance degradation preventing space 107 is blocked from the outside of the frame body 112.
The planar shape of the frame body 112 is not limited to the above four corners, and may be, for example, an annular shape. The shape that can form the performance deterioration preventing space 107 with a size that matches or exceeds the inner region 102b. If it is.
[0030]
The semiconductor device 111 according to the second embodiment configured as described above is manufactured by the method shown in FIGS. Here, as described above, the case where the frame body 112 is formed on the mounting surface 103 a of the circuit formation body 103 and the protruding electrode 104 is formed on the semiconductor element 102 is taken as an example. Further, in the following description of the operation, the operation related to the frame body 112, which is a characteristic component in the second embodiment, will be described, and other operations are the same as those in the above-described first embodiment. Abbreviations or explanations are omitted.
[0031]
First, as shown in FIGS. 10 and 11, the projecting electrode 104 of the semiconductor element 102 and the electrode portion 105 of the circuit forming body 103 are compared with the circuit forming body 103 in which the frame body 112 is previously formed on the mounting surface 103 a. The semiconductor elements 102 are positioned so as to face each other. Thereafter, the semiconductor element 102 is pressed against the circuit forming body 103, and the protruding electrode 104 and the electrode portion 105 are joined. Note that, in a state where the protruding electrode 104 and the electrode portion 105 are joined, one end 112a of the frame body 112, which is an end portion located on the semiconductor element 102 side in this embodiment, is in contact with the wiring surface 102a.
[0032]
Next, as shown in FIG. 12, the resin material 106 is supplied from the periphery of the semiconductor element 102 to the gap 108 by the injection nozzle 161 provided in the resin agent supply device that supplies the resin material 106. At this time, since the frame body 112 is provided in the second embodiment, the frame body 112 exerts the effect of a dam that prevents the resin material 106 from entering the performance deterioration prevention space 107 and prevents the gap 108. The resin material 106 can be selectively injected. Therefore, it is not always necessary to inject the resin material 106 into the gap 108 simultaneously from the four sides around the semiconductor element 102 as in the case of the first embodiment described above. In this way, by supplying the resin material 106, the performance degradation preventing space 107 is selectively formed on the wiring surface 102a of the semiconductor element 102 without causing the resin material 106 to enter the inner region 102b of the semiconductor element 102. can do.
Note that the time required from the start of injection of the resin material 106 to the completion thereof can be about 5 seconds when the size of the semiconductor element 102 is 10 mm square.
[0033]
In addition, the semiconductor element 102 is mounted on the circuit forming body 103 in the vacuum state or inert gas atmosphere described in the first embodiment, and the above-described resin material 106 is supplied. The inside of the prevention space 107 can be in a vacuum state or an inert gas other than air at atmospheric pressure. In this case, the semiconductor device 111 can also exhibit the same effect as described in the semiconductor device 101 of the first embodiment.
[0034]
Then, with the resin material 106 supplied, the resin material 106 is cured in the same manner as in the first embodiment, so that the protruding electrode 104 of the semiconductor element 102 and the electrode portion 105 of the circuit forming body 103 are joined. The portion is reinforced and protected by the resin material 106, and the semiconductor element 102 is fixed to the circuit formation body 103.
[0035]
As described above, according to the semiconductor device 111 of the second embodiment, the provision of the frame body 112 makes it possible to selectively prevent the performance degradation space 107 with respect to the wiring surface 102a of the semiconductor element 102 compared to the semiconductor device 101. Can be formed, and the size of the performance degradation preventing space 107 can be strictly defined. Therefore, compared with the semiconductor device 101, it is possible to form the performance deterioration prevention space 107 that can realize the relative dielectric constant = 1 and the dielectric loss tangent = 0 more strictly. Therefore, it is possible to provide a mounting structure that draws out the design performance of the semiconductor element 102, and it is possible to configure a semiconductor device with higher mounting reliability and higher performance.
[0036]
In both the first embodiment and the second embodiment described above, as shown in FIGS. 1 and 7, the resin material 106 is applied from the periphery of the semiconductor element 102 and covers the entire semiconductor element 102. Although not applied, the entire semiconductor element 102 may be covered and sealed.
[0037]
In both the first embodiment and the second embodiment described above, the semiconductor element 102 and the circuit forming body 103 are electrically connected via the protruding electrode 104, but the invention is limited to this form. is not. In other words, as described above, the cause of the conventional problems is that the resin material is in direct contact with the circuit portion formed in the semiconductor element. A performance deterioration prevention space may be provided so as to prevent the contact, and the form of electrical connection between the semiconductor element 102 and the circuit formation body 103 is not limited.
[0038]
【The invention's effect】
As described above in detail, according to the semiconductor device of the first aspect of the present invention and the method of manufacturing the semiconductor device of the second aspect, the performance degradation preventing space is provided in the resin material supplied to the gap between the semiconductor element and the circuit forming body. Therefore, the circuit portion formed in the semiconductor element and the resin material are not in direct contact with each other, and the circuit portion is exposed to the performance deterioration preventing space. Therefore, by setting the performance degradation prevention space in a vacuum state or a gas state, impedance matching of the semiconductor element is ensured particularly during high-speed high-frequency operation of the semiconductor element, and signal reflection or dielectric loss due to impedance mismatching is ensured. Signal loss and attenuation can be suppressed. As a result, it is possible to realize a mounting structure that realizes a mounting performance that exhibits the design performance of the semiconductor element.
[0039]
There is a possibility that the circuit portion of the semiconductor element will be adversely affected by enclosing an inert gas in the performance-preventing space or by making it in a vacuum state, compared to the case where atmospheric pressure air is encapsulated. Therefore, the mounting reliability of the semiconductor element can be further improved.
[0040]
Moreover, the range of the said performance degradation prevention space can be prescribed | regulated exactly | strictly by further providing the frame which forms the said performance degradation prevention space. Therefore, it is possible to further suppress the loss of the signal due to the reflection of the signal and the dielectric loss as compared with the case where the frame is not provided.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional view of the semiconductor device shown in FIG.
3 is a diagram showing a manufacturing operation of the semiconductor device shown in FIG. 1, and is a diagram showing a state immediately before the semiconductor element is mounted on the circuit formation body. FIG.
4 is a diagram showing a manufacturing operation of the semiconductor device shown in FIG. 1, and is a diagram showing a state in which a semiconductor element is mounted on a circuit formation body. FIG.
5 is a diagram illustrating a manufacturing operation of the semiconductor device illustrated in FIG. 1, and is a diagram illustrating a state in which a resin material is supplied to a gap between the semiconductor element and the circuit formation body. FIG.
6 is a diagram for explaining a device configuration for making the inside of a performance deterioration prevention space provided in the semiconductor device shown in FIG. 1 into a vacuum state; FIG.
FIG. 7 is a longitudinal sectional view of a semiconductor device according to a second embodiment of the present invention.
8 is a diagram for explaining a planar shape of a frame body provided on the circuit formation body in the semiconductor device shown in FIG. 7;
9 is a cross-sectional view of the semiconductor device shown in FIG.
10 is a diagram showing a manufacturing operation of the semiconductor device shown in FIG. 7, and is a diagram showing a state immediately before the semiconductor element is mounted on the circuit formation body. FIG.
11 is a diagram showing a manufacturing operation of the semiconductor device shown in FIG. 7, and is a diagram showing a state in which a semiconductor element is mounted on a circuit forming body. FIG.
12 is a diagram illustrating a manufacturing operation of the semiconductor device illustrated in FIG. 7, and is a diagram illustrating a state in which a resin material is supplied to a gap between the semiconductor element and the circuit forming body.
FIG. 13 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
101 ... Semiconductor device, 102 ... Semiconductor element, 102a ... Wiring surface,
103 ... Circuit forming body, 103a ... Mounting surface, 104 ... Projection electrode,
106: Resin material, 107: Space for preventing performance degradation, 108: Gap,
111... Semiconductor device, 112.

Claims (6)

配線面（１０２ａ）の周囲に電極を有する半導体素子（１０２）の上記配線面と回路形成体（１０３）の装着面（１０３ａ）とを互いに対向させて、上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接続した半導体装置において、
互いに対向する上記配線面と上記装着面との隙間（１０８）に対して、上記配線面の上記電極を覆い設けられる樹脂材（１０６）と、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれて不活性ガスが封入されている性能低下防止空間（１０７）と、
を備えたことを特徴とする半導体装置。 The wiring surface and the circuit forming body of a semiconductor device (102) having an electrode around the mounting surface of the (103) and (103a) are opposed to each other in the wiring surface (102a), the electrode and the circuit formation of the semiconductor element in the semi-conductor device connected to the electrode portion of the body electrical manner,
Relative gap (108) between the wiring surface and the instrumentation Chakumen you face each other, a resin material is provided to cover the electrode of the wiring surface (106),
And the mounting surface, and the resin material, the wiring surface of the inside of the semiconductor element than the electrode covered by the resin material and enclosed by it and performance degradation prevention space inert gas is sealed (107) ,
A semiconductor device comprising: 配線面（１０２ａ）の周囲に電極を有する半導体素子（１０２）の上記配線面と回路形成体（１０３）の装着面（１０３ａ）とを互いに対向させて、上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接続した半導体装置において、
互いに対向する上記配線面と上記装着面との隙間（１０８）に対して、上記配線面の上記電極を覆い設けられる樹脂材（１０６）と、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれて真空状態である性能低下防止空間（１０７）と、
を備えたことを特徴とする半導体装置。 The wiring surface and the circuit forming body of a semiconductor device (102) having an electrode around the mounting surface of the (103) and (103a) are opposed to each other in the wiring surface (102a), the electrode and the circuit formation of the semiconductor element in the semi-conductor device connected to the electrode portion of the body electrical manner,
Relative gap (108) between the wiring surface and the instrumentation Chakumen you face each other, a resin material is provided to cover the electrode of the wiring surface (106),
A performance degradation preventing space (107) in a vacuum state surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material ,
A semiconductor device comprising: 上記隙間に設けられ、上記性能低下防止空間を形成する枠体（１１２）をさらに備えた、請求項１又は２記載の半導体装置。  The semiconductor device according to claim 1, further comprising a frame body (112) provided in the gap and forming the performance deterioration preventing space. 配線面（１０２ａ）の周囲に電極を有する半導体素子（１０２）の上記配線面と回路形成体（１０３）の装着面（１０３ａ）とを直接に対向させた後、上記半導体素子の周囲に樹脂材（１０６）を設けて上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接合した半導体装置を製造する、半導体装置の製造方法において、
上記半導体素子の周囲に樹脂材を設ける前に、上記半導体素子及び上記回路形成体を真空下に配置し、その後、該真空下にて上記半導体素子の全周囲から上記隙間に向かって上記配線面の上記電極を覆うように同時に上記樹脂材を注入し、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれた真空状態の真空空間を形成する、
ことを特徴とする半導体装置の製造方法。After facing the wiring surface and the circuit forming body of a semiconductor device (102) having an electrode mounting surface of the (103) and (103a) directly to the periphery of the wiring surface (102a), the resin material around the semiconductor element (106) the provided manufacturing a semiconductor device electrically connected to the electrode portion of the electrode and the circuit forming body of the semiconductor device, method of manufacturing a semiconductor device,
Before around the upper Symbol semiconductor device provided resin material, the semiconductor element and the circuit forming body was placed under vacuum, then the wiring from the entire periphery of the semiconductor element in the vacuum under towards the gap Injecting the resin material at the same time so as to cover the electrode of the surface ,
Forming a vacuum space in a vacuum state surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material ;
A method for manufacturing a semiconductor device. 配線面（１０２ａ）の周囲に電極を有する半導体素子（１０２）の上記配線面と回路形成体（１０３）の装着面（１０３ａ）とを直接に対向させた後、上記半導体素子の周囲に樹脂材（１０６）を設けて上記半導体素子の上記電極と上記回路形成体の電極部とを電気的に接合した半導体装置を製造する、半導体装置の製造方法において、
上記半導体素子の周囲に樹脂材を設ける前に、上記半導体素子及び上記回路形成体を不活性ガス雰囲気内に配置し、その後、該不活性ガス雰囲気内にて上記半導体素子の全周囲から上記隙間に向かって上記配線面の上記電極を覆うように同時に上記樹脂材を注入し、
上記装着面と、上記樹脂材と、上記樹脂材にて覆われた電極よりも内側の上記半導体素子の配線面とで囲まれ不活性ガスを封入した不活性ガス空間を形成する、
ことを特徴とする半導体装置の製造方法。After facing the wiring surface and the circuit forming body of a semiconductor device (102) having an electrode mounting surface of the (103) and (103a) directly to the periphery of the wiring surface (102a), the resin material around the semiconductor element (106) the provided manufacturing a semiconductor device electrically connected to the electrode portion of the electrode and the circuit forming body of the semiconductor device, method of manufacturing a semiconductor device,
Before around the upper Symbol semiconductor device provided resin material, the semiconductor element and the circuit forming body was placed in an inert gas atmosphere, then the the whole periphery of the semiconductor element in the inert gas atmosphere Injecting the resin material at the same time so as to cover the electrode on the wiring surface toward the gap ,
Forming an inert gas space surrounded by the mounting surface, the resin material, and the wiring surface of the semiconductor element inside the electrode covered with the resin material and enclosing an inert gas ;
A method for manufacturing a semiconductor device. 上記半導体素子と上記回路形成体とを対向させる前に、上記真空空間を形成する枠体（１１２）を上記配線面又は上記装着面に設け、その後、上記半導体素子と上記回路形成体とを対向させ、さらに上記半導体素子の周囲に上記樹脂材を設けて上記隙間に注入して、上記枠体に囲まれた上記真空空間を形成する、請求項４記載の半導体装置の製造方法。Before the semiconductor element and the circuit forming body are opposed to each other, a frame body (112) that forms the vacuum space is provided on the wiring surface or the mounting surface, and then the semiconductor element and the circuit forming body are opposed to each other. It is allowed, and further injected into the gap of the resin material disposed around the semiconductor element, to form the vacuum space surrounded by the frame body, a manufacturing method of a semiconductor device according to claim 4 Symbol mounting.
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