JP2013229100A - ダイナミックマルチモード動作を有する不揮発性メモリ - Google Patents
ダイナミックマルチモード動作を有する不揮発性メモリ Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7206—Reconfiguration of flash memory system
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
Abstract
【解決手段】このフラッシュメモリデバイスは、セルあたり単一ビット(SBC)ストレージモードまたはセルあたり複数ビット(MBC)モードでデータを格納するように動的に構成可能であり、SBCデータとMBCデータとの両方が、同一のメモリアレイ内で共存するようになっている。メモリの各ページに格納された1つまたは複数のタグビットが、対応するサブディビジョンにデータを格納するのに使用されるストレージモードのタイプを示すのに使用され、サブディビジョンは、バンク、ブロック、またはページとすることができる。コントローラが、マルチモードフラッシュメモリデバイスの任意のサブディビジョンの寿命を最大にする目的で、ストレージモードを選択的に変更するために各ページに対応するプログラム-消去サイクル数を監視する。
【選択図】図13
Description
12 制御回路
14 メモリアレイ
20 バンク
22 フラッシュメモリセル
24 ストリング選択デバイス
26 ビット線
28 グラウンド選択デバイス
30 データレジスタ
100 フラッシュメモリシステム
102 ホストシステム
104 フラッシュメモリコントローラ
106 マルチモードフラッシュメモリデバイス
108 チャネル
120 フラッシュメモリシステム
122 フラッシュメモリコントローラ
124 ホストシステム
126 マルチモードフラッシュメモリデバイス
300 マルチモードフラッシュメモリデバイス
302 メモリブロック
304 ページ
306 ページ
308 ページ
310 ページ
312 ページ
314 ページ
315 ページ
316 ページ
317 ページ
318 ページ
320 ページ
322 ページ
324 ページ
350 ユーザデータフィールド
352 予備データフィールド
354 ストレージモードタグ
356 プログラム/消去サイクルカウンタ
358 SBCカウンタ
360 ロックビット
400 フラッシュメモリシステム
402 フラッシュメモリコントローラ
404 マルチモードフラッシュメモリデバイス
405 マルチモード制御回路
406 論理-物理アドレストランスレータ
408 コマンドデコーダ
410 制御論理
412 フラッシュメモリ回路網
414 メモリアレイ
416 MBCコマンドデコーダ
418 SBCコマンドデコーダ
420 共通コマンドデコーダ
Claims (5)
- セルあたり複数ビット(MBC)ページおよびセルあたり単一ビット(SBC)ページを有するNANDフラッシュメモリブロックからデータを読み取る方法であって、
a)前記NANDフラッシュメモリブロックの前記MBCページまたは前記SBCページを読み取るための読取りアドレスを受け取るステップと、
b)前記MBCページに対応するモードタグビットが第1論理状態である場合に、前記読取りアドレスでMBC読取り動作を実行するステップと、
c)前記SBCページに対応する前記モードタグビットが第2論理状態である場合に、前記読取りアドレスでSBC読取り動作を実行するステップと
を含む方法。 - NANDフラッシュメモリデバイスのサブディビジョンにデータをプログラムする方法であって、
第1ストレージモードで前記サブディビジョンにデータをプログラムするステップと、
前記サブディビジョンのプログラム/消去サイクルを監視するステップと、
前記サブディビジョンのプログラム/消去サイクルが所定の限度に達した場合、第2ストレージモードに前記サブディビジョンを変換するステップと、
を含み、
プログラムする前記ステップは、前記サブディビジョンのプログラム/消去サイクルに対応してカウンタを増加させるステップを含み、前記カウンタは、前記NANDフラッシュメモリデバイスに格納される、方法。 - フラッシュメモリアレイと、
外部プログラムコマンドに含められた情報がデコードされたとき、セルあたり複数ビット(MBC)プログラムコマンドまたはセルあたり単一ビット(SBC)プログラムコマンドのうちの1つを発行するコマンドデコーダと、
前記MBCプログラムコマンドまたは前記SBCプログラムコマンドのいずれかに応答してプログラミングアルゴリズムを実行する制御論理回路と、
前記プログラミングアルゴリズムに応答して、前記フラッシュメモリアレイの第1ブロック内の第1メモリセルにMBCデータを格納する、または前記フラッシュメモリアレイの第2ブロック内の第2メモリセルにSBCデータを格納する、のいずれかをするように、プログラムするフラッシュメモリ回路網と、
を含むフラッシュメモリデバイス。 - セルあたり複数ビット(MBC)ストレージモードおよびセルあたり単一ビット(SBC)ストレージモードのうちの1つでフラッシュメモリシステム内でデータを選択的にプログラムする方法であって、
a)データを受け取るステップと、
b)前記データの高信頼性レベルまたは低信頼性レベルを判定するステップと、
c)前記データが高信頼性であると判定される場合に、フラッシュメモリデバイスのフラッシュメモリアレイの第1ブロックに、前記データを前記SBCストレージモードでプログラムするステップと、
d)前記データが低信頼性であると判定される場合に、前記フラッシュメモリデバイスのフラッシュメモリアレイの第2ブロックに、前記データを前記MBCストレージモードでプログラムするステップと
を含み、
前記フラッシュメモリシステムのフラッシュコントローラは、前記フラッシュメモリデバイスに情報を提供し、
前記フラッシュメモリデバイスは、前記情報がデコードされたとき、MBCプログラムコマンドまたはSBCプログラムコマンドのうちの1つを発行する、方法。 - セルあたり複数ビット(MBC)データを格納するための第1ページを含むメモリブロックを有するNANDフラッシュメモリアレイと、
外部プログラムコマンドに応答してセルあたり複数ビット(MBC)プログラムコマンドおよびセルあたり単一ビット(SBC)プログラムコマンドのうちの1つを発行するコマンドデコーダと、
セルあたり複数ビット(MBC)プログラムコマンドまたはセルあたり単一ビット(SBC)プログラムコマンドのいずれかに応答してプログラミングアルゴリズムを実行する制御論理回路と、
前記プログラミングアルゴリズムに応答して、前記NANDフラッシュメモリアレイのメモリブロック内の第2ページに、SBCデータを格納するように、プログラムするフラッシュメモリ回路網と
を含むフラッシュメモリデバイス。
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US89025207P | 2007-02-16 | 2007-02-16 | |
US60/890,252 | 2007-02-16 | ||
US11/829,410 US7646636B2 (en) | 2007-02-16 | 2007-07-27 | Non-volatile memory with dynamic multi-mode operation |
US11/829,410 | 2007-07-27 |
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JP2009549749A Division JP5421127B2 (ja) | 2007-02-16 | 2008-02-14 | ダイナミックマルチモード動作を有する不揮発性メモリ |
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JP2009549749A Expired - Fee Related JP5421127B2 (ja) | 2007-02-16 | 2008-02-14 | ダイナミックマルチモード動作を有する不揮発性メモリ |
JP2013160457A Withdrawn JP2013229100A (ja) | 2007-02-16 | 2013-08-01 | ダイナミックマルチモード動作を有する不揮発性メモリ |
JP2015087437A Pending JP2015156251A (ja) | 2007-02-16 | 2015-04-22 | ダイナミックマルチモード動作を有する不揮発性メモリ |
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US (5) | US7646636B2 (ja) |
EP (2) | EP2490224A3 (ja) |
JP (3) | JP5421127B2 (ja) |
KR (6) | KR20090081426A (ja) |
CN (1) | CN101617372B (ja) |
CA (1) | CA2675565C (ja) |
ES (1) | ES2477493T3 (ja) |
TW (1) | TWI449049B (ja) |
WO (1) | WO2008098363A1 (ja) |
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