JP2012522399A - 選択的窒素化の方法 - Google Patents
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- JP2012522399A JP2012522399A JP2012503543A JP2012503543A JP2012522399A JP 2012522399 A JP2012522399 A JP 2012522399A JP 2012503543 A JP2012503543 A JP 2012503543A JP 2012503543 A JP2012503543 A JP 2012503543A JP 2012522399 A JP2012522399 A JP 2012522399A
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- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
Description
である。典型的な窒化物部は窒化シリコン(SiN)を含む。窒素含有層208は、約0.2から5nmの間の厚さを持つ。窒素含有層208は、約1から60%の窒素含有量を持つ。
Claims (15)
- 半導体装置の形成方法であって、この方法は、
酸化物表面とシリコン表面を有する基板を供給し、
酸化物表面およびシリコン表面の共に露出した部分に窒素含有層を形成し、そして
酸化物表面上から窒素含有層を選択的に除去するために、窒素含有層を酸化する工程を有する半導体装置の形成方法。 - さらに、シリコン特徴部上に形成された窒素含有層の残余の部分上に酸化物層を形成することからなる請求項1の方法。
- 酸化物表面は、半導体装置の1つまたはそれ以上のフローティングゲートに隣接して配置された浅いトレンチ分離領域(STI)の露出面を含み、シリコン表面は半導体装置のシリコンまたはポリシリコンのフローティングゲートの露出面である請求項1の方法。
- 窒素含有層の形成は、厚さが約0.2から約5.0ナノメーターの窒素含有層を形成することをからなる請求項1の方法。
- 窒素含有層の形成は、約1%から約60%の間の窒素含有量を持つ窒素含有層を形成することからなる請求項1の方法。
- 請求項1の方法であって、この方法はさらに、
酸化物層上から窒素含有層の一部を除去するため、窒素含有層形成後および窒素含有層の酸化以前に湿式エッチングを施すか、あるいは、
酸化物層上から残余の窒素含有種を除去するために、窒素含有層の酸化後にウエットエッチングを施すか、少なくとも一つを有する方法。 - 請求項1の方法は、さらに、
窒素含有層を酸化後、露出したシリコン表面上にインターポリ誘電体層を形成し、そして、
インターポリ誘電体層上に制御ゲート層を形成することを含む請求項1の方法。 - 窒素含有層がプラズマ窒化工程において形成される請求項1ないし7のいずれか1つに記載の方法。
- プラズマ窒化工程は、
窒素含有ガスからなるプロセスガスからプラズマを形成し、そして、
窒素含有層を形成するために、基板をプラズマに露出することを含む請求項8に記載の方法。 - 窒素含有ガスは、少なくとも、窒素(N2)またはアンモニア(NH3)のいずれか1つを有する請求項9に記載の方法。
- さらに、
窒素含有ガスの窒化速度あるいは窒素含有量の少なくとも1つを増加させるために、プラズマ窒化工程を実行中に基板を加熱することを含む請求項8に記載の方法。 - 窒素含有層はプラズマ酸化工程において酸化される請求項1ないし7のいずれか1つに記載の方法。
- プラズマ酸化工程は、
酸素(O2)に加えて、水素(H2)、ヘリウム(He)、窒素(N2)、あるいはアルゴン(Ar)のいずれか1種を有するプロセスガスからプラズマを形成し、そして、
窒素含有層を酸化するために、基板をプラズマに露出することを有する請求項12に記載の方法。 - 窒素含有層は、600より高く1100℃より低い温度で、熱酸化工程によって酸化されることを有する請求項1ないし7のいずれか1つに記載の方法。
- 熱酸化工程は全チャンバ圧力が20Torr以下で、水素(H2)と酸素含有ガスとを反応させることを有する請求項14に記載の方法。
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US16517909P | 2009-03-31 | 2009-03-31 | |
US61/165,179 | 2009-03-31 | ||
PCT/US2010/028998 WO2010117703A2 (en) | 2009-03-31 | 2010-03-29 | Method of selective nitridation |
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JP2012522399A true JP2012522399A (ja) | 2012-09-20 |
JP5595481B2 JP5595481B2 (ja) | 2014-09-24 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012216667A (ja) * | 2011-03-31 | 2012-11-08 | Tokyo Electron Ltd | プラズマ処理方法 |
JP2014533437A (ja) * | 2011-11-11 | 2014-12-11 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 層間多結晶シリコン誘電体キャップおよびその形成方法 |
WO2016104292A1 (ja) * | 2014-12-25 | 2016-06-30 | 株式会社日立国際電気 | 半導体装置の製造方法、記録媒体及び基板処理装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010147937A2 (en) * | 2009-06-15 | 2010-12-23 | Applied Materials, Inc. | Enhancing nand flash floating gate performance |
EP2495762B1 (en) * | 2011-03-03 | 2017-11-01 | IMEC vzw | Method for producing a floating gate semiconductor memory device |
CN103633030A (zh) * | 2012-08-22 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | 改善sonos闪存器件可靠性的面内均一性的方法 |
US10103027B2 (en) | 2016-06-20 | 2018-10-16 | Applied Materials, Inc. | Hydrogenation and nitridization processes for modifying effective oxide thickness of a film |
US10510545B2 (en) | 2016-06-20 | 2019-12-17 | Applied Materials, Inc. | Hydrogenation and nitridization processes for modifying effective oxide thickness of a film |
US10049882B1 (en) * | 2017-01-25 | 2018-08-14 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device including forming a dielectric layer on a structure having a height difference using ALD |
CN108987402A (zh) * | 2017-05-31 | 2018-12-11 | 华邦电子股份有限公司 | 存储元件的制造方法 |
TWI635599B (zh) * | 2017-05-31 | 2018-09-11 | 華邦電子股份有限公司 | 記憶元件的製造方法 |
US10483091B1 (en) | 2018-05-18 | 2019-11-19 | International Business Machines Corporation | Selective ion filtering in a multipurpose chamber |
US11588031B2 (en) * | 2019-12-30 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
WO2021150625A1 (en) | 2020-01-23 | 2021-07-29 | Applied Materials, Inc. | Method of cleaning a structure and method of depositiing a capping layer in a structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006013003A (ja) * | 2004-06-23 | 2006-01-12 | Toshiba Corp | 不揮発性半導体メモリ装置及びその製造方法 |
JP2009021608A (ja) * | 2007-07-16 | 2009-01-29 | Applied Materials Inc | 不揮発性メモリデバイス用インターポリ誘電体を形成するための統合スキーム |
JP2010103414A (ja) * | 2008-10-27 | 2010-05-06 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100356773B1 (ko) * | 2000-02-11 | 2002-10-18 | 삼성전자 주식회사 | 플래쉬 메모리 장치 및 그 형성 방법 |
US6620705B1 (en) * | 2000-12-06 | 2003-09-16 | Advanced Micro Devices, Inc. | Nitriding pretreatment of ONO nitride for oxide deposition |
US7517751B2 (en) | 2001-12-18 | 2009-04-14 | Tokyo Electron Limited | Substrate treating method |
TWI225668B (en) | 2002-05-13 | 2004-12-21 | Tokyo Electron Ltd | Substrate processing method |
WO2003098678A1 (fr) | 2002-05-16 | 2003-11-27 | Tokyo Electron Limited | Procede de traitement de substrat |
US7332408B2 (en) * | 2004-06-28 | 2008-02-19 | Micron Technology, Inc. | Isolation trenches for memory devices |
US7482223B2 (en) * | 2004-12-22 | 2009-01-27 | Sandisk Corporation | Multi-thickness dielectric for semiconductor memory |
KR100632640B1 (ko) * | 2005-03-10 | 2006-10-12 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조방법 |
US7294581B2 (en) | 2005-10-17 | 2007-11-13 | Applied Materials, Inc. | Method for fabricating silicon nitride spacer structures |
US7888217B2 (en) | 2005-10-20 | 2011-02-15 | Applied Materials, Inc. | Method for fabricating a gate dielectric of a field effect transistor |
US7416995B2 (en) | 2005-11-12 | 2008-08-26 | Applied Materials, Inc. | Method for fabricating controlled stress silicon nitride films |
US7465669B2 (en) | 2005-11-12 | 2008-12-16 | Applied Materials, Inc. | Method of fabricating a silicon nitride stack |
US7387972B2 (en) * | 2006-03-01 | 2008-06-17 | Promos Technologies Pte. Ltd. | Reducing nitrogen concentration with in-situ steam generation |
KR100806130B1 (ko) * | 2006-07-12 | 2008-02-22 | 삼성전자주식회사 | 불휘발성 메모리 장치의 제조방법 |
US20080179715A1 (en) * | 2007-01-30 | 2008-07-31 | Micron Technology, Inc. | Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device |
US7645709B2 (en) | 2007-07-30 | 2010-01-12 | Applied Materials, Inc. | Methods for low temperature oxidation of a semiconductor device |
US7910497B2 (en) | 2007-07-30 | 2011-03-22 | Applied Materials, Inc. | Method of forming dielectric layers on a substrate and apparatus therefor |
US7749849B2 (en) * | 2007-12-18 | 2010-07-06 | Micron Technology, Inc. | Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom |
WO2009114617A1 (en) | 2008-03-14 | 2009-09-17 | Applied Materials, Inc. | Methods for oxidation of a semiconductor device |
US8871645B2 (en) | 2008-09-11 | 2014-10-28 | Applied Materials, Inc. | Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof |
WO2010147937A2 (en) * | 2009-06-15 | 2010-12-23 | Applied Materials, Inc. | Enhancing nand flash floating gate performance |
-
2010
- 2010-03-29 JP JP2012503543A patent/JP5595481B2/ja active Active
- 2010-03-29 WO PCT/US2010/028998 patent/WO2010117703A2/en active Application Filing
- 2010-03-29 US US12/748,523 patent/US7972933B2/en active Active
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006013003A (ja) * | 2004-06-23 | 2006-01-12 | Toshiba Corp | 不揮発性半導体メモリ装置及びその製造方法 |
JP2009021608A (ja) * | 2007-07-16 | 2009-01-29 | Applied Materials Inc | 不揮発性メモリデバイス用インターポリ誘電体を形成するための統合スキーム |
JP2010103414A (ja) * | 2008-10-27 | 2010-05-06 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012216667A (ja) * | 2011-03-31 | 2012-11-08 | Tokyo Electron Ltd | プラズマ処理方法 |
JP2014533437A (ja) * | 2011-11-11 | 2014-12-11 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 層間多結晶シリコン誘電体キャップおよびその形成方法 |
WO2016104292A1 (ja) * | 2014-12-25 | 2016-06-30 | 株式会社日立国際電気 | 半導体装置の製造方法、記録媒体及び基板処理装置 |
KR20170086639A (ko) * | 2014-12-25 | 2017-07-26 | 가부시키가이샤 히다치 고쿠사이 덴키 | 반도체 장치의 제조 방법, 기록 매체 및 기판 처리 장치 |
JPWO2016104292A1 (ja) * | 2014-12-25 | 2017-11-02 | 株式会社日立国際電気 | 半導体装置の製造方法、プログラム及び基板処理装置 |
KR101965992B1 (ko) * | 2014-12-25 | 2019-04-04 | 가부시키가이샤 코쿠사이 엘렉트릭 | 반도체 장치의 제조 방법, 기록 매체 및 기판 처리 장치 |
US10453676B2 (en) | 2014-12-25 | 2019-10-22 | Kokusai Electric Corporation | Semiconductor device manufacturing method and recording medium |
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US7972933B2 (en) | 2011-07-05 |
WO2010117703A2 (en) | 2010-10-14 |
US20100248435A1 (en) | 2010-09-30 |
TWI604562B (zh) | 2017-11-01 |
WO2010117703A3 (en) | 2011-01-13 |
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