CN108987402A - 存储元件的制造方法 - Google Patents

存储元件的制造方法 Download PDF

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CN108987402A
CN108987402A CN201710396986.2A CN201710396986A CN108987402A CN 108987402 A CN108987402 A CN 108987402A CN 201710396986 A CN201710396986 A CN 201710396986A CN 108987402 A CN108987402 A CN 108987402A
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dielectric layer
layer
conductor layer
manufacturing
memory element
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刘重显
陈俊旭
蒋汝平
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to US15/867,736 priority patent/US10381449B2/en
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Abstract

本发明提供一种存储元件的制造方法，其步骤如下。在衬底上依序形成第一介电层与第一导体层。在衬底、第一介电层以及第一导体层中形成第一开口与位于第一开口上的第二开口。在第一开口中形成隔离结构。在衬底上形成第二介电层，使得第二介电层共形覆盖第一导体层的顶面与第二开口的表面。对第二介电层进行热处理，以强化第二介电层与第一导体层之间的键结。进行蚀刻工艺，移除第二介电层的一部分，以暴露出隔离结构的顶面。

Description

存储元件的制造方法
技术领域
本发明涉及一种半导体元件的制造方法，尤其涉及一种存储元件的制造方法。
背景技术
近年来，由于闪速存储器兼具高密度、低成本、可重复写入及电可抹除性等优点，已然成为非易失性存储器元件的主流，并被广泛的应用于各式可携式电子产品中，例如笔记本电脑、数码随身听、数码相机、手机、游戏主机等相关可携式电子产品。
随着存储器工艺的微缩，一般闪速存储器的工艺会发生以下问题：由于浮置栅极的侧壁过于粗糙(rough)，其使得栅间介电层与控制栅极填入浮置栅极之间的空间时，会导致孔洞(void)或缝隙(seam)形成在控制栅极中。所述孔洞或缝隙会降低元件的可靠度与良率。因此，如何提供一种闪速存储器的制造方法，使浮置栅极的侧壁平坦，以减少控制栅极中的孔洞或缝隙产生，进而提升元件的可靠度与良率，将成为重要的一门课题。
发明内容
本发明提供一种存储元件的制造方法，其可保护浮置栅极(floating gate)的侧壁，以避免浮置栅极的侧壁受到损伤，进而提升元件的可靠度与良率。
本发明提供一种存储元件的制造方法，其步骤如下。在衬底上依序形成第一介电层与第一导体层。在衬底、第一介电层以及第一导体层中形成第一开口与位于第一开口上的第二开口。在第一开口中形成隔离结构，其中隔离结构的顶面低于第一导体层的顶面。在衬底上形成第二介电层，使得第二介电层共形覆盖第一导体层的顶面与第二开口的表面。对第二介电层进行热处理，以强化第二介电层与第一导体层之间的键结。进行蚀刻工艺，移除第二介电层的一部分，以暴露出隔离结构的顶面。在衬底上形成第三介电层，使得第三介电层覆盖第二介电层的剩余部分与隔离结构的顶面。
基于上述，本发明可通过快速热退火处理以强化第二介电层与第一导体层(例如是浮置栅极)之间的Si-N键结。在蚀刻工艺之后，仍有剩余的第二介电层配置在浮置栅极的侧壁上，以保护浮置栅极不受损伤。因此，浮置栅极可具有平滑表面，以减少第二导体层(例如是控制栅极)中的孔洞或缝隙的产生，进而提升元件的可靠度与良率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1E是依照本发明一实施例的一种存储元件的制造流程的剖面示意图。
附图标记说明
10：第一开口
20：第二开口
100：衬底
101：隔离结构
101T：顶面
102：第一隔离材料
104：第二隔离材料
106：第一介电层
106T：顶面
108：第一导体层
108T：顶面
108S：侧壁
110、110a：第二介电层
112：热处理
114：第三介电层
116：第二导体层
R：凹陷
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
另外，以下段落的存储元件是以闪速存储器(Flash)为例。但本发明不以此为限，在其他实施例中，所述存储元件也可以是闪速存储器阵列。
请参照图1A，本实施例提供一种存储元件的制造方法，其步骤如下。首先，提供衬底100。在本实施例中，衬底100可例如为半导体衬底、半导体化合物衬底或是绝缘层上有半导体衬底(Semiconductor Over Insulator，SOI)。
接着，在衬底100上依序形成第一介电层106与第一导体层108。在本实施例中，第一介电层106可以是穿隧介电层；第一导体层108可以是浮置栅极。第一介电层106的材料包括氧化硅；第一导体层108的材料包括多晶硅。在一实施例中，第一介电层106的厚度可介于至之间，其形成方法可以是化学气相沉积法。第一导体层108的厚度可介于70nm至100nm之间，其形成方法可以是化学气相沉积法。
之后，在衬底100、第一介电层106以及第一导体层108中形成第一开口10与位于第一开口10上的第二开口20。第一开口10与第二开口20的形成方法可例如是在第一导体层108上形成掩膜图案(未示出)。所述掩膜图案暴露出第一导体层108的部分表面，以定义出第一开口10与第二开口20的位置。以所述掩膜图案为掩膜，移除部分衬底100、部分第一介电层106以及部分第一导体层108，以形成第一开口10与第二开口20。
接着，在第一开口10中形成隔离结构101。详细地说，隔离结构101可包括第一隔离材料102与第二隔离材料104。第一隔离材料102共形地形成在第一开口10中，以覆盖第一开口10的侧壁与底面。第二隔离材料104形成在第一隔离材料102的内表面上，并填满第一开口10。如图1A所示，第一隔离材料102包覆第二隔离材料104，使得第一隔离材料102位于衬底100与第二隔离材料104之间。在一实施例中，第一隔离材料102可以是高温氧化物(Hightemperature oxide，HTO)。第二隔离材料104可以是旋涂式玻璃(spin-on glass，SOG)。
值得注意的是，如图1A所示，隔离结构101的顶面101T低于第一导体层108的顶面108T，其使得第一导体层108的部分侧壁108S外露。也就是说，第二开口20暴露出第一导体层108的部分侧壁108S，其可增加第一导体层108与后续形成的第二导体层116(如图1E所示)之间的接触面积，进而提升栅极耦合比(gate-coupling ratio，GCR)。在一实施例中，隔离结构101的顶面101T可高于第一介电层106的顶面106T。在一实施例中，隔离结构101的顶面101T为具有凹陷R的表面。但本发明不以此为限，在其他实施例中，隔离结构101的顶面101T也可以是平坦的表面。
请参照图1A与图1B，在衬底100上形成第二介电层110。第二介电层110共形覆盖第一导体层108的顶面108T、第一导体层108的部分侧壁108S以及隔离结构101的顶面101T(也即第二开口20的表面)。在一实施例中，第二介电层110的材料包括氮化硅、氮氧化硅或其组合。第二介电层110的厚度可介于1nm至2nm之间，其形成方法可以是等离子体氮化处理法或化学气相沉积法。
接着，对第二介电层110进行热处理112，以强化第二介电层110与第一导体层108之间的键结。详细地说，所述热处理112可加强第一导体层108中的硅(Si)与第二介电层110中的氮(N)的Si-N键结。在替代实施例中，所述热处理112之后，也可在第一导体层108与第二介电层110之间形成氮氧化硅(SiON)。而此氮氧化硅会被后续的湿式蚀刻工艺(如图1C所示)所移除。另一方面，覆盖隔离结构101的顶面101T上的第二介电层110则未被强化。
在一实施例中，所述热处理112可以是快速热退火处理。在一实施例中，所述快速热退火处理的温度为850℃至1050℃，而快速热退火处理的时间为1秒至60秒，其通入的气体为氮气。在替代实施例中，所述快速热退火处理的温度为950℃至1000℃，而快速热退火处理的时间为1秒至10秒，或是1秒至5秒，其通入的气体为氮气。当快速热退火处理的时间超过10秒时，将会产生额外的热预算(thermal budget)，其容易导致元件的不稳定，并造成产能的浪费。具体来说，此热处理112是在整个元件的所有井区的离子注入工艺之后才进行。因此，当所述井区在面临此热处理112的时间超过10秒时，便会产生额外的热预算，使得所述井区中的掺质扩散，进而导致元件的不稳定。而当快速热退火处理的时间小于1秒时，则会使得第一导体层108与第二介电层110之间的Si-N键结的强度不足，而使得后续蚀刻工艺损害第一导体层108的表面，进而降低元件的可靠度与良率。
请参照图1B与图1C，在热处理112之后，进行蚀刻工艺，移除第二介电层110的一部分，以暴露出隔离结构101的顶面101T。在一实施例中，所述蚀刻工艺可以是湿式蚀刻工艺，其可使用稀释氢氟酸(DHF)溶液当作蚀刻液。由于上述热处理112已强化了第一导体层108与第二介电层110之间的Si-N键结，因此，在蚀刻工艺之后，仍有残留的第二介电层110a覆盖第一导体层108的顶面108T与侧壁108S。在一实施例中，覆盖在第一导体层108上的第二介电层110a的剩余部分的厚度小于等于
值得一提的是，残留的第二介电层110a可保护第一导体层108的顶面108T与侧壁108S不被蚀刻，而使得第一导体层108的顶面108T与侧壁108S保持平滑。具有平滑表面的第一导体层108可减少后续形成的第二导体层116(如图1E所示)中的孔洞或缝隙的产生，进而提升元件的可靠度与良率。另外，在蚀刻工艺之后，可完全清除隔离结构101的顶面101T上的第二介电层(如图1C所示)，以避免存储元件操作时隔离结构101两侧的第一导体层108之间的电性干扰(electrical disturbance)问题。
请参照图1C与图1D，在衬底100上形成第三介电层114。第三介电层114共形地覆盖第二介电层110a的剩余部分与隔离结构101的顶面101T上。在一实施例中，第三介电层114与隔离结构101的顶面101T直接接触。在一实施例中，第三介电层114可例如是由氧化硅/氮化硅/氧化硅/氮化硅所构成的复合层结构。但本发明不以此为限，在其他实施例中，第三介电层114可以是任意层数的氧化硅与氮化硅所构成的复合层结构。在替代实施例中，第三介电层114也可以是由高介电常数材料所构成的复合层结构，所述高介电常数材料可以是介电常数大于4的介电材料。在一实施例中，第三介电层114的厚度可介于9nm至14nm之间，其形成方法包括热氧化法、化学气相沉积法、等离子体氮化处理法或其组合。第二介电层110a与第三介电层114所构成的介电结构可用以当作第一导体层108(例如是浮置栅极)与后续形成的第二导体层116(例如是控制栅极)之间的栅间介电层，以电性隔绝第一导体层108与第二导体层116(如图1E所示)。
请参照图1D与图1E，在形成第三介电层114之后，可于衬底100上形成第二导体层116。第二导体层116填入第二开口20中并覆盖第一导体层108的顶面108T。在本实施例中，第二导体层116可以是控制栅极。第二导体层116的材料包括多晶硅。在一实施例中，第二导体层116的厚度可介于35nm之间，其形成方法可以是化学气相沉积法。
综上所述，本发明可通过快速热退火处理以强化第二介电层与第一导体层(例如是浮置栅极)之间的Si-N键结。在蚀刻工艺之后，仍有剩余的第二介电层配置在浮置栅极的侧壁上，以保护浮置栅极不受损伤。因此，浮置栅极可具有平滑表面，以减少第二导体层(例如是控制栅极)中的孔洞或缝隙的产生，进而提升元件的可靠度与良率。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (10)

1.一种存储元件的制造方法，包括：
在衬底上依序形成第一介电层与第一导体层；
在所述衬底、所述第一介电层以及所述第一导体层中形成第一开口与位于所述第一开口上的第二开口；
在所述第一开口中形成隔离结构，其中所述隔离结构的顶面低于所述第一导体层的顶面；
在所述衬底上形成第二介电层，使得所述第二介电层共形覆盖所述第一导体层的顶面与所述第二开口的表面；
对所述第二介电层进行热处理，以强化所述第二介电层与所述第一导体层之间的键结；
进行蚀刻工艺，移除所述第二介电层的一部分，以暴露出所述隔离结构的顶面；以及
在所述衬底上形成第三介电层，使得所述第三介电层覆盖所述第二介电层的剩余部分与所述隔离结构的顶面。
2.根据权利要求1所述的存储元件的制造方法，其中所述热处理包括快速热退火处理。
3.根据权利要求2所述的存储元件的制造方法，其中所述快速热退火处理的温度为850℃至1050℃，所述快速热退火处理的时间为1秒至60秒。
4.根据权利要求2所述的存储元件的制造方法，其中所述快速热退火处理的温度为950℃至1000℃，所述快速热退火处理的时间为1秒至10秒。
5.根据权利要求1所述的存储元件的制造方法，其中所述第一介电层为穿隧介电层，其材料包括氧化硅，所述第三介电层包括由氧化硅/氮化硅/氧化硅/氮化硅所构成的复合层结构。
6.根据权利要求1所述的存储元件的制造方法，其中所述第二介电层的材料包括氮化硅、氮氧化硅或其组合。
7.根据权利要求1所述的存储元件的制造方法，其中所述第一导体层为浮置栅极，其材料包括多晶硅。
8.根据权利要求1所述的存储元件的制造方法，移除所述第二介电层的所述部分之后，覆盖在所述第一导体层上的所述第二介电层的剩余部分的厚度小于等于
9.根据权利要求1所述的存储元件的制造方法，在形成所述第三介电层之后，还包括于所述衬底上形成第二导体层，使得所述第二导体层填入所述第二开口中。
10.根据权利要求9所述的存储元件的制造方法，其中所述第一导体层为浮置栅极，所述第二导体层为控制栅极，而介于所述第一导体层与所述第二导体层之间的所述第二介电层与所述第三介电层为栅间介电层。
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