JP2011528196A5 - - Google Patents

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Publication number
JP2011528196A5
JP2011528196A5 JP2011517524A JP2011517524A JP2011528196A5 JP 2011528196 A5 JP2011528196 A5 JP 2011528196A5 JP 2011517524 A JP2011517524 A JP 2011517524A JP 2011517524 A JP2011517524 A JP 2011517524A JP 2011528196 A5 JP2011528196 A5 JP 2011528196A5
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JP
Japan
Prior art keywords
circuit
signal
pads
pad
external device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011517524A
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English (en)
Japanese (ja)
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JP2011528196A (ja
JP5566381B2 (ja
Filing date
Publication date
Priority claimed from US12/172,247 external-priority patent/US8138787B2/en
Application filed filed Critical
Publication of JP2011528196A publication Critical patent/JP2011528196A/ja
Publication of JP2011528196A5 publication Critical patent/JP2011528196A5/ja
Application granted granted Critical
Publication of JP5566381B2 publication Critical patent/JP5566381B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2011517524A 2008-07-13 2009-07-07 回路における周波数性能を最適化する入力／出力モジュールのための装置および方法 Expired - Fee Related JP5566381B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/172,247 US8138787B2 (en) 2008-07-13 2008-07-13 Apparatus and method for input/output module that optimizes frequency performance in a circuit
US12/172,247 2008-07-13
PCT/US2009/049822 WO2010008971A2 (en) 2008-07-13 2009-07-07 Apparatus and method for input/output module that optimizes frequency performance in a circuit

Publications (3)

Publication Number Publication Date
JP2011528196A JP2011528196A (ja) 2011-11-10
JP2011528196A5 true JP2011528196A5 (enExample) 2012-08-02
JP5566381B2 JP5566381B2 (ja) 2014-08-06

Family

ID=41504357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011517524A Expired - Fee Related JP5566381B2 (ja) 2008-07-13 2009-07-07 回路における周波数性能を最適化する入力／出力モジュールのための装置および方法

Country Status (5)

Country Link
US (1) US8138787B2 (enExample)
EP (1) EP2311190A4 (enExample)
JP (1) JP5566381B2 (enExample)
CN (1) CN102089974B (enExample)
WO (1) WO2010008971A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201205427D0 (en) * 2012-03-28 2012-05-09 Yota Devices Ipr Ltd Display device and connector
KR20150026644A (ko) * 2013-09-03 2015-03-11 에스케이하이닉스 주식회사 반도체칩, 반도체칩 패키지 및 이를 포함하는 반도체시스템
US9503155B2 (en) * 2015-04-09 2016-11-22 Nxp B.V. Tuning asymmetry of a differential digital interface to cancel magnetic coupling
KR102777475B1 (ko) 2019-10-17 2025-03-10 에스케이하이닉스 주식회사 반도체 패키지

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992011701A2 (en) * 1990-12-18 1992-07-09 Vlsi Technology Inc. Reduction of noise on power and ground inputs to an integrated circuit
JPH07182859A (ja) * 1993-12-21 1995-07-21 Toshiba Corp 半導体集積回路装置
US5406607A (en) * 1994-02-24 1995-04-11 Convex Computer Corporation Apparatus, systems and methods for addressing electronic memories
US5604710A (en) * 1994-05-20 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Arrangement of power supply and data input/output pads in semiconductor memory device
US5847936A (en) * 1997-06-20 1998-12-08 Sun Microsystems, Inc. Optimized routing scheme for an integrated circuit/printed circuit board
JP3535797B2 (ja) * 2000-03-10 2004-06-07 日本電信電話株式会社 モノリシック集積回路の製造方法
US6603199B1 (en) * 2000-11-28 2003-08-05 National Semiconductor Corporation Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages
US6591410B1 (en) * 2000-12-28 2003-07-08 Lsi Logic Corporation Six-to-one signal/power ratio bump and trace pattern for flip chip design
JP3929289B2 (ja) * 2001-11-12 2007-06-13 株式会社ルネサステクノロジ 半導体装置
JP2003229448A (ja) * 2002-01-31 2003-08-15 Kinseki Ltd 半導体素子の電極構造とそれを用いた圧電発振器
JP2003338175A (ja) * 2002-05-20 2003-11-28 Mitsubishi Electric Corp 半導体回路装置
US6972464B2 (en) * 2002-10-08 2005-12-06 Great Wall Semiconductor Corporation Power MOSFET
TWI265600B (en) * 2002-11-18 2006-11-01 Hynix Semiconductor Inc Semiconductor device and method for fabricating the same
US6998719B2 (en) * 2003-07-30 2006-02-14 Telairity Semiconductor, Inc. Power grid layout techniques on integrated circuits
US7091614B2 (en) * 2004-11-05 2006-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design for routing an electrical connection
US7200021B2 (en) * 2004-12-10 2007-04-03 Infineon Technologies Ag Stacked DRAM memory chip for a dual inline memory module (DIMM)
JP4693428B2 (ja) * 2005-01-27 2011-06-01 ルネサスエレクトロニクス株式会社 半導体集積回路
US7405473B1 (en) * 2005-11-23 2008-07-29 Altera Corporation Techniques for optimizing electrical performance and layout efficiency in connectors with via placement and routing
EP2140741B1 (en) * 2007-04-20 2013-02-27 Telefonaktiebolaget LM Ericsson (publ) A printed board assembly and a method

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