WO1992011701A2

WO1992011701A2 - Reduction of noise on power and ground inputs to an integrated circuit

Info

Publication number: WO1992011701A2
Application number: PCT/EP1991/002329
Authority: WO
Inventors: David Thomas Rackley
Original assignee: Vlsi Technology Inc.
Priority date: 1990-12-18
Filing date: 1991-12-03
Publication date: 1992-07-09
Also published as: WO1992011701A3

Abstract

Regions on the surface of an integrated circuit device which are not used by logic circuitry of the integrated circuit device are used for reducing noise on a power line and a ground line on the integrated circuit device. In these unused regions (4) are fabricated capacitors between the power line and the ground line. The unused regions may be, for example, free pad structures, corners of the integrated circuit device and unused logic cells within the integrated circuit device.

Description

REDUCTION OF NOISE ON POWER AND GROUND INPUTS TO AN INTEGRA

CIRCUIT.

The present invention concerns structures used to reduce noise on the power line and/or the ground line of an integrated circuit device.

Noise on power and ground lines can cause malfunction of integrated circuit devices. For example, transistor to transistor logic (TTL) level shifters within an integrated circuit device are particularly susceptible to noise generated errors. Noise becomes a greater factor when large amounts of current are switched in short time intervals. This can occur, for example, when drivers are constructed with transistors with large width to length ( /L) ratios. Such transistors generate relatively large amounts of current. Noise is increased when there are multiple drivers which are switched together, that is drivers with simultaneous switching outputs (SSO) . Additionally, noise can become a greater nuisance when geometries of the integrated circuit device become smaller, resulting in higher switching speeds.

Numerous strategies have been used to reduce the difficulties associated with excess noise on the power and ground lines. For example, the power line and ground line of circuitry within an integrated circuit device which is sensitive to noise may be separated from the power line and ground line of other circuitry within the integrated circuit, such as input/output (I/O) circuitry or core circuitry, when the I/O and/or core circuitry tends to generate a lot of noise. This, however, requires additional pins to be added to the integrated circuit device package and associated I/O circuitry.

Additionally, care may be taken to reduce the inductance within the integrated circuit device by selection of high quality packaging, including redundant power pin pairs to the integrated circuit device and/or by increasing the width of power lines on the integrated circuit device. This, however, can result in an increase in the cost of manufacturing of the integrated circuit device. Finally, the integrated circuit device can be designed to limit the switching speed and/or current levels to reduce noise.

Summary of the invention

According to one aspect of the invention, a method for fabricating an integrated circuit to reduce noise on a power line and/or a ground line on an integrated circuit device is characterised by: locating regions on the surface of the integrated circuit which are not used by logical circuitry of the integrated circuit; and fabricating capacitors on at least some of the said regions, the capacitors being electrically connected between the power line and the ground line.

According to another aspect of the invention, a device for reducing noise on a power line and a ground line of an integrated circuit comprises capacitors connected between the power line and the ground line, the capacitors being located in regions which are not used by logical circuitry of the integrated circuit.

Each capacitor may comprise a parallel plate capacitor of which the plates and an intervening dielectric layer are disposed as superposed layers over a substrate on which the integrated circuit is formed.

The present invention is based on the utilization of otherwise unused regions on the surface of the integrated circuit device, i.e. regions which are not used by logical circuitry of the integrated circuit device. These unused regions or areas may be, for example, unused pad structures, corners of the integrated circuit device and unused logic cells within the integrated circuit device. In these unused areas may be placed capacitors between, for example, the power line and the ground line or possibly between two power lines. The present invention is advantageous in that protection against noise on a power line or the ground line can be provided without the requirement of additional I/O pins and without the requirement that the width of connection lines for the power line and the ground line be increased in width. The addition of the capacitance between the lines is easily accomplished in the design of an integrated circuit device, and may be completely implemented using only otherwise unused areas on the integrated circuit device.

Brief Description of the Drawings

Figure 1 is a block diagram of the layout of an integrated circuit device.

Figure 2 shows a block diagram of used and unused pad structures on an integrated circuit device.

Figure 3 shows a block diagram of used and unused logic cells within an integrated circuit device.

Figure 4 shows the construction of capacitors in otherwise unused regions of an integrated circuit device in accordance with the preferred embodiment of the present invention.

Description of the Preferred Embodiment

In the preferred embodiment of the present invention, area on an integrated circuit device which is not used in the circuit design, is used to provide capacitance between a power line and a ground line.

For example, Figure 1 is a schematic diagram of a layout of an integrated circuit device 1. Circuit logic 2 within integrated circuit device 1 is connected to other devices through utilized terminal pad structures 3. Free pad structures 4 interspersed with the terminal pads are not utilized by the logic of integrated circuit device 1 and so are available as areas which can be adapted to provide capacitance between the power line and ground line of integrated circuit device 1. Also corner regions 5 of the integrated circuit device 1 are not otherwise utilized and so are also available as areas which may be adapted to provide capacitance between the power line and the ground line. Figure 2 is a schematic diagram of utilized pad structures and free pad structures within an integrated circuit device. Three utilized pad structures are shown. A pad bonding region 11 is connected to pad logic circuitry 16 through a connection region 23. A pad bonding region 13 is connected to pad logic circuitry 18 through a connection area 24. A pad bonding region 15 is connected to pad logic circuitry 20 through a connection region 25. A power line 21 and a ground line 22 supply power to the pad logic circuitry.

Two free pad structures are shown. A pad bonding region 12 is shown as separate from a pad logic circuitry area 17. A pad bonding region 14 is shown as separate from a pad logic circuit region 19. Since these pad structures are not utilized by the integrated circuit device, they are available as areas which provide capacitance between power line 21 and ground line 22 as is more fully described below.

Figure 3 is a schematic diagram of gate array logic cells within circuit logic 2 including a logic cell 25, a logic cell 26, a logic cell 27, a logic cell 28 and a logic cell 29. Pins 34 are used to electrically connect the logic cells to power line 21. Pins 35 are used to connect the cells to ground line 22.

Logic cell 25, logic cell 27 and logic cell 29 are utilized as part of the logic circuitry of integrated circuit device 1. Logic cell 26 and logic cell 28 are not used as part of the logic circuitry of integrated circuit device 1 and so are available as areas or regions which provide capacitance between power line 21 and ground line 22 as is more fully described below.

Figure 4 is a cross-section view of a structure by which unused regions of an integrated circuit device 1 may be used to provide capacitance between power line 21 and ground line 22. Each unused region is used to form a parallel plate capacitor structure in which a conductive plate 41 coupled to power line 21 is placed in parallel to a conductive plate 42 electrically coupled to ground line 22. Between the plates 41 and 42 is an insulator layer 32, made for example of an isolation oxide. The result, is that in each unused area 33 of integrated circuit device 1 a parallel plate capacitor structure is constructed over a substrate 31. Typically, the plates 41 and 42 are metallic and of the order of 0.8 microns thick. Insulator layer 32 may be of the order of 1.0 microns thick.

The present invention is of particular benefit for integrated circuit devices which use gate array technology. In such integrated circuit devices there are generally regions of the integrated circuit devices, such as corner regions, free pad structures and unused logic cell areas, which are typically wasted. Using the present invention these otherwise unused regions are used to provide protection against noise on the power and ground lines.

The present invention may also be used for devices which are designed using other integrated circuit device technology, such as standard cell technology. Using such technology, corner regions and sometimes free pad structures generally are still an unused resource on the integrated circuit devices. However, if other resources on the integrated circuit devices are efficiently utilized, it may be necessary to increase the die size of the integrated circuit device in order to add additional area which may be used to provide capacitance between the power line and the ground line.

When designing integrated circuit devices in accordance with the invention, the utilization of free pad structures to provide capacitance between the power line and the ground line may be done very simply, possibly by just making a change to a library in a compiler program which generates the layout of the integrated circuit device. Similarly, the corner regions may be easily utilized to provide capacitance between the power line and the ground line. In order to utilize unused logic cell areas to provide capacitance between the power line and the ground line, it is necessary first to discover where these cells reside. Once the location of these unused logic cell areas are discovered, they may be used to provide capacitance between the power line and the ground line.

Claims

1. A method for fabricating an integrated circuit to reduce noise on a power line and/or a ground line on an integrated circuit device, characterised by: locating regions (4) on the surface of the integrated circuit which are not used by logical circuitry of the integrated circuit; and fabricating capacitors (41, 42) on at least some of the said regions, the capacitors being electrically connected between the power line and the ground line.

2. A method according to claim 1 wherein the regions include locations of free pad structures.

3. A method according to claim 1 wherein the regions include corners of the integrated circuit.

4. A method according to claim 1 wherein the regions include locations of unused logic cells within the integrated circuit.

5. A device for reducing noise on a power line and a ground line of an integrated circuit, the device comprising capacitors (41,42) connected between the power line (21) and the ground line (22) wherein the capacitors are located in regions which are not used by logical circuitry of the integrated circuit.

6. A device as in claim 5 wherein the regions include locations of free pad structures.

7. A device as in claim 5 wherein the regions include corners of the integrated circuit.

8. A device as in claim 5 wherein the regions include locations of unused logic cells within the integrated circuit.

9. A device according to any of claims 5 to 8, wherein each capacitor comprises a parallel plate capacitor of which the plates (41, 42) and an intervening dielectric layer (32) are disposed as superposed layers over a substrate (31) on which the integrated circuit is formed.