JPH01243542A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a large-capacity capacitance element without increasing an area of a semiconductor substrate by forming the capacitance element by making use of a dead space which cannot be used as a gate array part and a buffer region. CONSTITUTION:A gate array part 2 where many standard cells have been arranged regularly at high density is arranged in the central part of a semiconductor substrate 1. A buffer region 3 where many input/output buffer circuit parts 31 have been arranged in a row is arranged at a peripheral part of the substrate 1. One pair of power-supply buses 5, 6 by aluminum wiring parts on a second layer are wired in parallel along the upper part of the region 3. A capacitance element 8 is formed by utilizing an area at a corner part 7 which is a dead space. By this setup, the large-capacity capacitance element can be obtained without increasing an area of the substrate 1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technology that is effective when applied to semiconductor integrated circuit devices and furthermore gate arrays, such as MOS (
Metal-oxide-semiconductor) type or bipolar/MO8
The present invention relates to a technology that is effective for use in complex gate arrays.

[Prior Art] A conventional semiconductor integrated circuit device of this type includes a gate array section formed in the center of a semiconductor substrate, a buffer region formed along the periphery of the semiconductor substrate, and a buffer region of this buffer region. It has a terminal area formed on the outside and a pair of power supply buses wired along the buffer area, and by designing only the circuit wiring according to the customer's order, it is possible to integrate semiconductors in small quantities and in a wide variety of products. A circuit device can be provided with a low initial investment cost and a short design period (for example, see Nikkei Electronics, March 7, 1988 issue no. 442J, pages 138-142, published by Nikkei McGraw-Hill).

[Problems to be Solved by the Invention] However, the present inventors have found that the above-mentioned technique has the following problems.

That is, in the semiconductor integrated circuit device described above.

In order to increase the circuit scale that can be configured according to customer orders, it is required to increase the number of standard cells in the gate array section as much as possible.

For this reason, the gate array section occupies most of the surface area of the semiconductor substrate, and inside thereof, a large number of standard cells are arranged at high density, leaving an area for wiring channels. Recently, a type called a tiled type or a channelless type, in which only standard cells are lined up without gaps, has been provided, but this is also to increase the scale of the circuit that can be configured.

As described above, in a gate array that is required to have as many standard cells as possible, a relatively large capacitance element that can be used as a power supply bypass capacitor, for example, has not been provided. Capacitive elements that can be used for power supply bypass, etc. require a large layout area, and if they are installed, the layout area for forming a standard cell will be significantly reduced, and the value of the gate array will be significantly reduced. This is because it will be put away.

Even if the above-mentioned capacitive element is installed at the cost of significantly reducing the number of standard cells, by changing only the wiring structure, it is possible to meet the diverse specification requests from customers in a short period of time and at low cost. For gate arrays whose original function is
It is expected that there may be cases where the capacitive element placed with great effort is not used, and in such a case, the capacitive element becomes a useless item that only impairs the function of the gate array.

An object of the present invention is to provide a semiconductor substrate without increasing the area of the semiconductor substrate or impairing its function as a gate array.
For example, it includes a large-capacity capacitive element that can be used in a power supply bypass circuit. Our goal is to provide this technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a gate array section is formed in the center of a semiconductor substrate, a buffer region is formed along the periphery of the gate array section, a terminal region is formed outside this buffer region, and a pair of power supply bus lines is further formed along the buffer region. are wired in parallel, and a capacitive element is formed using the area of the corner portion where the running direction of the pair of power supply buses changes.

[Operation] According to the above-described means, the capacitive element is formed using dead space that cannot be used in either the gate array section or the buffer region.

As a result, without increasing the area of the semiconductor substrate,
It also includes a large-capacity capacitive element that can be used, for example, as a power supply bypass, without impairing its function as a gate array. That purpose is achieved.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a layout configuration of main parts of a semiconductor integrated circuit device to which the technology of the present invention is applied.

The semiconductor integrated circuit device shown in the figure is configured as a gate array having a MOS type or a bipolar/MO3 composite type structure.

First, in the center of the semiconductor substrate 1, a gate array section 2 is arranged in which a large number of standard cells (not shown) are regularly arranged at high density. Outside the gate array section 2 and at the periphery of the semiconductor substrate 1, a buffer region 3 in which a large number of human output buffer circuit sections 31 are arranged in a line is arranged. Further, outside this buffer area 3, a terminal area 4 is placed in which terminal pads (not shown) are arranged in a line at predetermined intervals.

Further, along the top of the buffer region 3, a pair of power supply bus lines 5.6 made of a second layer of aluminum wiring are laid in parallel. In this pair of power supply buses 5.6, one bus 5 is connected to the high side power supply potential VcC, and the other bus 6 is connected to the low side reference potential, that is, the ground potential GND. By positioning the buffer area 3 under the two power supply buses 5 and 6 of VcC and GND, which are wired together, the power is applied equally to each of the cover sofa circuit sections 31 in the buffer area 4. It is now possible to supply.

The part where it is not possible to wire the VCC and GND power supply buses 5 and 6 in alignment is a dead space where the human output buffer circuit section 31 cannot be placed under it because power cannot be supplied evenly. becomes. This dead space occurs at the corner portion 7 where the running direction of the pair of power supply buses 5 and 6 changes. At the corner portion 7 where the power busbars 5 and 6 are bent, as shown in FIG. ) is separated from the position of the crowd buffer circuit section 31', and power cannot be supplied under the same conditions as the other input/output buffer sections 31.

In the semiconductor integrated circuit device of the embodiment shown in FIG. 1, the capacitive element 8 is formed using the area of the corner portion 7, which is a dead space.

2 and 3 show a specific example of the element structure of the capacitive element 8 formed in the corner portion 7, FIG. 2 shows its planar layout state, and FIG. 3 shows its cross-sectional state. are shown respectively.

In the figure, a well diffusion layer 81 is selectively formed in the capacitive element 7, a gate electrode 83 is formed on this diffusion layer 81 with an oxide insulating film 82 in between, and a gate electrode 83 is formed on this diffusion layer 81 with an oxide insulating film 82 in between. An insulating film 84 is placed between the eyebrows, and one side 6 of the power supply busbars is positioned so as to overlap.

The well diffusion layer 81 has a power source 16 located above it.
is connected to the same potential (Vcc/GND) as the gate electrode 8
3 is a potential (GND/V
cc).

This creates capacitances C1 and C between the power supply bus 6 and the gate electrode 83 and between the diffusion layer 81 and the gate electrode 83, respectively.
2 is formed, and the parallel combined capacitance C1+C2 of these two capacitors C1 and C2 becomes the capacitance of the capacitive element 8. The capacitance C1+C2 of this capacitive element 8 is the power supply Vcc−G
A power supply bypass circuit is formed by being connected equally sparingly in parallel to ND.

Furthermore, in the embodiment, the gate electrode 83 has a slit 83a.
By providing this, the effective area of the gate electrode 83 is expanded and the capacitance C1 between the power supply bus 6 and the gate electrode 83 is increased.

As described above, the corner portion 7 which cannot be used as either the gate array portion 2 or the buffer region 3
A capacitive element 8 with a relatively large capacity is formed in. Thereby, a power supply bypass capacitor is formed without increasing the area of the semiconductor substrate 1 and without impairing the function of the gate array.

In this case, if a power supply bypass circuit is formed using a capacitive element within the semiconductor substrate 1, there is a concern that a portion of the pulsed bypass current may stray into the substrate 1 and adversely affect the internal circuit section. However, since the power supply bypass circuit formed by the capacitive element 8 is formed in the corner section 7 that is farthest from the gate array section 2, which is the internal circuit section, there is little possibility of an adverse effect on the internal circuit.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

For example, the capacitive element 8 may be formed using junction capacitance due to a diffusion layer. Further, an MIS (metal-insulator-semiconductor) type structure other than MO5 may be used.

In the above explanation, the invention made by the present inventor was mainly applied to gate arrays, which is the background field of application, but the invention is not limited to this, for example, PLA (programmable logic array).
It can also be applied to

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to have a large capacitance element that can be used, for example, as a power supply bypass, without increasing the area of the semiconductor substrate and without impairing the function of the gate array.

[Brief explanation of the drawing]

FIG. 1 is a plan view partially showing essential parts of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view showing a portion of a capacitive element, and FIG. 3 is a partial plan view of a capacitive element. FIG. 1... Semiconductor substrate, 2... Gate array section, 3
... Buffer area, 31... Input/output buffer circuit section, 4... Terminal area, 5, 6... Power bus line,
7... Corner part, 8... Capacitive element, 81...
...Well diffusion layer, 82...Oxide insulating film, 83...
...Gate electrode, 84...Interlayer insulating film, C1, C2
...Capacitance generated in capacitive element 8.

Claims (1)

[Claims] 1. A gate array portion formed in the center of the semiconductor substrate, a buffer region formed along the periphery of the semiconductor substrate, and a terminal region formed outside the buffer region. A semiconductor integrated circuit device comprising: a pair of power supply busbars wired along the buffer region; and a capacitive element formed using the area of a corner portion where the running direction of the pair of power supply busbars changes. 2. The semiconductor integrated circuit device according to claim 1, wherein a MOS (metal-oxide-semiconductor) or MIS (metal-insulator-semiconductor) capacitive element is formed under the corner portion of the power supply bus. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the capacitive element formed at the corner of the power supply bus is connected in parallel to the power supply as a bypass capacitor.