JP2011501397A - 極薄チップパッケージング - Google Patents
極薄チップパッケージング Download PDFInfo
- Publication number
- JP2011501397A JP2011501397A JP2010504906A JP2010504906A JP2011501397A JP 2011501397 A JP2011501397 A JP 2011501397A JP 2010504906 A JP2010504906 A JP 2010504906A JP 2010504906 A JP2010504906 A JP 2010504906A JP 2011501397 A JP2011501397 A JP 2011501397A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- stable base
- applying
- medium
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 94
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000011248 coating agent Substances 0.000 claims abstract description 45
- 238000000576 coating method Methods 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000001066 destructive effect Effects 0.000 claims description 2
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 33
- 235000012431 wafers Nutrition 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 16
- 238000012545 processing Methods 0.000 description 15
- 238000013459 approach Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 13
- 230000008901 benefit Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000012811 non-conductive material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
Description
Claims (24)
- i)第1チップを安定ベースに取り付けるステップと;
ii)前記安定ベース上の位置に接点パッドを形成するステップと;
iii)前記第1チップの面を電気的に絶縁するように媒体を前記安定ベース上に適用するステップと;
iv)前記媒体上に電気経路を形成するステップと;
v)第2チップの少なくとも1つの電気的接続点を前記第1チップの少なくとも1つの電気的接続点と物理的に接触させることにより、前記第2チップを前記第1チップに取り付けてアセンブリを形成するステップと;
vi)前記安定ベースを除去するステップを備える;
パッケージング方法。 - i)のステップの前に、前記安定ベース上にサポートコーティングを適用するステップをさらに備える;
請求項1の方法。 - 前記媒体を適用する前記ステップは、前記第1チップの前記安定ベースとは反対側の表面に実質的に一致するか、または超える、前記安定ベースから上の高さまで前記媒体を適用するステップを備える;
請求項1の方法。 - 少なくとも1つの接点パッドの前記安定ベースとは反対側を露出させるために選択領域において前記媒体を除去するステップをさらに備える;
請求項3の方法。 - i)のステップの前に、前記安定ベース上に接着材を適用するステップをさらに備える;
請求項1の方法。 - 前記サポートコーティングを適用する前記ステップは、誘電材料を適用するステップを備える;
請求項2の方法。 - 前記サポートコーティングを適用する前記ステップは、エッチング停止材料を適用するステップを備える;
請求項2の方法。 - 前記サポートコーティングを適用する前記ステップは、犠牲層材料を適用するステップを備える;
請求項2の方法。 - 前記安定ベースを除去する前記ステップは、前記犠牲層を消失させるステップを備える;
請求項1の方法。 - 前記犠牲層を消失させる前記ステップは、前記犠牲層を加熱するステップを備える;
請求項9の方法。 - 前記犠牲層を消失させる前記ステップは、前記犠牲層をエッチングするステップを備える;
請求項9の方法。 - 前記犠牲層を消失させる前記ステップは、前記犠牲層を破壊的化学反応に晒すステップを備える;
請求項9の方法。 - 前記安定ベースを除去する前記ステップは、前記安定ベースをウェットエッチングするステップを備える;
請求項1の方法。 - 前記電気経路を形成する前記ステップは、金属を堆積させるステップを備える;
請求項1の方法。 - 前記電気経路を形成する前記ステップは、金属を電気めっきするステップを備える;
請求項1の方法。 - 前記電気経路を形成する前記ステップは、金属を無電解めっきするステップを備える;
請求項1の方法。 - 前記安定ベースを除去する前記ステップは、前記安定ベースをエッチング除去するステップを備える;
請求項2の方法。 - 前記サポートコーティングはエッチング停止材であり、
前記安定ベースをエッチング除去するステップは、前記第1チップが取り付けられる面の反対側から、前記エッチング停止材に達するまで、前記安定ベースをエッチングするステップを備える;
請求項17の方法。 - 前記エッチング停止材に達した後に、前記エッチング停止材を除去するステップをさらに備える;
請求項18の方法。 - 前記安定ベースを除去するステップは、前記安定ベースを研削除去するステップを備える;
請求項1の方法。 - 前記安定ベースを除去するステップは、前記安定ベースをラッピング除去するステップを備える;
請求項1の方法。 - v)のステップとvi)のステップの間に、前記方法は、前記第2チップを収納する前記アセンブリの1つの面上にコーティング材を付加するステップを備える;
請求項1の方法。 - 互いに電気的に接続される少なくとも2つのチップと;
少なくとも1つの接点パッドと;
前記接点パッドから前記チップの少なくとも一方の上の接点まで延在する導電経路と;
前記接点パッドの上で、かつ前記チップのうちの第1チップの周辺に存在する平坦化媒体と;
前記平坦化媒体上のコーティング材であって、前記導電経路の少なくとも一部は前記コーティング材と前記平坦化媒体との間に位置し、前記コーティング材は前記チップのうちの第2チップの少なくとも一部を覆う、コーティング材とを備える;
パッケージ。 - 前記コーティング材と前記平坦化媒体の少なくとも一方はポリマーである、
請求項23のパッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/738,817 US7960210B2 (en) | 2007-04-23 | 2007-04-23 | Ultra-thin chip packaging |
PCT/IB2008/001626 WO2008129424A2 (en) | 2007-04-23 | 2008-06-20 | Ultra-thin stacked chios packaging |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011501397A true JP2011501397A (ja) | 2011-01-06 |
JP4970593B2 JP4970593B2 (ja) | 2012-07-11 |
Family
ID=39789478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010504906A Active JP4970593B2 (ja) | 2007-04-23 | 2008-06-20 | 極薄チップパッケージング |
Country Status (6)
Country | Link |
---|---|
US (2) | US7960210B2 (ja) |
EP (1) | EP2361439A2 (ja) |
JP (1) | JP4970593B2 (ja) |
KR (2) | KR101157726B1 (ja) |
CN (1) | CN101663747B (ja) |
WO (1) | WO2008129424A2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012169440A (ja) * | 2011-02-14 | 2012-09-06 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2013110264A (ja) * | 2011-11-21 | 2013-06-06 | Fujitsu Semiconductor Ltd | 半導体装置及び半導体装置の製造方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100099012A1 (en) * | 2008-10-17 | 2010-04-22 | Brookhaven Science Associates, Llc | Electrocatalyst Synthesized by Depositing a Contiguous Metal Adlayer on Transition Metal Nanostructures |
US7838337B2 (en) * | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8895440B2 (en) | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
US10153179B2 (en) | 2012-08-24 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company | Carrier warpage control for three dimensional integrated circuit (3DIC) stacking |
DE102013104111B4 (de) | 2012-08-24 | 2018-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zum Ausbilden einer Package-on-Package-(PoP)-Vorrichtung mit einer Träger-Verwerfungssteuerung für die dreidimensional integierte Schaltkreis-(3DIC)-Stapelung |
US9287204B2 (en) | 2012-12-20 | 2016-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form |
KR101523274B1 (ko) * | 2013-06-28 | 2015-05-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
TWI576870B (zh) * | 2013-08-26 | 2017-04-01 | 精材科技股份有限公司 | 電感結構及其製作方法 |
US9299614B2 (en) * | 2013-12-10 | 2016-03-29 | Applied Materials, Inc. | Method and carrier for dicing a wafer |
US20150255366A1 (en) * | 2014-03-06 | 2015-09-10 | Apple Inc. | Embedded system in package |
KR101587740B1 (ko) | 2014-11-10 | 2016-01-22 | 한국가스공사 | 접촉식 자왜 피도파 변환기 모듈 |
US11362027B2 (en) | 2020-02-28 | 2022-06-14 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003078105A (ja) * | 2001-08-30 | 2003-03-14 | Hynix Semiconductor Inc | スタックチップモジュール |
JP2004320059A (ja) * | 2004-08-16 | 2004-11-11 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2006134914A (ja) * | 2004-11-02 | 2006-05-25 | Dainippon Printing Co Ltd | 電子部品内蔵モジュール |
JP2007059821A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2007180529A (ja) * | 2005-12-02 | 2007-07-12 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2007250906A (ja) * | 2006-03-16 | 2007-09-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Family Cites Families (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3312878A (en) | 1965-06-01 | 1967-04-04 | Ibm | High speed packaging of miniaturized circuit modules |
US5399898A (en) | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
JPH0831617B2 (ja) | 1990-04-18 | 1996-03-27 | 三菱電機株式会社 | 太陽電池及びその製造方法 |
JP2918307B2 (ja) | 1990-08-07 | 1999-07-12 | 沖電気工業株式会社 | 半導体記憶素子 |
KR940006696B1 (ko) | 1991-01-16 | 1994-07-25 | 금성일렉트론 주식회사 | 반도체 소자의 격리막 형성방법 |
EP0516866A1 (en) | 1991-05-03 | 1992-12-09 | International Business Machines Corporation | Modular multilayer interwiring structure |
US6094058A (en) * | 1991-06-04 | 2000-07-25 | Micron Technology, Inc. | Temporary semiconductor package having dense array external contacts |
US5308784A (en) | 1991-10-02 | 1994-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for making the same |
US5603847A (en) | 1993-04-07 | 1997-02-18 | Zycon Corporation | Annular circuit components coupled with printed circuit board through-hole |
US5587119A (en) | 1994-09-14 | 1996-12-24 | E-Systems, Inc. | Method for manufacturing a coaxial interconnect |
DE4433845A1 (de) | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
US5814889A (en) | 1995-06-05 | 1998-09-29 | Harris Corporation | Intergrated circuit with coaxial isolation and method |
US5608264A (en) | 1995-06-05 | 1997-03-04 | Harris Corporation | Surface mountable integrated circuit with conductive vias |
US5872051A (en) | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
JP2739855B2 (ja) | 1995-12-14 | 1998-04-15 | 日本電気株式会社 | 半導体装置およびその製造方法 |
TW303502B (en) | 1996-01-11 | 1997-04-21 | Micron Technology Inc | Temporary semiconductor package having dense array external contacts |
US5973396A (en) | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
US6310484B1 (en) | 1996-04-01 | 2001-10-30 | Micron Technology, Inc. | Semiconductor test interconnect with variable flexure contacts |
US5872338A (en) | 1996-04-10 | 1999-02-16 | Prolinx Labs Corporation | Multilayer board having insulating isolation rings |
JP2790122B2 (ja) | 1996-05-31 | 1998-08-27 | 日本電気株式会社 | 積層回路基板 |
US7052941B2 (en) | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
JP3176307B2 (ja) | 1997-03-03 | 2001-06-18 | 日本電気株式会社 | 集積回路装置の実装構造およびその製造方法 |
JPH10335383A (ja) | 1997-05-28 | 1998-12-18 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH11166935A (ja) | 1997-09-25 | 1999-06-22 | Canon Inc | 光検出または照射用の光プローブと該プローブを備えた近視野光学顕微鏡、及該光プローブの製造方法とその製造に用いる基板 |
US6620731B1 (en) | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
US6075710A (en) | 1998-02-11 | 2000-06-13 | Express Packaging Systems, Inc. | Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips |
US5962922A (en) | 1998-03-18 | 1999-10-05 | Wang; Bily | Cavity grid array integrated circuit package |
US6222276B1 (en) | 1998-04-07 | 2001-04-24 | International Business Machines Corporation | Through-chip conductors for low inductance chip-to-chip integration and off-chip connections |
US6380023B2 (en) | 1998-09-02 | 2002-04-30 | Micron Technology, Inc. | Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits |
US6122187A (en) | 1998-11-23 | 2000-09-19 | Micron Technology, Inc. | Stacked integrated circuits |
US6316737B1 (en) | 1999-09-09 | 2001-11-13 | Vlt Corporation | Making a connection between a component and a circuit board |
JP3386029B2 (ja) | 2000-02-09 | 2003-03-10 | 日本電気株式会社 | フリップチップ型半導体装置及びその製造方法 |
US6446317B1 (en) | 2000-03-31 | 2002-09-10 | Intel Corporation | Hybrid capacitor and method of fabrication therefor |
JP2001338947A (ja) | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
US6393789B1 (en) * | 2000-07-12 | 2002-05-28 | Christopher P. Lanclos | Refractory anchor |
TW525417B (en) | 2000-08-11 | 2003-03-21 | Ind Tech Res Inst | Composite through hole structure |
US6577013B1 (en) | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
US6720245B2 (en) | 2000-09-07 | 2004-04-13 | Interuniversitair Microelektronica Centrum (Imec) | Method of fabrication and device for electromagnetic-shielding structures in a damascene-based interconnect scheme |
US7190080B1 (en) | 2000-10-13 | 2007-03-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
JP2002134545A (ja) | 2000-10-26 | 2002-05-10 | Oki Electric Ind Co Ltd | 半導体集積回路チップ及び基板、並びにその製造方法 |
JP4608763B2 (ja) | 2000-11-09 | 2011-01-12 | 日本電気株式会社 | 半導体装置 |
EP1217656A1 (en) | 2000-12-20 | 2002-06-26 | STMicroelectronics S.r.l. | Process for manufacturing components in a semiconductor material with reduction in the starting wafer thickness |
US6512300B2 (en) | 2001-01-10 | 2003-01-28 | Raytheon Company | Water level interconnection |
JP4118029B2 (ja) | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
US7218349B2 (en) | 2001-08-09 | 2007-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US6747347B2 (en) | 2001-08-30 | 2004-06-08 | Micron Technology, Inc. | Multi-chip electronic package and cooling system |
JP3495727B2 (ja) | 2001-11-07 | 2004-02-09 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
US6599778B2 (en) | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
US6590278B1 (en) | 2002-01-08 | 2003-07-08 | International Business Machines Corporation | Electronic package |
TW200302685A (en) * | 2002-01-23 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Circuit component built-in module and method of manufacturing the same |
US6770822B2 (en) | 2002-02-22 | 2004-08-03 | Bridgewave Communications, Inc. | High frequency device packages and methods |
US7135777B2 (en) | 2002-05-03 | 2006-11-14 | Georgia Tech Research Corporation | Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof |
US6939789B2 (en) | 2002-05-13 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of wafer level chip scale packaging |
SG111069A1 (en) | 2002-06-18 | 2005-05-30 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods |
JP3679786B2 (ja) | 2002-06-25 | 2005-08-03 | 松下電器産業株式会社 | 半導体装置の製造方法 |
SG111972A1 (en) | 2002-10-17 | 2005-06-29 | Agency Science Tech & Res | Wafer-level package for micro-electro-mechanical systems |
JP4056854B2 (ja) * | 2002-11-05 | 2008-03-05 | 新光電気工業株式会社 | 半導体装置の製造方法 |
TWI233172B (en) * | 2003-04-02 | 2005-05-21 | Siliconware Precision Industries Co Ltd | Non-leaded semiconductor package and method of fabricating the same |
ITTO20030269A1 (it) | 2003-04-08 | 2004-10-09 | St Microelectronics Srl | Procedimento per la fabbricazione di un dispositivo |
US20050046034A1 (en) | 2003-09-03 | 2005-03-03 | Micron Technology, Inc. | Apparatus and method for high density multi-chip structures |
TWI251313B (en) | 2003-09-26 | 2006-03-11 | Seiko Epson Corp | Intermediate chip module, semiconductor device, circuit board, and electronic device |
US20050104027A1 (en) | 2003-10-17 | 2005-05-19 | Lazarev Pavel I. | Three-dimensional integrated circuit with integrated heat sinks |
JP4303563B2 (ja) * | 2003-11-12 | 2009-07-29 | 大日本印刷株式会社 | 電子装置および電子装置の製造方法 |
US7276787B2 (en) | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US7230318B2 (en) | 2003-12-24 | 2007-06-12 | Agency For Science, Technology And Research | RF and MMIC stackable micro-modules |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
US7268012B2 (en) * | 2004-08-31 | 2007-09-11 | Micron Technology, Inc. | Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby |
US7157310B2 (en) | 2004-09-01 | 2007-01-02 | Micron Technology, Inc. | Methods for packaging microfeature devices and microfeature devices formed by such methods |
DE102005026098B3 (de) | 2005-06-01 | 2007-01-04 | Infineon Technologies Ag | Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung derselben |
TWI251922B (en) * | 2005-07-14 | 2006-03-21 | Siliconware Precision Industries Co Ltd | Multichip stack structure |
IL171378A (en) | 2005-10-11 | 2010-11-30 | Dror Hurwitz | Integrated circuit support structures and the fabrication thereof |
US20080197474A1 (en) * | 2007-02-16 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with multi-chips and method of the same |
-
2007
- 2007-04-23 US US11/738,817 patent/US7960210B2/en active Active
-
2008
- 2008-06-20 EP EP08762937A patent/EP2361439A2/en not_active Withdrawn
- 2008-06-20 CN CN2008800129833A patent/CN101663747B/zh active Active
- 2008-06-20 JP JP2010504906A patent/JP4970593B2/ja active Active
- 2008-06-20 KR KR1020097023473A patent/KR101157726B1/ko active IP Right Grant
- 2008-06-20 KR KR1020127002724A patent/KR101245928B1/ko active IP Right Grant
- 2008-06-20 WO PCT/IB2008/001626 patent/WO2008129424A2/en active Application Filing
-
2009
- 2009-07-08 US US12/499,554 patent/US20090267219A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003078105A (ja) * | 2001-08-30 | 2003-03-14 | Hynix Semiconductor Inc | スタックチップモジュール |
JP2004320059A (ja) * | 2004-08-16 | 2004-11-11 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2006134914A (ja) * | 2004-11-02 | 2006-05-25 | Dainippon Printing Co Ltd | 電子部品内蔵モジュール |
JP2007059821A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2007180529A (ja) * | 2005-12-02 | 2007-07-12 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2007250906A (ja) * | 2006-03-16 | 2007-09-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012169440A (ja) * | 2011-02-14 | 2012-09-06 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2013110264A (ja) * | 2011-11-21 | 2013-06-06 | Fujitsu Semiconductor Ltd | 半導体装置及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101663747A (zh) | 2010-03-03 |
JP4970593B2 (ja) | 2012-07-11 |
KR20100020939A (ko) | 2010-02-23 |
KR101157726B1 (ko) | 2012-06-21 |
WO2008129424A2 (en) | 2008-10-30 |
US20080258284A1 (en) | 2008-10-23 |
KR101245928B1 (ko) | 2013-03-20 |
KR20120055547A (ko) | 2012-05-31 |
US7960210B2 (en) | 2011-06-14 |
CN101663747B (zh) | 2013-05-22 |
US20090267219A1 (en) | 2009-10-29 |
WO2008129424A3 (en) | 2008-12-18 |
EP2361439A2 (en) | 2011-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4970593B2 (ja) | 極薄チップパッケージング | |
US11443995B2 (en) | Integrated circuit package and method | |
US10720409B2 (en) | Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same | |
US11854988B2 (en) | Semiconductor device and method of manufacture | |
TWI429046B (zh) | 半導體裝置及其製造方法 | |
US7956443B2 (en) | Through-wafer interconnects for photoimager and memory wafers | |
TWI451505B (zh) | 凹入的半導體基底和相關技術 | |
TWI389277B (zh) | 藉由一附有凹槽之環狀孔的晶粒堆疊 | |
CN111799227B (zh) | 半导体器件及其形成方法 | |
US11854921B2 (en) | Integrated circuit package and method | |
CN111033732A (zh) | 使用导线接合的混合式添加结构的可堆叠存储器裸片 | |
JP2007180529A (ja) | 半導体装置およびその製造方法 | |
TW200834769A (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP5003023B2 (ja) | 基板処理方法及び半導体装置の製造方法 | |
US20220392884A1 (en) | Integrated Circuit Package and Method | |
US20240021554A1 (en) | Integrated circuit package and method of forming thereof | |
KR20220115850A (ko) | 칩릿 인터포저 | |
TW202238877A (zh) | 半導體封裝及製造半導體封裝的方法 | |
TWI838073B (zh) | 積體電路封裝及其形成方法 | |
TWI842343B (zh) | 裝置封裝、半導體封裝及封裝方法 | |
US20240213236A1 (en) | Integrated circuit package and method | |
TW202410370A (zh) | 半導體封裝及其製造方法 | |
TW202301516A (zh) | 拾取裝置及其使用方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110902 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111129 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120315 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120404 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150413 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4970593 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |