JP2011146711A5 - - Google Patents

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Publication number
JP2011146711A5
JP2011146711A5 JP2011004797A JP2011004797A JP2011146711A5 JP 2011146711 A5 JP2011146711 A5 JP 2011146711A5 JP 2011004797 A JP2011004797 A JP 2011004797A JP 2011004797 A JP2011004797 A JP 2011004797A JP 2011146711 A5 JP2011146711 A5 JP 2011146711A5
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JP
Japan
Prior art keywords
substrate
copper
dielectric
layer
aluminum
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JP2011004797A
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English (en)
Japanese (ja)
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JP5773306B2 (ja
JP2011146711A (ja
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Publication date
Priority claimed from US12/688,154 external-priority patent/US8268722B2/en
Priority claimed from US12/689,803 external-priority patent/US7858510B1/en
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Publication of JP2011146711A publication Critical patent/JP2011146711A/ja
Publication of JP2011146711A5 publication Critical patent/JP2011146711A5/ja
Application granted granted Critical
Publication of JP5773306B2 publication Critical patent/JP5773306B2/ja
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JP2011004797A 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置 Active JP5773306B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/688,154 US8268722B2 (en) 2009-06-03 2010-01-15 Interfacial capping layers for interconnects
US12/688,154 2010-01-15
US12/689,803 US7858510B1 (en) 2008-02-28 2010-01-19 Interfacial layers for electromigration resistance improvement in damascene interconnects
US12/689,803 2010-01-19

Publications (3)

Publication Number Publication Date
JP2011146711A JP2011146711A (ja) 2011-07-28
JP2011146711A5 true JP2011146711A5 (de) 2014-02-27
JP5773306B2 JP5773306B2 (ja) 2015-09-02

Family

ID=44268066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011004797A Active JP5773306B2 (ja) 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置

Country Status (4)

Country Link
JP (1) JP5773306B2 (de)
KR (1) KR101742825B1 (de)
CN (1) CN102130046B (de)
TW (2) TW201709418A (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727881B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7727880B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
KR20190077619A (ko) 2011-06-03 2019-07-03 노벨러스 시스템즈, 인코포레이티드 상호접속을 위한 캡핑층들을 함유하는 금속 및 실리콘
CN104008995B (zh) * 2013-02-22 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
EP2965347A4 (de) * 2013-03-05 2017-02-15 Entegris, Inc. Ionenimplantationszusammensetzungen, systeme und verfahren
WO2015013266A1 (en) * 2013-07-24 2015-01-29 Applied Materials, Inc Cobalt substrate processing systems, apparatus, and methods
CN104576514B (zh) * 2013-10-29 2017-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN104637864B (zh) * 2013-11-14 2017-11-24 中芯国际集成电路制造(上海)有限公司 提高数据保持能力的方法
US9368448B2 (en) * 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US9465071B2 (en) 2014-03-04 2016-10-11 Mediatek Inc. Method and apparatus for generating featured scan pattern
US10319908B2 (en) * 2014-05-01 2019-06-11 Crossbar, Inc. Integrative resistive memory in backend metal layers
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
JP6998945B2 (ja) * 2016-10-02 2022-01-18 アプライド マテリアルズ インコーポレイテッド ルテニウムライナーと共に銅のエレクトロマイグレーションを改善するドープされた選択的な金属キャップ
US9859153B1 (en) * 2016-11-14 2018-01-02 Lam Research Corporation Deposition of aluminum oxide etch stop layers
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法
US20190127212A1 (en) * 2017-10-31 2019-05-02 Texas Instruments Incorporated Forming a passivation coating for mems devices
US10741440B2 (en) * 2018-06-05 2020-08-11 Lam Research Corporation Metal liner passivation and adhesion enhancement by zinc doping
US10707119B1 (en) * 2019-01-14 2020-07-07 Globalfoundries Inc. Interconnect structures with airgaps and dielectric-capped interconnects
CN111769074B (zh) * 2019-04-02 2024-09-27 长鑫存储技术有限公司 半导体互连结构及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0765179B2 (ja) * 1987-05-15 1995-07-12 日本電信電話株式会社 化学的気相成長方法
US6605531B1 (en) * 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US20020048926A1 (en) * 2000-09-14 2002-04-25 Konecni Anthony J. Method for forming a self-aligned copper capping diffusion barrier
US6664182B2 (en) * 2001-04-25 2003-12-16 Macronix International Co. Ltd. Method of improving the interlayer adhesion property of low-k layers in a dual damascene process
US6518167B1 (en) * 2002-04-16 2003-02-11 Advanced Micro Devices, Inc. Method of forming a metal or metal nitride interface layer between silicon nitride and copper
JP2006505127A (ja) * 2002-10-29 2006-02-09 エーエスエム　インターナショナル　エヌ．ヴェー． 酸素架橋構造及び方法
KR100564801B1 (ko) * 2003-12-30 2006-03-28 동부아남반도체 주식회사 반도체 제조 방법
US7102232B2 (en) * 2004-04-19 2006-09-05 International Business Machines Corporation Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer
US7704873B1 (en) * 2004-11-03 2010-04-27 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
TW200802703A (en) * 2005-11-28 2008-01-01 Nxp Bv Method of forming a self aligned copper capping layer
JP2007180408A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US7754588B2 (en) * 2007-09-28 2010-07-13 Tel Epion Inc. Method to improve a copper/dielectric interface in semiconductor devices

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