KR101742825B1 - 다마신 인터커넥트에서 전자이동 저항성 개선을 위한 계면층 - Google Patents

다마신 인터커넥트에서 전자이동 저항성 개선을 위한 계면층 Download PDF

Info

Publication number
KR101742825B1
KR101742825B1 KR1020110004334A KR20110004334A KR101742825B1 KR 101742825 B1 KR101742825 B1 KR 101742825B1 KR 1020110004334 A KR1020110004334 A KR 1020110004334A KR 20110004334 A KR20110004334 A KR 20110004334A KR 101742825 B1 KR101742825 B1 KR 101742825B1
Authority
KR
South Korea
Prior art keywords
layer
copper
substrate
insulating film
aluminum
Prior art date
Application number
KR1020110004334A
Other languages
English (en)
Korean (ko)
Other versions
KR20110084130A (ko
Inventor
아난다 바너지
조니 앤드류 안토넬리
제니퍼 오'러플린
만디얌 스리람
바트 반 슈라벤디즈크
세샤사이 바라다라잔
Original Assignee
노벨러스 시스템즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/688,154 external-priority patent/US8268722B2/en
Priority claimed from US12/689,803 external-priority patent/US7858510B1/en
Application filed by 노벨러스 시스템즈, 인코포레이티드 filed Critical 노벨러스 시스템즈, 인코포레이티드
Publication of KR20110084130A publication Critical patent/KR20110084130A/ko
Application granted granted Critical
Publication of KR101742825B1 publication Critical patent/KR101742825B1/ko

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020110004334A 2010-01-15 2011-01-17 다마신 인터커넥트에서 전자이동 저항성 개선을 위한 계면층 KR101742825B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/688,154 US8268722B2 (en) 2009-06-03 2010-01-15 Interfacial capping layers for interconnects
US12/688,154 2010-01-15
US12/689,803 2010-01-19
US12/689,803 US7858510B1 (en) 2008-02-28 2010-01-19 Interfacial layers for electromigration resistance improvement in damascene interconnects

Publications (2)

Publication Number Publication Date
KR20110084130A KR20110084130A (ko) 2011-07-21
KR101742825B1 true KR101742825B1 (ko) 2017-06-01

Family

ID=44268066

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110004334A KR101742825B1 (ko) 2010-01-15 2011-01-17 다마신 인터커넥트에서 전자이동 저항성 개선을 위한 계면층

Country Status (4)

Country Link
JP (1) JP5773306B2 (de)
KR (1) KR101742825B1 (de)
CN (1) CN102130046B (de)
TW (2) TW201709418A (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727881B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7727880B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
CN103582932B (zh) 2011-06-03 2017-01-18 诺发系统公司 用于互连的包含金属和硅的盖层
CN104008995B (zh) * 2013-02-22 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
SG11201506605XA (en) * 2013-03-05 2015-09-29 Entegris Inc Ion implantation compositions, systems, and methods
CN105378907A (zh) * 2013-07-24 2016-03-02 应用材料公司 钴基板处理系统、设备及方法
CN104576514B (zh) * 2013-10-29 2017-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN104637864B (zh) * 2013-11-14 2017-11-24 中芯国际集成电路制造(上海)有限公司 提高数据保持能力的方法
US9368448B2 (en) * 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US9465071B2 (en) * 2014-03-04 2016-10-11 Mediatek Inc. Method and apparatus for generating featured scan pattern
US10319908B2 (en) * 2014-05-01 2019-06-11 Crossbar, Inc. Integrative resistive memory in backend metal layers
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
KR20230026514A (ko) 2016-10-02 2023-02-24 어플라이드 머티어리얼스, 인코포레이티드 루테늄 라이너로 구리 전자 이동을 개선하기 위한 도핑된 선택적 금속 캡
US9859153B1 (en) * 2016-11-14 2018-01-02 Lam Research Corporation Deposition of aluminum oxide etch stop layers
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法
US20190127212A1 (en) * 2017-10-31 2019-05-02 Texas Instruments Incorporated Forming a passivation coating for mems devices
US10741440B2 (en) * 2018-06-05 2020-08-11 Lam Research Corporation Metal liner passivation and adhesion enhancement by zinc doping
US10707119B1 (en) * 2019-01-14 2020-07-07 Globalfoundries Inc. Interconnect structures with airgaps and dielectric-capped interconnects
CN111769074B (zh) * 2019-04-02 2024-09-27 长鑫存储技术有限公司 半导体互连结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001524754A (ja) 1997-11-26 2001-12-04 アプライド マテリアルズ インコーポレイテッド Cvdアルミニウム及びpvdアルミニウム集積を用いた新しいホール充填技術
JP2002164351A (ja) 2000-09-14 2002-06-07 Texas Instruments Inc 自己整合型銅キャップ拡散障壁形成方法
US20050142833A1 (en) 2003-12-30 2005-06-30 Dongbuanam Semiconductor Inc. Method of fabricating semiconductor device
US20070145600A1 (en) 2005-12-28 2007-06-28 Hisashi Yano Semiconductor device and manufacturing method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0765179B2 (ja) * 1987-05-15 1995-07-12 日本電信電話株式会社 化学的気相成長方法
US6664182B2 (en) * 2001-04-25 2003-12-16 Macronix International Co. Ltd. Method of improving the interlayer adhesion property of low-k layers in a dual damascene process
US6518167B1 (en) * 2002-04-16 2003-02-11 Advanced Micro Devices, Inc. Method of forming a metal or metal nitride interface layer between silicon nitride and copper
JP2006505127A (ja) * 2002-10-29 2006-02-09 エーエスエム インターナショナル エヌ.ヴェー. 酸素架橋構造及び方法
US7102232B2 (en) * 2004-04-19 2006-09-05 International Business Machines Corporation Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer
US7704873B1 (en) * 2004-11-03 2010-04-27 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
TW200802703A (en) * 2005-11-28 2008-01-01 Nxp Bv Method of forming a self aligned copper capping layer
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US7754588B2 (en) * 2007-09-28 2010-07-13 Tel Epion Inc. Method to improve a copper/dielectric interface in semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001524754A (ja) 1997-11-26 2001-12-04 アプライド マテリアルズ インコーポレイテッド Cvdアルミニウム及びpvdアルミニウム集積を用いた新しいホール充填技術
JP2002164351A (ja) 2000-09-14 2002-06-07 Texas Instruments Inc 自己整合型銅キャップ拡散障壁形成方法
US20050142833A1 (en) 2003-12-30 2005-06-30 Dongbuanam Semiconductor Inc. Method of fabricating semiconductor device
US20070145600A1 (en) 2005-12-28 2007-06-28 Hisashi Yano Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN102130046A (zh) 2011-07-20
KR20110084130A (ko) 2011-07-21
TW201709418A (zh) 2017-03-01
CN102130046B (zh) 2015-01-14
TWI612618B (zh) 2018-01-21
JP2011146711A (ja) 2011-07-28
JP5773306B2 (ja) 2015-09-02
TW201138024A (en) 2011-11-01

Similar Documents

Publication Publication Date Title
KR101742825B1 (ko) 다마신 인터커넥트에서 전자이동 저항성 개선을 위한 계면층
US7858510B1 (en) Interfacial layers for electromigration resistance improvement in damascene interconnects
US7648899B1 (en) Interfacial layers for electromigration resistance improvement in damascene interconnects
US8268722B2 (en) Interfacial capping layers for interconnects
TWI541938B (zh) 用於互連的含金屬及矽覆蓋層
US11587829B2 (en) Doping control of metal nitride films
US7704873B1 (en) Protective self-aligned buffer layers for damascene interconnects
US7135403B2 (en) Method for forming metal interconnection line in semiconductor device
US8865594B2 (en) Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US7915166B1 (en) Diffusion barrier and etch stop films
US6955983B2 (en) Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
KR20140099311A (ko) 구리 배리어 용도들을 위한 도핑된 탄탈룸 질화물
US20020132469A1 (en) Method for forming metal wiring layer
US20080157375A1 (en) Semiconductor device having a metal interconnection and method of fabricating the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant