KR101742825B1 - Interfacial layers for electromigration resistance improvement in damascene interconnects - Google Patents

Abstract

The electron mobility of the interconnect can be improved by using a protective cap existing at the interface between the metal wiring and the insulating film diffusion barrier (or etch stop) layer. The protective cap is formed by treating the oxide-free copper surface with an organoaluminum compound in the absence of plasma at a substrate temperature of about 350 DEG C and depositing a first layer of aluminum-containing material over the exposed copper. The formed aluminum-containing layer is chemically changed to partially or totally passivate to form a bond of Al-N, Al-O, or both Al-O and Al-N in the layer. In some embodiments, a passivation is formed by contacting a substrate having an exposed first layer with an oxygen-containing reactant and / or a nitrogen-containing reactant in the absence of a plasma. A protective cap may be formed on the substrate including the exposed ULK. The aluminum-containing layer normally present in the insulating film portion will spontaneously form a non-conductive layer having Al-O bonds.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an interfacial layer for improving electromagnetic transfer resistance in a damascene interconnect,

The present invention relates to a method of forming a layer of material on a partially fabricated integrated circuit, and more particularly to a method of forming a protective cap in a copper interconnect to improve the electron mobility of a damascene interconnect.

The damascene process is a method of forming a metal wiring on an integrated circuit. The damascene process involves forming a trench formed in an insulating layer (interlayer insulating film) and an inlaid metal wiring in the via. A damascene process is often considered a preferred method because it requires fewer processing steps than other methods and provides a higher yield. The damascene process is particularly suitable for metals such as copper that can not be readily patterned by plasma etching.

In a typical damascene process flow, a metal is deposited over the patterned insulating film to fill the via and the trench formed in the insulating layer. A final metallization layer is usually formed directly on the layer with the active element or above the metallization layer placed lower. A thin layer of an insulating film diffusion barrier material such as silicon carbide or silicon nitride may be deposited between adjacent metal interconnection layers to prevent metal from diffusing into the bulk layer of the insulating film. Also in some cases, the silicon carbide or silicon nitride insulating film diffusion barrier layer also serves as an etch stop layer during patterning of an interlayer dielectric (ILD).

In a typical integrated circuit (IC), several metallization layers are deposited on top of each other to form a stack, where metal-filled vias and trenches serve as IC conducting paths. The conduction path of one metallization layer is connected to the conduction path of the underlying or overlying layer by a series of damascene interconnects.

Several problems are presented in the fabrication of these interconnects, which are becoming increasingly important in the dimensioning of ever-shrinking IC device features. Currently, there is a growing need for interconnect fabrication methods that can provide interconnects with improved lifetime and reliability at 90 nm technology nodes and at more advanced nodes.

One problem encountered during IC fabrication is electromigration failure. Electron transfer occurs when the high current density experienced by the interconnect results in the migration of metal atoms with current, resulting in the formation of voids in the interconnect. Ultimately, the formation of cavities can lead to device failure, which is known as an electron transport disorder. During miniaturization of ongoing IC devices, the interconnect dimensions are reduced and larger current densities are experienced by the interconnect. As a result, the possibility of electron mobility failure increases with the miniaturization of such devices. Copper has greater electron mobility resistance than aluminum, but even at copper interconnects, electron mobility disturbances are becoming a significant reliability problem at the 45 nm technology node and at the more advanced nodes.

A protective cap is presently provided at the interface between the metal wiring and the insulating film diffusion barrier (or etch stop) layer, and the protective cap can improve the electron mobility of the interconnects. A method of forming such a protective cap is also described. Advantageously, the protective cap described herein can be formed as a very thin layer present at the top of the metal interconnect at the interface with the insulating film diffusion barrier layer, without significantly increasing the interconnect resistance. The protective capping layer may comprise, for example, a solid solution, an alloy, or a compound of an interconnect metal (e.g., copper) and a doping element (e.g., boron, aluminum, titanium, etc.). In many embodiments, it is advantageous to select doping elements that either form an alloy with the interconnect metal or accumulate at the grain boundary thereby reducing migration of the interconnect metal atoms.

The method provided herein includes depositing a source layer of a dopant-generating material (e.g., a material containing B, Al, Ti, etc.) on an exposed metal interconnect, depositing an upper portion of the source layer over the passivation layer (E. G., Nitride or oxide), maintaining the unaltered portion of the dopant-generating source layer in contact with the interconnect metal, and subsequently depositing an unchanged portion of the source layer into the interconnect metal, So that the thickness of the protective cap can be adjusted. In one embodiment, the amount of dopant that is inserted into the interconnect is limited to the thickness of the unchanged portion of the source layer that is in contact with the interconnect. In other alternative embodiments, the amount of dopant that is inserted into the interconnect is controlled by adjusting the temperature during diffusion and / or reaction.

The resistance of the interconnect is often increased when a dopant or a large amount of readily diffusing dopant (e.g., Si or Ge) is deposited on the interconnect metal. Advantageously, the thin protective cap formed in this adjustable manner significantly reduces the resistance of the interconnect . In addition, as will be described below, the method provided herein is suitable for forming a protective capping layer from a dopant-generating source deposited on top of both the exposed metal and the insulating film with little or no choice . This method can also be used when the dopant-containing source layer is selectively deposited only on the metal layer without significant deposition on the insulating film.

According to an aspect of the present invention, a method of forming a semiconductor device structure is provided. In one embodiment, the method comprises the steps of: (a) depositing a substrate having an exposed layer of a first metal (e.g., copper or copper alloy) and an exposed layer of an insulating film with boron or a second metal (e.g., Al, Hf, Ti, Co, Ta , Mo, Ru, Sn, Sb, etc.) to deposit a source layer comprising boron or a second metal on both the insulating film and the first metal; (b) varying the upper portion of the source layer over the region of the first metal to form a passivation layer, wherein the portion of the unchanged source layer remains in contact with the layer of the first metal ; (c) allowing the active component from the unaltered source layer to diffuse into or react with the first metal to form a protective cap within the first metal layer.

In one embodiment, the substrate is a damascene structure having exposed copper interconnects embedded in a layer of intermetal dielectric. Prior to deposition of the source layer, the substrate may optionally be pre-cleaned to remove contaminants (e.g., copper oxide) from the copper surface. For example, pre-cleaning may be performed by exposing the substrate to a reducing gas of the plasma (e.g., H ₂ or NH ₃ ). A source layer containing a source of a dopant (active component) can then be deposited by contacting the substrate with a volatile dopant precursor at a specific temperature. Typically (though not necessarily) the deposition of the source layer is performed thermally in the absence of a plasma discharge. Pre-cleaning and source layer deposition can be performed in a CVD apparatus, for example, without vacuum break in the same process chamber.

In one embodiment, at a chamber temperature between about 200 and 400 캜 in the absence of plasma discharge, the substrate is exposed to a gas mixture containing B ₂ H ₆ (or other boron-containing precursor) and an inert carrier gas A boron-containing source layer is deposited by contact. The pressure in the deposition chamber is maintained in the range of about 0.5 to 10 Torr and the concentration of B ₂ H ₆ in the gas mixture is in the range of about 0.5 to 20% by volume. Under these conditions, a boron-containing source layer is deposited over both the exposed insulating layer and the metal portion of the substrate. The source layer was found to have a BH bond and will therefore be referred to as a BH _x layer.

In many embodiments, due to the higher precursor decomposition rate at the metal surface, a greater amount of dopant source material is deposited over the metal portion of the substrate as compared to the insulating film portion of the substrate. As a result, in these embodiments, the thickness of the source layer deposited over the metal portion is greater than the thickness of the source layer deposited over the insulating layer. However, in many boron-containing precursors and metal-containing precursors, the complete deposition selectivity between metal and insulating film is generally difficult to achieve. Advantageously, the deposition methods disclosed herein do not require absolute metal / insulating film selectivity in the deposition of the source layer.

In some embodiments, a metal halide, a metal hydride, a metal carbonyl, or a volatile metal compound such as a volatile organometallic compound under temperature and pressure suitable for causing precursor decomposition and deposition of a metal- Containing precursor is contacted with the substrate to deposit a metal-containing source layer. In many cases, a temperature and pressure range similar to those listed above for the deposition of the BH _x layer is used. Those skilled in the art will understand how to optimize deposition conditions for different types of metal precursors.

A number of metals are suitable as dopants for forming the protective cap. The metal includes metals that form an intermetallic phase with solid solution, alloy, or interconnect metal, and metals that can diffuse or accumulate at the crystal boundary of the interconnect. For example, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, and Sb may be used as components of the protective cap. Alloys and solid solutions of these metals with each other or with these metals and other metals may also be used. Volatile precursors for the aluminum-containing source layer include, but are not limited to, trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutylaluminum, and tris (diethylamino) aluminum. Suitable precursors for the deposition of other metals include bis (cyclopentadienyl) cobalt, cobalt (II) acetylacetone salts, tetrakis (dimethylamido) hafnium, tetrakis (diethylamido) hafnium, tetrakis Amido) molybdenum, tetrakis (dimethylamino) titanium (TDMAT), tetrakis (diethylamino) titanium (TDEAT), tetrakis (ethylmethylamido) titanium, bis (diethylamino) bis ) Titanium, pentakis (dimethylamino) titanium, tert (butylimidotris) (diethylamido) tantalum (tertiary), diethylamido tantalum (TBTDET), pentakis (diethylamido) diethylamido tantalum, bis (ethylcyclopentadienyl) ruthenium, tris (dimethylamido) antimony, and tetramethyltin.

As described above, after the source layer containing boron or metal is deposited, the upper portion thereof is changed to form a passivation layer (e.g., a layer containing nitride or oxide), the bottom portion of which is unchanged, As shown in Fig. In many embodiments where the source layer is deposited to a greater thickness over the metal than over the insulating layer, the portion of the source layer that is present on the insulating layer due to this change process is a material with low conductivity (e.g., BN _x , Al _x O _y Etc.). ≪ / RTI > This change is done to prevent shorts between adjacent interconnects. Moreover, the partial change in the source layer present on the metal wiring serves to adjust the amount of dopant present in the layer, and provides a passage through which the interconnect resistance can be controlled by adjusting the thickness of the protective cap.

A number of processes may be used to form the passivation layer. In one embodiment, the source layer is changed by exposing the substrate to the nitrogen-containing reactant in the plasma discharge. For example, NH ₃ , N ₂ H ₄ , amines, N ₂ , and mixtures thereof may be used. In a specific example, the substrate is exposed to N ₂ And BH _x is brought into contact with a mixture of NH ₃ The source layer can be changed to form a passivation layer containing BN _x . In another embodiment, the source layer (e.g., the metal-containing source layer) is changed by exposing the substrate to an oxygen-containing compound (e.g., O ₂ , N ₂ O, or CO ₂ ) , Aluminum oxide, titanium oxide, etc.) can be formed. In other embodiments, the source layer may be varied using carbon containing reactants in the plasma to form a passivation layer containing carbides or hydrocarbons (e.g., BC _x , C _x H _y, etc.).

The thickness of the layer to be changed can be customized as desired. By adjusting the thickness of the layer to be changed, the thickness of the remaining unaltered layer containing the dopant source is adjusted, which results in the thickness of the protective cap in the interconnect being adjusted. For example, between about 20 and 60% of the thickness of the source layer present on the metal lines to form the passivation layer may be varied, and the unchanged dopant-containing portions remain in contact with the metal lines. In one example, the source layer present on the metal lines has a thickness between about 50 and 500 ANGSTROM. After about 20 to 60% of the thickness of the source layer thickness has been converted to the passivation layer, a thickness of between about 20 and 400 A remains in contact with the metallization.

Then, after the modified layer is formed, the active component from the unaltered source layer can diffuse into the interconnect metal or react with the interconnect metal and form a protective cap in the layer of interconnect metal. In some embodiments, before forming the protective cap, the active ingredient is first generated in the source layer. Depending on the nature of the active ingredient, various conditions can be used to produce the active ingredient and promote the active ingredient to diffuse into the interconnect metal. In some embodiments, the substrate may be exposed to high temperatures for a predetermined period of time to facilitate formation of a protective cap within the metal interconnect. In other embodiments, the formation of the protective cap occurs at room temperature after sufficient time has been allowed for dopant diffusion.

In some embodiments, after a passivation layer is formed, an etch stop layer or an insulating film diffusion barrier layer (e.g., a layer comprising doped or undoped silicon carbide or silicon nitride) is deposited over the passivation layer. In other embodiments, the passivation layer itself may serve as an etch stop layer or an insulating film diffusion barrier layer, and no separate etch stop layer is required. In the latter embodiment, an intermetal dielectric is deposited directly on the passivation layer.

In some embodiments, doping of the interconnect metal is performed by allowing the dopant to diffuse into the interconnect metal or react with the interconnect metal after the insulating film diffusion barrier layer or etch stop layer is deposited. For example, after the etch stop layer (e.g., silicon carbide layer) has been deposited, the substrate may be heated to at least about 100 DEG C to facilitate formation of the protective cap.

Advantageously, in some embodiments, the entire cap-forming process and the diffusion barrier (or etch stop) deposition process are performed sequentially in a module without vacuum release. A PECVD module device having multiple stations in one chamber or having multiple chambers is a suitable device for such deposition. Notably, both the metal-containing layer and the insulating layer can be continuously deposited in one PECVD apparatus without releasing the vacuum state. For example, in one embodiment, this process includes depositing a metal-containing source layer, converting the top portion of the source layer to a passivation layer, allowing the active component to form a protective cap within the metal interconnect, A diffusion barrier layer, or an etch stop layer, wherein all processes are performed in a single apparatus without vacuum release.

A device formed using this method can have improved electron mobility and also exhibit greater adhesion to the metal / insulating film diffusion interface.

According to still another aspect of the present invention, there is provided a semiconductor device. The semiconductor device includes a region of an insulating material and a region of copper or a copper alloy embedded in the insulating material. Such a semiconductor device further comprises a layer comprising BN _x deposited over a layer of insulating film and over a region of copper or copper alloy. The semiconductor device further comprises a boron-containing cap within the copper or copper alloy region.

In accordance with another aspect of the present invention, there is provided an apparatus for forming a protective cap on or in a metal portion of a partially fabricated semiconductor device. The apparatus comprises: (a) a process chamber having an inlet for injection of reactants; (b) a wafer support for securing the wafer in position during formation of the protective cap; And (c) a controller including program instructions for depositing a protective cap. The instructions comprising: (i) depositing a source layer comprising boron or a second metal over the exposed metal portion and the exposed portion of the insulating film on the wafer substrate; (Ii) changing an upper portion of the active component layer to form a passivation layer; And (iii) instructions for the active ingredient in the source layer to diffuse into the metal on the substrate or react with the metal to form a protective cap. In some embodiments, the apparatus is a PECVD apparatus. These processes can be performed continuously in one station of the multi-station device. In other embodiments, some processes may be performed at a first station of the device, and other processes may be performed at a different station. One station may be configured for processes performed at a first temperature and another station may be configured for processes performed at a different temperature. For example, deposition of a source layer may be performed at one station of the multi-station at a first temperature, and subsequent changes of the source layer may be performed at another temperature at another station. The substrate can be transported between stations without vacuum release. In other embodiments, the process can be similarly implemented in a multi-chamber device in which the substrate can be transported between chambers without exposing the substrate to ambient conditions.

In another aspect of the present invention, a method of forming an aluminum-containing protective cap on an oxide-free copper surface is provided. The method comprises the steps of: (a) providing a substrate having an exposed layer of an oxide-free copper or copper alloy and an exposed layer of an insulating film so as to form a first layer comprising aluminum on top of both the insulating film and the copper or copper alloy layer, ; (b) chemically changing a portion or all of the first layer to form a passivation layer comprising aluminum; And (c) depositing an insulating layer over the passivation layer. In some embodiments, each of steps (a), (b), and (c) are performed in a chemical vapor deposition (CVD) apparatus. Moreover, in certain embodiments, the insulating layer deposited in (c) is an etch-stop insulating layer. This etch stop insulating layer may be a doped or undoped material such as, for example, silicon nitride or silicon carbide. In another embodiment, the insulating layer deposited in (c) is an interlayer dielectric (ILD) layer deposited directly over the passivation layer.

In a particular embodiment, the method comprises an additional step before step (a). Specifically, the substrate surface is cleaned to completely remove the copper oxide from the surface of the copper or copper alloy. Examples of cleaning techniques include N ₂ , NH _3, and H ₂ (1) direct plasma treatment, (2) remote plasma treatment, (3) UV treatment, and (4) heat treatment.

In the above-described embodiment, step (a) may involve contacting the substrate with an organoaluminum compound at a substrate temperature of at least about 350 캜 (e.g., at least about 400 캜) in the absence of plasma. By way of example, the organoaluminum compound is trimethylaluminum.

In certain embodiments, step (b) involves substantially completely passivating the first layer present on the copper or copper alloy without allowing aluminum to diffuse substantially into the copper layer. Alternatively, step (b) involves partially passivating the first layer present on the copper or copper alloy while allowing aluminum to diffuse partially into the copper layer.

In certain embodiments, passivating the layer in (b) comprises forming a substantially immobile compound comprising an Al-N bond. In a specific embodiment, the passivation process involves treating the substrate with a nitrogen-containing agent, which may be, for example, direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. In a more specific embodiment, the treatment involves exposing the substrate to a nitrogen-containing formulation in the absence of plasma. The latter treatment may be appropriate when, for example, the insulating film is an ULK insulating film.

In another embodiment, the step of passivating the layer in (b) comprises forming a substantially free-flowing compound comprising an Al-O bond. Such a process may involve treating the substrate with an oxygen-containing agent, which may be, for example, one of direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. In a specific embodiment, the treatment entails contacting the substrate with an oxygen-containing agent in the absence of plasma. This processing is, for example, an insulating film may be suitable when the oxygen ULK dielectric film - are examples of formulations containing contains _{O 2, N 2 O, CO} 2, and O _3.

Yet another aspect of the present invention relates to an apparatus for forming a semiconductor device structure comprising: (a) a process chamber having an inlet for the injection of a metal-containing reactant or a volatile metal-containing reactant in gaseous form; (b) a wafer support for securing the wafer in place during deposition of the metal-containing layer on the wafer substrate in the process chamber; And (c) a controller including program instructions. The program instructions comprising the steps of: (i) depositing a first layer by contacting a substrate having an exposed layer of copper or copper alloy free of oxide and an exposed layer of an insulating film with an aluminum-containing reactant; And (ii) chemically changing part or all of the first layer to form a passivation layer comprising aluminum.

The above and other features and advantages of the present invention will be described in more detail with reference to the accompanying drawings.

1A-1E are cross-sectional views of device structures formed during a copper dual damascene fabrication process.
2A to 2C are cross-sectional views of a partially fabricated device structure showing a protective cap.
Figure 3a shows an exemplary process flow diagram of a cap-forming process in accordance with some embodiments.
Figure 3B shows another exemplary process flow diagram of a cap-forming process in accordance with some embodiments.
Figures 4A-4E are cross-sectional views of device structures produced during formation of the capping layer, in accordance with some embodiments.
5 is a graphical representation of a PECVD apparatus that may utilize a low frequency (LF) and radio frequency (HF) radio frequency plasma source that may be used to form a capping layer in accordance with some embodiments of the present invention.
Figure 6 is a graphical representation of an example of a multi-station device suitable for forming a capping layer in accordance with some embodiments of the present invention.
Figure 7 is a schematic representation of another example of a multi-station suitable for forming a capping layer in accordance with some embodiments of the present invention.

summary

As device dimensions continue to decrease and current density experienced by interconnects increases, electron mobility in IC fabrication has become a significant reliability issue. Electron transport is itself evident in the movement of metal atoms with current and in the formation of voids in interconnects. The formation of cavities can result in device failure. The migration of metal atoms is particularly pronounced at the metal / diffusion barrier interface and along the grain boundary. Currently, at 90 nm and 45 nm technology nodes, a method is needed to improve the electron mobility performance. Although electron transport performance can be improved by implanting the dopant element into the interconnect, such a dopant has typically higher resistance than an interconnect metal (e.g., Cu) and can significantly increase the interconnect resistance. Thus, doping of the unregulated interconnect metal can result in interconnects having unacceptably high resistance.

Methods for introducing an adjustable dopant are provided herein. The method involves forming a protective cap in a metal interconnect by implanting a controlled amount of dopant into the interconnect. As a result, a very thin protective cap can typically be formed in the upper portion of the metal wiring at the interface between the metal and the insulating film diffusion barrier (or etch stop) layer. Such a protective cap preferably (but not necessarily) comprises a solid solution, an alloy, or a compound of interconnect metal with a dopant. For example, copper may be doped with B, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, or Sb. These dopants can also be used together with one another or with other elements. In general, various dopants can be used. Dopants capable of forming compounds with solid solutions, alloys, and interconnect metals, and dopants that can accumulate at the metal / diffusion barrier interface and at crystal boundaries in the interconnect are particularly preferred.

Although the protective cap described herein and the method of forming such a protective cap are beneficial in improving the electron mobility of the interconnect, the use of the described devices and processes is not limited to this particular application. For example, the protective cap may serve to improve the adhesion between the metal wiring and the insulating film diffusion barrier layer or etch stop layer, and may also prevent oxidation of the interconnect metal during IC device fabrication.

The formation of a protective cap in the interconnect will be illustrated in the context of a copper dual damascene process. It is understood that the methods disclosed herein may also be used in other processes including single damascene processes and may also be applied to various interconnect metals other than copper. For example, the present invention is also applicable to aluminum, gold, and silver-containing interconnects.

1A to 1D show a cross-sectional view of a device structure formed on a semiconductor substrate at various stages of a dual damascene fabrication process. A cross-sectional view of the completed structure formed by the dual damascene process is shown in Fig. The "semiconductor substrate" used in this application is not limited to the semiconductor portion of the IC element but is broadly defined as a semiconductor-containing substrate. Referring to FIG. 1A, an example of a partially fabricated IC structure 100 used in dual damascene fabrication is shown. The structure 100, such as that shown in FIGS. 1A-1D, is a portion of a semiconductor substrate and, in some embodiments, may be directly on a layer containing active elements such as transistors. In another alternative embodiment, the structure 100 may be directly on a metallization layer or other layers comprising a conductive material (e.g., a layer containing a memory capacitor).

Layer 103 shown in FIG. 1A is a layer of an intermetallic dielectric that may be silicon dioxide, more typically a low-k insulating material. In order to minimize the dielectric constant of the intermetal dielectric stack, a material having a k value of less than about 3.5, preferably less than about 3.0, and often less than about 2.8 is used as the interlayer dielectric. Such materials include, but are not limited to, fluorine or carbon-doped silicon dioxide, low-k materials containing organics, and doped porous silicon dioxide, as known to those skilled in the art. Such materials can be deposited, for example, by PECVD or by a spin-on process. (Trenches and vias) are deposited in the layer 103 and a partially conductive metal diffusion barrier 105 is deposited on this wiring path and subsequently the copper conductive root 107 is inlaid. Copper or other mobility (mobile) conductive material is to provide a conductive path of a semiconductor substrate, a silicon element, and an insulating layer lying under the metal wiring, and the metal wiring metal ions (e.g., Cu ^{2 +)} should be protected from , The metal ions may be diffused or drifted into silicon or an interlayer insulating film if there is no conductive path, resulting in deterioration of properties of silicon or an interlayer insulating film. Several types of metal diffusion barriers are used to protect the insulating layer of the IC device. These types may be subdivided into a partially conductive metal-containing layer (e.g., 105) and an insulating barrier barrier layer, which will be described in more detail with respect to FIG. 1B. Suitable materials for the partially conductive diffusion barrier 105 include materials such as tantalum, tantalum nitride, titanium, and titanium nitride. These materials are typically deposited by PVD or ALD methods on insulating layers with vias and trenches.

The copper conductive roots 107 can be formed through a number of techniques including PVD, electroplating, electroless deposition, CVD, and the like. In some embodiments, a preferred method of forming a copper fill comprises depositing a seed layer of thin copper by PVD, followed by depositing a bulk copper fill by electrolytic plating. Since copper is typically deposited to have excess portions present in the field portion, chemical mechanical polishing (CMP) is needed to remove the excess to obtain a planarized structure 100.

Referring now to FIG. 1B, after the structure 100 is completed, the surface of the substrate 100 may be pre-cleaned to remove contaminants and metal oxides. After pre-cleaning, a dopant source layer containing the active component (dopant-generating component containing boron or metal) is deposited on both the copper wiring 107 and the insulating film 103. Then, the source layer is changed to a passivation layer, for example, by a nitridation reaction or an oxidation reaction of the source layer. For example, the passivation layer may comprise BN _x , BO _x , AlO _x , TiO _x And the like. The source layer can be completely changed to the non-conductive passivation layer over the regions of the insulating film to prevent shorting between adjacent metal wirings 107. The portion of the source layer directly overlying the copper wiring 107 is only partially changed to the passivation layer, whereby the portion of the unchanged source layer remains in contact with the copper. After the dopant from the portion of the un-passivated source layer is diffused or reacted with copper, a protective cap 108 is formed in the upper portion of the metal line 107. By adjusting the amount of material deposited on the source layer, by adjusting the degree of change during partial passivation of the source layer, and by adjusting the conditions used during dopant and copper diffusion and / or reaction, the thickness of the protective cap is adjusted . The protective cap may comprise, for example, an alloy or solid solution of B, Al, Ti, etc., and copper. In some embodiments, the amount of dopant in the alloy or solid solution is controlled by adjusting the temperature and time used to promote the diffusion of the dopant from the source layer. The composition of the protective cap and the composition of the passivation layer will be described in detail in the following sections.

In some embodiments, the passivation layer also serves as a diffusion barrier layer. In another alternative embodiment, a separate diffusion barrier (or etch stop) layer is deposited on top of the passivation layer. Typically, such a diffusion barrier layer comprises doped or undoped silicon carbide or silicon nitride.

1B, the film 109 may comprise a single passivation layer (e.g., a BN _x or AlO _x layer), or may include a passivation layer adjacent to the copper wiring 107 and a top layer overlying the passivation layer Or a bi-layer composed of an insulating film diffusion barrier layer (e.g., a doped silicon carbide layer). All of these embodiments will be described in detail in the following sections with reference to Figures 2A-2C. The film 109 may be referred to as a Cu / insulating film interface film, or simply referred to as an "interfacial film ".

In embodiments where the interfacial film comprises a separate insulating film diffusion barrier layer, the insulating film diffusion barrier layer is typically deposited on top of the passivation layer by PECVD. In one embodiment, deposition of a passivation layer, formation of a protective cap 108, and deposition of an insulating film diffusion barrier layer are performed in one PECVD device without dissolving the vacuum state. The interface film 109 may also serve as an etch stop during the subsequent damascene process.

Referring again to FIG. 1B, a first insulating layer 111 of a dual damascene insulator structure is deposited over the film 109. Following this deposition, an etch stop film 113 is deposited over the first dielectric layer 111, optionally by PECVD. The insulating layer 111 is typically comprised of a low-k insulating material such as those listed for the insulating layer 103. The layers 111 and 103 do not necessarily have to have the same composition.

Followed by a process in which a first insulating layer 1115 of a dual damascene insulating film structure is deposited on the etch-stop film 113 in a manner similar to the first insulating layer 111, as shown in Fig. 1C. Followed by deposition of an anti-reflection layer (not shown) and a CMP blocking film 117. The second insulating layer 115 typically contains a low-k insulating material as described above for layers 103 and 111. The CMP blocking film 117 serves to protect the soft insulating material of the intermetal dielectric layer (IMD) layer 115 during a subsequent CMP process. Typically, the CMP blocking layer is subject to integration repuirement similar to diffusion barrier and etch stop films 109 and 113, and may include materials based on silicon carbide or silicon nitride.

As shown in FIGS. 1D and 1E, the dual damascene process continues with the etching of the via 119 and the trenches 121 in the first and second insulating layers. The pattern shown in FIG. 1D can be etched using standard lithographic techniques. A trench-first or via-first method, well known to those skilled in the art, may be used.

1E, the newly formed vias and trenches are coated with a metal diffusion barrier 123 as described above, and the metal diffusion barrier is formed by depositing tantalum, tantalum nitride, titanium nitride, Lt; RTI ID = 0.0 > and / or < / RTI >

After the diffusion barrier 123 has been deposited, a seed layer of copper is applied (typically by a PVD process) so that the feature can be electrofilled with a copper inlay. In a CMP process in which the copper layer is deposited, for example, by electro-charging and is performed to inhibit CMP in the CMP blocking film 117, an excess of the deposited metal in the field is removed. Fig. 1e shows a completed dual damascene process where copper conductive roots 124 and 125 are inlaid in vias and trenches over barrier 123 (seed layer not shown). Figure 1e shows three interconnects in which the copper wiring is doped in an adjustable manner.

If additional processing is required, an interface film similar to the film 109 and a protective cap similar to the cap 108 is formed on top of the structure shown in Fig. 2e, followed by a new metallization layer.

The structure and composition of the protective cap 108 and the interface layer 109 will be described in detail with reference to Figures 2A-2C.

Device structure

Referring to Figure 2a, an exemplary cross-sectional view of a partial IC structure is shown. In these devices, vias and trenches formed in the interlayer insulating film 201 are lined with diffusion barrier material 203 and filled with copper or copper alloy 205. The upper portion of the copper wiring 205 includes a thin protective cap 207 present at the interface between the copper wiring 205 and the passivation layer 209. A passivation layer 209 is present on both the ILD layer 201 and the protective cap 207 and is in contact with both of these layers. An insulating film diffusion barrier or etch stop layer 211 is present on top of the passivation layer 211. Although not shown for the sake of clarity, another ILD layer is present on top of the insulating film diffusion barrier or etch stop layer 211. The passivation layer 209 and the diffusion barrier (or etch stop) layer 211 together form an interfacial film (such as the interfacial film as shown by layer 109 in relation to Figure IB) present at the metal / ILD boundary .

In one embodiment, the interlayer dielectric layer 201 has a thickness of about 1,000 to 10,000 ANGSTROM. Layer 210 may comprise a variety of ILD materials such as low-k and ultra low-k insulating films known to those skilled in the art. For example, carbon-doped silicon oxide or an organic insulating material having a k less than about 2.8 may be used. The copper wire 205 may have a thickness of about 500 to 10,000 ANGSTROM and preferably about 10% or less, more preferably about 2% or less of the thickness, as measured by the layer thickness, Respectively. In many embodiments, it is understood that the protective cap will have a stepped composition and will have the largest dopant concentration at the passivation layer interface. The acceptable thickness of the protective cap will depend on the resistivity of the dopant. Generally, according to the above-described method, a protective cap is formed such that the resistive shift of the via is less than or equal to about 10%, preferably less than or equal to about 5%, and more preferably less than or equal to about 3%. This resistive shift is measured as the difference in resistance of the capless interconnect versus the resistance of the capped interconnect. In some embodiments, an acceptable resistive shift is obtained by forming the protective cap to have a thickness that does not exceed 500 ANGSTROM, preferably a thickness that does not exceed 100 ANGSTROM.

It is understood that different dopants can diffuse differently in the copper interconnect and can affect the interconnect resistance to different degrees. Accordingly, the numerical values provided above serve only as an illustration and are not intended to limit the structure of the present invention to the thickness parameters mentioned. For example, a particular dopant can be diffused into the copper interconnect, deposited over the entire copper interconnect without forming a separate cap, or deposited at the crystal boundary and / or at other interfaces (e.g., (At the interface between the copper layer 203 and the copper layer 205). Advantageously, the provided invention allows this dopant to be injected in a controlled amount, so that in this case the interconnect resistance can be adjusted even if the layer thickness can not be precisely defined.

A number of doping elements may be used in the protective cap. Dopants that form compounds with solid solution, alloys, or copper, and dopants that can accumulate at the interface of the copper crystal boundary and copper and other layers are prioritized. Materials with relatively low resistance (e.g., metals) are often preferred. Moreover, materials that are not easily diffused into copper at low temperatures (e.g., at temperatures below about 100 DEG C) are often preferred. Examples of suitable dopants include but are not limited to B, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, and Sb. In general, it is preferred that the selected dopant has a volatile precursor so that deposition can be performed by CVD. Thus, volatile hydrides, carbonyls, halides, and metal dopants with organometallic precursors are typically preferred. Compounds that can be injected into the gas phase at temperatures up to 450 ° C and precursors of at least about 1 Torr are suitable precursors.

In a specific embodiment, the protective cap 207 comprises copper and boron, or copper and aluminum, or copper and titanium. In some embodiments, the dopants are used together. For example, the protective cap 207 may comprise a combination of copper, aluminum, and titanium, or copper and dopants. In some embodiments, the dopants described above may be doped with a material (such as CuSi _x , CuGe _x , SiN _x , and SiC _x ) used to form a self-aligned buffer (PSAB) Used together. U.S. Patent Application No. 11 / 726,363 entitled " Protective Self-aligned Buffer Layers for Damascene Interconnects ", Chattopadhyay et al., Filed March 20, 2007, U.S. Patent Application No. 11 / 709,293, entitled " Protective Self-aligned Buffer Layers for Damascene Interconnects " filed on February 20, 2007, and van Schravendijk, are inventors and filed on November 3, 2004 U.S. Patent Application No. 10 / 980,076, entitled " Protection of Cu Damascene Interconnects by Formation of a Self-aligned Buffer Layer ", which is incorporated herein by reference.

In one embodiment, the passivation layer 209 on top of both the ILD layer 201 and the protection cap 207 has a thickness of between about 50 and 500 ANGSTROM. The passivation layer typically contains a non-conductive material that prevents shorting between adjacent interconnects. The passivation layer typically contains a modified dopant, which may contain, for example, a nitride, oxide, carbide, sulfide, selenide, phosphide, or bicomponent of a dopant (boron or metal). Moreover, the passivation layer may contain hydrocarbons (C _x H). In one embodiment, the passivation layer contains BN _x . In some embodiments, in other alternative embodiments, the BN _x layer may also comprise hydrogen. In another example, the passivation layer contains metal oxides such as AlO _x , HfO _x , TiO _x , CoO _x , TaO _x , MoO _x , RuO _x , SnO _x , and SbO _x .

As shown in FIG. 2A, an insulating film diffusion barrier or etch stop layer 211 is present on top of the passivation layer. In one embodiment, layer 211 has a thickness between about 50 and 500 ANGSTROM. Traditionally, silicon nitride and nitrogen-doped silicon carbide (NDC) have been used in these applications. At present, materials with lower dielectric constants than silicon nitride are often used as insulating film diffusion barriers. Such materials include carbon-rich silicon carbides such as those described in U.S. Patent Application No. 10 / 869,474, to Yu et al., Filed on June 15, 2004 and co-owned; U.S. Patent Application No. 10 / 915,117, filed on August 9, 2004, and Yu et al., Inventors, and U.S. Patent Application No. 11 / 373,847, filed March 8, 2006, - doped silicon carbide; And Tang et al., Inventors and oxygen-doped silicon carbide as described in U.S. Patent No. 6,855,645, issued February 15, 2005. All such United States patent applications and US patents are incorporated herein by reference. In some embodiments, layer 211 may be formed of several sub-layers (e. G., A sub-layer containing doped or undoped silicon carbide, having different compositions tailored for improved diffusion barrier and etch stop properties) Lt; / RTI > For example, the barrier may comprise a sub-layer of undoped carbide, a sub-layer of nitrogen-doped carbide, and any combination of sub-layers of oxygen-doped carbide. The barrier may have two sub-layers, three sub-layers, or more sub-layers. An example of a combination barrier layer is shown in U.S. Patent Application No. 10 / 869,474, filed on October 16, 2007, now U.S. Patent No. 7,282,438, filed June 15, 2004, Incorporated herein by reference. For example, the insulating film diffusion barrier layer may comprise doped or undoped silicon carbide, silicon nitride, or silicon carbonitride.

In the embodiment shown in FIG. 2A, layers 209 and 211 together form an interfacial layer present between two ILD layers (the top ILD layer is not shown).

In certain embodiments, the passivation layer 209 may serve as a diffusion barrier or an etch stop layer without the need for a separate silicon carbide or silicon nitride layer 211. In this embodiment shown in Figure 2B, the interfacial layer present between the two ILD layers consists solely of the passivation layer 209. For example, certain metal oxides and metal nitrides can act as etch stop layers or diffusion barrier layers.

Figure 2c shows an embodiment in which a layer of dopant or dopant-generating compound 208 is present between the protective cap 207 and the passivation layer 209 and is in contact with these two layers. The layer 208 is aligned on the copper wiring 205 and does not extend over the layer of the insulating film 201. [ Layer 208 may comprise a pure dopant or dopant-generating compound. For example, layer 208 may include BH _x , Al, Ti, Ta, Hf, Ru, and the like. The metal in this layer may not have other elements such as H, C, N, etc., and may be combined with other such elements. In some embodiments, copper may diffuse upward toward layer 208 to form an alloy, a mixture, or a solid solution with a dopant in layer 208. In this embodiment, the bilayer 207/208 will serve as a protective cap. In general, the protective cap as described herein may be entirely in the copper line at the same level as the peripheral insulating film 210, or may include a portion that exists above the height of the peripheral insulating film 201 .

In one specific example, the device has a structure as shown in Fig. 2A, with a boron-doped protective cap 207 and a passivation layer 209 containing BN _x . The copper wiring 205 is present in a layer of an ULK insulating film (k of about 2.5) having a thickness of about 3,500 angstroms. The protective cap 207 includes copper and boron, and has a thickness of about 100 angstroms. The protective cap is present at the top of the copper layer at the interface with the passivation layer. The passivation layer has a thickness of about 150 A and includes BN _x . The passivation layer may also contain hydrogen and will be mentioned in the experimental part as (BNH) _x layer. The layer of diffusion barrier 211 may comprise nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or undoped silicon carbide. The layer 211 has a thickness of 100 ANGSTROM to 500 ANGSTROM.

In another specific example, the device has a structure as shown in Fig. 2A and has a titanium protective cap 207 and a passivation layer 209 containing TiN _x . The copper wiring 205 is present in the layer of the ULK insulating film (k of about 2.5) having a thickness of about 3,500 ANGSTROM. The protective cap 207 includes copper and titanium and has a thickness of about 100 angstroms. The protective cap is present at the top of the copper wiring at the interface with the passivation layer. The passivation layer has a thickness of about 150 ANGSTROM and contains TiN _x . The passivation layer may also comprise hydrogen. The layer of diffusion barrier 211 may comprise nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or undoped silicon carbide. The layer 211 has a thickness of 100 ANGSTROM to 500 ANGSTROM.

In another specific example, the device has a structure such as that shown in Figure 2A and has an aluminum-doped protective cap 207. The copper wiring 205 is present in the layer of the ULK insulating film (k of about 2.5) having a thickness of about 3,500 angstroms. The protective cap 207 includes copper and aluminum and has a thickness of about 100 angstroms. The protective cap is present at the top of the copper wiring at the interface with the passivation layer. The passivation layer has a thickness of about 100 ANGSTROM or less and consists essentially of AlO _x . A layer 211 of diffusion barrier having a thickness of about 100 A to 500 A is present in contact with AlO _x and may include nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or undoped silicon carbide.

protect Capping  Layer formation method

An exemplary method of forming the protective capping layer is shown in the process flow chart shown in FIG. 3A. A cross-sectional view of the device structure obtained at various stages of the process is shown in Figures 4A-4E. Although the methods described herein may be practiced in many types of devices, in some embodiments, a Plasma Chemical Vapor Deposition (PECVD) device is preferred. In some embodiments, the PECVD apparatus can provide high frequency (HF) and low frequency (LF) plasma generation sources.

Referring to FIG. 3A, as shown in step 301, a process is started by providing a partially fabricated semiconductor element having a pattern of copper wiring to an insulating film. For example, an element such as that shown in Fig. 4A can be used. The device has a layer of copper or copper alloy (405) embedded in a layer of insulating film (401). A thin diffusion barrier material layer (containing, for example, Ta, TaN _x , TiN _x , Ru, and W) is present at the interface between copper and the insulating film. A layer of copper and a layer of insulating film are exposed on the substrate surface.

Optionally, the substrate may be pre-cleaned in step 303 to remove contaminants from the surface of the substrate. For example, the substrate may be pre-cleaned by exposing the substrate to a reducing gas in the plasma (e.g., a gas selected from the group consisting of H ₂ , N ₂ , NH _3, and mixtures thereof in plasma discharge) The oxide can be removed. In some embodiments, pre-cleaning with H ₂ plasma results in particularly improved properties of the devices. The process gas during pre-cleaning may also include carrier gas such as N ₂ , He, Ar. In one embodiment, pre-cleaning is performed in a PECVD chamber at a temperature of about 200 to 400 DEG C, at about 1.5 to 4 Torr, and at a H ₂ flow rate of about 4,000 to 10,000 sccm. Plasma, which may have HF and LF components, is heated to a high degree and a total power of 200 to 1000 W per 300 mm wafer is maintained. In some embodiments, it is desirable to use HF power of 0.1 to 1.5 W / cm ² and LF power of 0 to 0.8 W / cm ² during the pre-clean process. In another example, NH ₃ is used as a reducing gas instead of H ₂ and flows into the process chamber at a flow rate ranging from about 6,000 to 8,000 sccm. N ₂ carrier gas flows into the chamber at a flow rate of about 2,000 to 4,000 sccm. The pre-wash process can last for a few seconds (e.g., between about 6 and 20 seconds).

In some embodiments, it is desirable to perform pre-cleaning using a more milder method than direct plasma exposure. This mild method is particularly advantageous when copper wiring is embedded in a soft ULK insulating film that can be easily damaged by direct plasma exposure.

In some embodiments, H ₂ , N ₂ , NH ₃ And a mixture thereof, a complete removal or partial removal of the copper oxide is carried out by using a remote plasma containing gas. In this embodiment, a plasma can be formed in the chamber using one or more of these gases (e.g., a mixture of H ₂ and N ₂ , or a mixture of NH ₃ and N ₂ ) Lt; RTI ID = 0.0 > a < / RTI > The formed plasma is then directed through the delivery line to the ion filter, which reduces the ion plasma while leaving a radical. The resulting radical rich process gas is delivered to the chamber housing the substrate through an inlet (e.g., showerhead). In some embodiments, the radical-rich process gas (in some embodiments, substantially free of ionic species or substantially free of ionic species) contacts the substrate surface and partially or wholly removes the copper oxide. Because high energy ions in the plasma are directly related to the dielectric breakdown, the use of ion-poor remote plasmas can provide a mild and effective method of pre-cleaning. An example of a suitable remote plasma system can be found in the Gamma ^TM product line provided by Novellus Systems, San Jose, Calif.

In yet another embodiment, H ₂ , N ₂ , NH ₃ And ultraviolet (UV) radiation treatment in the presence of a reducing gas such as a gas selected from the group consisting of a mixture of these gases. In this embodiment, one or more of these gases (e.g., a mixture of H ₂ and N ₂ , or a mixture of NH ₃ and N ₂ ) are in contact with the substrate while UV is being irradiated to the substrate. For example, B. Varadarajan et al., Inventor, filed on November 12, 2009 and co-owned patent application No. 61 / 260,789 entitled UV and Reducing Treatment for K Recovery and Surface Clean in Semiconductor Processing, , Which is incorporated herein by reference for the purpose of providing details of a UV treatment apparatus and method suitable for use in the embodiments described herein. do. The described UV treatment can be used to control the removal of copper oxide where the thickness of the removed oxide can be controlled by the duration of UV exposure, process gas composition, substrate temperature, and other conditions.

In some embodiments, pre-cleaning is achieved by heat treatment in a plasma free environment. For _{example, H 2, N 2, NH} 3, or a wafer to at least about 200 ℃ temperature can be heated in an atmosphere comprising a mixture thereof for about 15 to 60 seconds. This thermal treatment can be used for partial copper oxide removal and is particularly advantageous for substrate processing that contains a soft ULK dielectric.

After pre-cleaning is complete, in 305 a source layer of dopant-containing material is deposited over the substrate surface. Advantageously, the dopant-containing material does not need to be selectively deposited over the metal surface and can be deposited on both the surface of the insulating film and the metal. (E.g., a boron-containing or metal-containing reactant) with a partially fabricated device under conditions that result in the deposition of a dopant-containing (e.g., boron-containing or metal- A source layer is deposited by contact.

In one embodiment, the dopant-containing source layer is thermally deposited without plasma discharge. For example, a volatile precursor such as a volatile hydride, halide, carbonyl, or organometallic compound can be reacted (e.g., decomposed) at a high temperature to deposit a layer of dopant-containing material on the substrate surface. As will be understood by those skilled in the art, temperature ranges, substrate exposure times, and other deposition conditions are adjusted for each particular precursor.

In one embodiment, B ₂ H ₆ can be used as a precursor to form a B-doped protective cap. In one exemplary process, B ₂ H ₆ is injected into the process chamber with one or more additional carrier gases such as N ₂ , O ₂ , CO ₂ , He, NH ₃ , Ar, and the like. In this example, the B ₂ H ₆ concentration is in the range of about 0.5 to 20% and the pressure is in the range of about 0.5 Torr to about 10 Torr. B ₂ H ₆ is contacted with the substrate at a chamber temperature between about 200 and 400 ° C in the absence of a plasma discharge to deposit a boron-containing layer on the substrate. This layer will be referred to as a BH _x layer since it has been determined to have BH bonds. The BH _x layer diffuses into the copper wiring and serves as a B dopant source to form a protective cap.

In another example, a volatile metal-containing precursor is injected into the chamber. Organometallic compounds, metal hydrides, metal halides, and metal carbonyls can serve as suitable precursors. For example, alkyl-substituted metal derivatives and cyclopentadienyl-substituted metal derivatives can be used. These precursors can react at high temperatures to form a metal-containing source layer on the substrate. In some embodiments, similar pressure and temperature ranges as those used in the deposition of the B-containing cap may be used. Generally, depending on the nature of the precursor, the deposition conditions are optimized to deposit the metal-containing source layer with optimal quality. For example, the temperature range can be optimized to suit the particular decomposition process for the precursor, and thus the composition of the metal-containing source layer can be adjusted as desired. Those in the field will understand how to optimize deposition conditions and how to obtain metal-containing source layers using optimized compositions.

As noted, a variety of metals can serve as dopants. For example, exemplary copper interconnects may be doped with Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, and Sb. Other metals well known for volatile precursors may be used. Examples of suitable precursors for aluminum-containing source layer deposition include, but are not limited to, trimethyl aluminum, dimethyl aluminum hydride, triethyl aluminum, triisobutyl aluminum, and tris (diethylamino) aluminum. Examples of precursors that can be used for the deposition of source layers containing other metals include bis (cyclopentadienyl) cobalt, cobalt (II) acetylacetonate, tetrakis (dimethylamido) hafnium dimethylamido hafnium), tetrakis (diethylamido) hafnium, tetrakis (dimethylamido) molybdenum, tetrakis (dimethylamino) titanium (TDMAT), tetra (Diethylamino) titanium (TDEAT), tetrakis (ethylmethylamido) titanium, bis (diethylamino) bis (diisopropylamino) titanium, pentakis (Butylimidotris) (diethylamido) tantalum (TBTDET), pentakis (diethylamido) tantalum, bis (ethylcyclopenta) Dienyl) ruthenium, tris (dimethyl Not shown) it is not antimony (tris (dimethylamido) antimony), and tetramethyl tin (tetramethyltin) include, but are limited thereto.

The source layer does not necessarily contain a dopant consisting of a pure element but may include a dopant compound with other elements (for example, H, C, N, etc.). However, a dopant can easily be generated from this layer, and once formed, the dopant can diffuse into copper or react with copper. However, in other embodiments, the source layer may contain a substantially pure metal or boron.

The source layer need not be selectively deposited only on the top of the copper wiring, but may be deposited on both the top of the insulating layer and the top of the copper. However, in many embodiments, a certain degree of selectivity between the copper and the insulating film is achieved and the source layer 408 (which may be a BH _x layer or a metal-containing layer) is deposited over the copper wiring 408, As shown in Fig. 4B with a larger thickness above, a thicker source layer is formed over the copper wiring. Depending on the particular precursor and deposition conditions, a wide range of selectivity can be achieved, ranging from the process in which the source layer is completely selectively deposited on copper interconnects to the completely non-selective process in which the source layer is deposited to the same thickness on both copper and insulator films Can be achieved. Although the methods described herein can be used for the controllable implantation of dopants from selectively and non-selectively deposited source layers, the methods are described herein using layers deposited with partial selectivity as an example. Partial selectivity characterized by a thicker source layer thickness deposited over copper interconnects as compared to the thickness of the source layer deposited over the insulating layer can be observed in boron-containing and many metal-containing source layers. In some embodiments, the thickness of the source layer overlying the copper is about 10-500% greater than the thickness of the source layer overlying the insulating film.

Referring again to the process flow diagram shown in Figure 3A, after the source layer is formed in process 305, in the subsequent process 307, the upper portion of the source layer overlying the copper is changed to form the passivation layer, A portion of the source layer that is not in contact remains in contact with the layer of copper. This is illustrated by the structure shown in Figure 4c where only a small portion of the source layer 408 remains unchanged and is in contact with the copper wiring 405 and the upper portion of the source layer overlying the copper is changed, Layer 409 is formed. The portion of the source layer present on the insulating film is completely changed to the passivation material. The passivation process 309 has two purposes. First, it helps to adjust the interconnect resistance because the partial passivation of the source layer limits the amount of available dopant. Preferably, the passivation layer contains a material that may not readily diffuse from the passivation material into the copper interconnect. For example, boron is changed to boron nitride and aluminum is changed to aluminum oxide. Although the liberated boron and aluminum can diffuse into the copper wiring, when it is converted to nitride and oxide, this material is trapped in the passivation layer and can not be injected into the copper wiring to increase the resistance of the copper wiring. Since the upper portion of the source layer is changed to the passivation layer, the amount of dopant injected into the copper wiring is determined by the thickness of the unchanged portion of the source layer remaining in contact with the copper wiring. Depending on the amount of dopant that needs to be implanted into the interconnects, more or less of the source layer can be converted into the passivation layer. For example, the thickness of the initially deposited source layer may range between about 50 and 500 ANGSTROM, and about 20 to 60 percent of this thickness may be changed to a passivation layer.

Passivation is also required in embodiments where the source layer contains a conductive material deposited over both copper and the insulating film. In such an embodiment, the passivation can prevent shorting between adjacent copper interconnects by changing the conductive material (e.g., metal) to a material that is substantially non-conductive or non-conductive. For example, the partially conductive BH _x The source layer may be completely changed over the insulating layer to a passivation layer containing BN _x which is essentially non-conductive. Similarly, the source layer containing aluminum may be changed to aluminum oxide which is non-conductive.

Many compounds such as nitrides, oxides, sulfides, selenides, tellurides, phosphides, and carbides are materials suitable for the passivation layer. Of course, nitrides and oxides are preferred in many embodiments.

The passivation layer can be formed by contacting the dopant-containing source layer with a suitable reagent, which can change the source layer material to a passivation material. In some embodiments in which a change can be performed thermally (without using a plasma), it is often preferable to change the source layer in the plasma discharge. For example, a nitridation reaction can be achieved by contacting the substrate with a nitrogen-containing reagent (e.g., N ₂ , NH ₃ , N ₂ H ₄ , amine, etc.) in a plasma. Similarly, an oxide can be formed by contacting an oxygen-containing reactant (e.g., O ₂ , CO ₂ , N ₂ O, etc.) in the plasma. Similarly, sulfides, selenides, tellurides, phosphides, and carbides (e.g., H ₂ S, H ₂ Se, H ₂ Te, PH ₃ , C _x H _y Respectively) can be formed.

In some embodiments, post-treatment involves direct plasma treatment. For example, if the substrate with the exposed source layer is H ₂ , N ₂ , NH ₃ And mixtures thereof. ≪ / RTI > In some embodiments, a substrate having a source layer is treated with H ₂ in the plasma. Hydrogen plasma treatment can serve to remove residual organic groups from the precursor layer and can form terminal metal-H bonds. In another example, when the substrate is exposed to H ₂ And N ₂ , or post-treated with NH ₃ in the plasma, whereby the organic groups are removed and metal-N bonds are formed. Other nitriding agents (e.g., N ₂ H and amines) may be used in some embodiments.

Even when pre-processing is used, it is sometimes preferable to use a milder processing method than direct plasma processing. For example, in some embodiments, H ₂ , N ₂ , NH ₃ And mixtures thereof. The substrate may be processed using a remote plasma formed from a gas selected from the group consisting of, for example, < RTI ID = 0.0 > As previously described, a remote plasma is created in a chamber that is physically separate from the chamber housing the substrate, and the ion species is removed before such remote plasma is delivered to the substrate, thereby reducing the likelihood of damage to the insulation layer. This is because the radicals contained in the far-field plasma usually damage less than the high-energy ions. Removal of organic groups from the layers as well as metal-H and metal-N formation can be achieved by remote plasma.

Moreover, using the method described in the previously referenced U.S. Provisional Patent Application No. 61 / 260,789, H ₂ , N ₂ , NH ₃ And a mixture thereof, may be carried out by mild post-treatment by UV irradiation. This UV treatment can be used to form metal-H and metal-N bonds and to remove organic substituents from the precursor layer.

In some embodiments, post-treatment is accomplished by heat treatment in a plasma free environment. For example, the wafer can be heated to a temperature of about 300 to 350 DEG C in an atmosphere containing H ₂ , N ₂ , NH ₃ , or a mixture thereof. This heat treatment is particularly advantageous for processing substrates containing a weak ULK insulating film.

In some embodiments, post-processing is performed by treating the source layer with the reactants at room temperature or elevated temperature in a plasma free environment. For example, in some embodiments, a passivation layer having metal-oxygen bonds is formed by treating the substrate with an oxygen-containing reactant (e.g., O ₂ , H ₂ O, N ₂ O) in a plasma free environment.

Remote plasma post-treatment, thermal post-treatment, and UV post-treatment are particularly advantageous when ULK insulating films, particularly easily damaged porous and organic insulating films, are used in the ILD layer.

Post-nitridation is preferred in many embodiments, although other types of post-treatment may also be used in some embodiments.

For example, a substrate having a precursor layer exposed to an oxygen-containing gas (e.g., O ₂ , CO ₂ , N ₂ O, etc.) is contacted with the plasma or not in contact with the plasma to form a metal- Post-processing may be implemented. In another alternative embodiment, the metal-C bond is formed in the post-treatment step, for example, by treating the source layer with hydrocarbons in the plasma. The metal -S, the metal-Se (H ₂ S, H ₂ Se, H ₂ Te, PH ₃ ), in the presence of the plasma or without the plasma, , Metal-Te, and Metal-P bonds may be formed. Both direct plasma and remote plasma can be used for this type of post-treatment.

Referring again to FIG. 4C, (for example, BN _x , AlO _x , TiO _x A passivation layer is present on the insulating layer 401 and the copper layer 405. [ A thin layer 408 containing an undoped dopant source is present between the copper wiring and the passivation material layer.

After the passivation layer is formed, in step 309, the active component (dopant) from the unchanged source layer can diffuse into copper or react with copper and form a protective cap within the copper layer. This is illustrated by the arrows in the structure shown in Fig. 4c. The resulting structure is shown in Figure 4d, wherein a protective cap 407 is formed in the top of the spurious interconnect. In this example, the dopant from the source layer 408 has migrated to the copper wiring intact. In other embodiments, a portion of the dopant may remain in the source layer. In another alternative embodiment, the copper may diffuse into the unchanged source layer while the dopant may diffuse into the copper wiring. In the latter two cases, a protective cap may be present in the copper wiring initially provided (as shown in Figure 2C) and on the copper wiring.

The formation of the protective cap can occur under a variety of conditions, which can be governed by the particular dopant source present in the unchanged source layer. In some embodiments, the dopant-containing material present in the source layer may not immediately diffuse into the copper or may not immediately react with the copper. In this embodiment, the dopant can be first produced, for example, by exposing the substrate to high temperatures. In other embodiments, the diffusion of the dopant and / or the reaction of the dopant is also promoted by heating the substrate. In some embodiments, the thickness of the protective cap can be adjusted by adjusting the time for exposing the substrate to high temperatures and the exposure temperature itself. In some embodiments, the formation of the protective cap is promoted by heating the substrate to a temperature of at least about 100 DEG C for a predetermined period of time (e.g., for about 0.25 to 60 minutes).

Upon formation of the protective cap, in step 311, a doped or undoped silicon carbide layer is deposited. The resulting structure is shown in Figure 4e. A silicon carbide layer 411 is deposited on the upper portion of the passivation layer 409 over the copper wiring and the insulating film region. The silicon carbide layer serves as an etch stop layer or an insulating film diffusion barrier layer, and is typically deposited to a thickness of about 100 to 500 ANGSTROM. For example, a silicon carbide layer is deposited by CVD (preferably by PECVD) by exposing the substrate to a silicon-containing and carbon-containing precursor in a plasma discharge. For example, silanes, alkylsilanes, and hydrocarbons can be used as precursors. When doped silicon carbide is deposited, the dopant-containing precursor is further implanted into the process chamber. For example, CO ₂ , O ₂ or N ₂ O may be added during the deposition of the oxygen-containing silicon carbide, B ₂ H ₆ may be added to deposit the boron-doped silicon carbide, NH ₃ and N ₂ can be added to deposit nitrogen-doped silicon carbide. In other embodiments, doped or undoped silicon nitride may be deposited on top of the passivation layer to serve as an etch stop layer or diffusion barrier layer. In some embodiments, the deposition of an insulating film diffusion barrier layer is performed at a temperature higher than the temperature used to form the capping layer (including formation of the source layer and the passivation). For example, in some embodiments, the formation of a protective cap is implemented at a temperature below 350 占 폚 (e.g., at about 200-350 占 폚) and at a temperature above about 350 占 폚 (e.g., A diffusion barrier deposition is performed.

In some cases, the insulating film diffusion barrier or etch stop layer is optional because the passivation layer itself may have properties suitable to serve as a diffusion barrier or etch barrier. For example, a passivation layer containing a specific metal oxide may serve as a diffusion barrier layer, thereby eliminating the need for deposition of a separate silicon carbide layer.

The process shown in FIG. 3 proceeds to the subsequent process 313, and an interlayer insulating film (for example, silicon dioxide, organic silicon glass, porous organic insulating film, etc.) is deposited in the process 313. An insulating film is deposited over the diffusion barrier or etch stop layer (e.g., over the silicon carbide layer), or the insulating film is deposited directly over the passivation layer if the passivation material has properties appropriate to serve as diffusion barriers. The insulating film can be deposited by PECVD or by a spin-on method, and is typically deposited to a thickness between about 3,000 and 10,000 ANGSTROM. Thereafter, a damascene process can be followed, as shown in Figures 1C-1E.

It is understood that the process depicted by the flowchart shown in FIG. 3 is exemplary only and that various variations of the process may be implemented. For example, the various processes shown in FIG. 3 may be performed in different orders. Specifically, implantation of the active component (dopant) into the copper layer can be performed at different times during the process. In some embodiments, the generation and diffusion of the dopant may begin after the etch stop layer or diffusion barrier layer is deposited. In some embodiments, after the ILD layer is formed, diffusion of the dopant in the post-treatment is facilitated. Often this process is performed by heating the substrate to a temperature of about 100 캜 or more. In other embodiments, the active component (dopant) may diffuse into the copper or react with the copper before the source layer is passivated. In this embodiment, the amount of implanted dopant can be controlled by adjusting the contact time of the unchanged source layer with copper and / or by controlling the process temperature.

In some embodiments, the process shown in FIG. 3A is modified by partially passively bypassing, rather than partially, the source layer present on the copper interconnect, thereby substantially preventing the dopant element from diffusing into the copper interconnect. This modification is advantageous in some cases because it is capable of achieving improved electron mobility performance while minimizing the increase in interconnect resistance due to dopant diffusion.

Another embodiment of the process is illustrated by the process flow diagram shown in FIG. 3B. This process utilizes a high temperature deposition of an aluminum-containing source layer over an oxide-free copper surface. The above process starts in step 301 by providing a partially fabricated semiconductor element having a pattern of copper wiring to the insulating film. For example, a substrate (e.g., the substrate shown in FIG. 4A) may be used. In some embodiments, copper wiring is embedded in a layer of a ULK dielectric (e.g., a porous and organic dielectric film having a dielectric constant of 2.8 or less). In the embodiment described in FIG. 3B, it is very important to provide an oxide-free copper surface to prevent reaction between the copper oxide and the organoaluminum precursor. Even if a thin layer of copper oxide is to change the aluminum deposition means, aluminum oxide may be formed. In the embodiment shown in FIG. 3B, such immediate aluminum oxide formation is not required on the copper surface.

To remove the copper oxide, the substrate is pre-cleaned in step 303. This pre-cleaning is controlled in such a way that the copper oxide is completely removed from the copper surface. This control can be achieved by selecting an appropriate pre-wash duration and process conditions. This can be pre-cleaned by direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment, as previously described with respect to Figure 3a. When a soft ULK insulating film is used, pre-treatment is used in some embodiments in the absence of direct plasma.

After the oxide-free copper layer is obtained, the partially fabricated device is contacted with the organoaluminum reactant at a substrate temperature of at least about 350 < 0 > C (e.g., above about 400 & Layer can be formed. Significantly, at lower temperatures, deposition of the aluminum-containing layer on the oxide-free copper surface will not occur at the proper rate. A variety of organoaluminum reactants may be used, in some embodiments trialkylaluminum, and especially trimethylaluminum, is preferred. Examples of suitable reactants include precursors selected from the group consisting of trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutylaluminum, and tris (diethylamino) aluminum. In the absence of a plasma, the reactants in the CVD chamber contact the substrate, typically forming an aluminum-containing layer on top of both the exposed insulating film and the copper surface. For example, the thickness of the layer can be controlled by adjusting the reactant flow rate and substrate temperature. Typically, a layer deposited over an insulating layer may be spontaneously oxidized upon deposition (due to oxidizing species present in the insulating layer) to form a non-conductive layer having Al-O bonds. In the case where the aluminum-containing layer is not completely oxidized on the insulating film, the aluminum-containing layer is changed in a post-treatment step in which all of the conductive material on the insulating film is changed to a non-conductive form so as to prevent a short circuit between the interconnects. Regardless of whether the aluminum-containing layer deposited over the insulating film is immediately spontaneously oxidized upon deposition, some or all of the aluminum-containing layer present on the copper may be immobilized (in some embodiments, Compound) can be used.

Process 307 provides two post-processing options. In the first embodiment, only the upper portion of the aluminum-containing layer present on the copper is changed to form the passivation layer, where the portion of the unaltered layer remains in contact with the layer of copper, and in step 309 , And aluminum from unchanged portions diffuses into copper. In an alternative embodiment, all of the aluminum-bearing layer present on the copper is changed to form a free-flowing compound, thereby substantially preventing the diffusion of aluminum into the copper wiring. As the interconnect resistance is undesirably increased due to excessive diffusion of aluminum to copper and the formation of a thin, immovable cap (such as an Al-O or Al-N bond) over the copper improves the adhesion to the insulating film, , It is desirable to minimize or completely avoid aluminum diffusion

As described in connection with Figure 3a, a variety of post-treatments can be used, including direct plasma treatment, remote plasma treatment, UV treatment, and thermal (plasma-free) treatment at elevated temperature or room temperature.

In one embodiment, a plasma-free oxidation process (at room or elevated temperature) can be used to form a layer having Al-O bonds on the copper surface. For example, a substrate having an aluminum-containing layer in contact with an oxygen-containing reactant (e.g., O ₂ , O ₃ , N ₂ O, H ₂ O or CO ₂ ) in the absence of a plasma A floating Al-O-containing material can be formed.

In yet another embodiment, a plasma-free nitridation process (at room temperature or elevated temperature) may be used to form a layer having Al-N bonds on the copper surface. For example, in the absence of a plasma (after treatment of the organoaluminum reactant), the aluminum-containing layer may contact the oxygen-containing reactant (e.g., ammonia).

Plasma-free post-treatment (including UV and heat treatment) is particularly preferred when the substrate comprises a mechanically weak ULK dielectric film, which can minimize dielectric film damage.

After the post-treatment process is completed, in processes 311 and 313, an insulation film diffusion barrier layer deposition and an interlayer insulation film deposition are performed as described in connection with FIG. 3A.

The methods described above can provide adjustable resistivity and improved electron transfer properties to the interconnect. The thickness of the protective capping layer formed by these methods can range from about 10 A to about 10,000 A. It is particularly advantageous that the methods provide controllability over the thickness of the capping layer in the range of about 10 to 100 angstroms, in particular in the range of 10 to 60 angstroms. Capping films ranging in thickness from about 10 to 60 angstroms provide an especially small resistive shift of less than 1% and less than 3% in the interconnect, and such small resistive shifts are presently required in the IC industry.

Device

Generally, protective cap formation can be performed in any type of apparatus, which allows for the injection of volatile precursors, and can be used to control the reaction conditions (e.g., chamber temperature, precursor flow rate, exposure time, etc.) ≪ / RTI > In order to prevent oxidation and contamination of the substrate due to carelessness, it is often preferable to perform the steps 301 to 311 without exposing the substrate to the atmospheric environment. In one embodiment, steps 301 to 311 are performed successively in one module without releasing the vacuum state. In some embodiments, steps 301-311 are performed in a single CVD (preferably PECVD) apparatus having multiple stations in one chamber or multiple chambers. A VECTOR ^TM PECVD device available from Novellus Systems, San Jose, CA is an example of a suitable device.

An exemplary apparatus will include one or more chambers or "reactors" housing one or more wafers and suitable for wafer processing. Each chamber can house one or more wafers for processing. One or more chambers hold the wafer in the designated position (with or without movement, such as rotation, vibration, or agitation, at that location). In one embodiment, the wafer undergoing the source layer and etch stop layer deposition is transported from one station to another station in the reactor during the process. During the process, each wafer is held in place by a support, wafer chuck, and / or other wafer holding device. In certain processes in which the wafer is heated, the apparatus may include a heater, such as a heating plate. In a preferred embodiment of the present invention, a PECVD system may be used. In a more preferred embodiment, the PECVD system comprises an LF RF power supply.

5 is a simplified block diagram illustrating various reactor components arranged to implement the present invention. As shown, the reactor 500 includes a process chamber 524 that surrounds the other components of the reactor and includes a showerhead 514 that cooperates with a heater block 520 on the ground, Lt; RTI ID = 0.0 > a < / RTI > A high frequency RF generator 502 and a low frequency RF generator 504 are connected to a matching network 506 and in turn the matching network is connected to a showerhead 514.

Within the reactor, the wafer support 518 supports the substrate 516. The support typically includes a chuck, a fork, or a lift pin to fix and transport the substrate during deposition reactions or during deposition reactions. The chuck can be an electrostatic chuck, a mechanical chuck, or any other type of chuck available in industry and / or research.

Process gases are injected through inlet 512. A plurality of source gas lines 510 are connected to the manifold 508. The gases may or may not be premixed. Appropriate valve and flow control means are used during pre-cleaning, during formation of the source layer, during formation of the passivation layer, and to ensure correct gas during the doping process of the process. In the case where the chemical precursor is transported in liquid form, liquid flow control means is used. The liquid is then vaporized during transport of the liquid and mixed with other process gases in a manifold heated above the vaporization point of the liquid prior to reaching the deposition chamber.

The process gases exit chamber 500 through inlet 522. A vacuum pump 526 (e.g., one or two stage mechanical dry pump and / or turbomolecular pump) typically evacuates the process gas and is controlled by a flow control device such as a throttle or pendulum valve Thereby maintaining the inside of the reactor at a proper low pressure.

In one of the embodiments, a multi-station device may be used to form the capping layer and the diffusion barrier. The multi-station reactor can increase the efficiency of wafer processing by allowing different processes to be driven simultaneously in one chamber environment. One example of such a device is shown in Fig. A schematic representation of the plan view is shown. The apparatus chamber 601 includes four stations 603 to 609 and two load locks, an inlet load lock 619 and an outlet load lock 617. In other embodiments, a single load lock may be used for both the inlet and the outlet of the wiper. Generally, any number of stations are possible within a single chamber of a multi-station device. Station 603 is used to load and unload substrate wafers. The stations 603 to 609 may have the same or different functions. For example, some of the stations may be used exclusively to form the capping layer, and other stations may be used to deposit the insulating film diffusion barrier film. Moreover, some stations may be used exclusively for copper oxide reduction.

In one of the embodiments, the individual stations may operate under separate process conditions and may be substantially isolated from each other. For example, one station may operate under one temperature regime and another chamber may operate under a different temperature regime.

In one embodiment, the pre-cleaning process, the deposition of the source layer, and the formation of the passivation layer are performed in one preferred temperature regime and are performed in one station of the multi-station device. In some embodiments, deposition of the insulating film diffusion barrier may require different temperature regimes and may be performed at different stations. In some embodiments, the entire capping process, including pre-processing, formation of the source layer, passivation, and formation of the dopant-containing cap, is performed in a single station or in one station of the multi-station device. In some embodiments, the deposition of the insulating film diffusion barrier may be performed in the same station as the capping process. In some cases, the inlet load lock 619 may be used to pre-clean or pre-treat the wafer. This may involve, for example, oxide removal by chemical reduction.

In one example, the station 603 may be used exclusively for pre-cleaning and for forming the capping layer (from the precursor layer and the passivation layer). The station 603 may operate in a temperature range of about 200 to 400 degrees Celsius and this temperature range is preferred in some embodiments for both the capping and pre-cleaning processes. Deposition of insulating barrier barrier material such as silicon carbide at the stations 605, 607 and 609 can be performed at about 350 to 400 캜, which is the preferred process temperature for some silicon carbide deposition processes.

Advantageously, pre-cleaning, deposition of the source layer, passivation, and implantation of the dopant may require similar conditions in some embodiments and may be performed in one station 603.

According to the embodiment described above, the station 603 is a pre-clean station and a protective cap forming station. Both stations 605, 607 and 609 may operate for deposition of an insulating film diffusion barrier layer. The index plate 611 can be used to lift the substrate from the support and then accurately position the substrate at the processing station. After the wafer substrate is loaded into the station 603 and there is subjected to any processing (e.g., pre-cleaning and capping, including precursor layer deposition and passivation), the wafer substrate is guided to the station 605 And passivation) and / or insulation film deposition are performed. Thereafter, the wafer is transferred to the station 607 to start or continue deposition of the diffusion barrier insulating film. Further, the substrate is guided to the station 609 to perform additional deposition of the barrier insulating film, and then the substrate is guided to the station 603, the substrate is unloaded and the module is changed to a new wafer. During normal operation, a separate substrate occupies each station and the substrate is transported to the new station each time the process is repeated. Thus, an apparatus with four stations 603, 605, 607, and 609 enables simultaneous processing of four wafers, where one or more stations perform processes different from those performed at other stations . Alternatively, four wafers may be subjected to the same process at all four stations without dedicated use of a particular station for deposition of a particular layer.

Some specific examples of station-to-station will now be provided. In a first example, the inlet load lock performs pre-treatment (e. G., Reduction of copper oxide). A first station (e.g., station 603 or a plurality of consecutively arranged first stations) of the apparatus then forms a capping layer (e.g., by exposing it to a precursor such as TMA). The second station (e.g., the station of FIG. 6) then performs post-processing such as passivation (e.g., exposure to nitrogen, ammonia, and / or hydrogen as described herein). The remaining stations in the device (e.g., stations 607 and 609) then perform diffusion barrier formation.

In another example, a first station (e.g., station 603) performs preprocessing and a second station (e.g., station 605 or a series of consecutive stations) performs capping layer formation and post- , Passivation) and the remaining stations perform the insulation film diffusion barrier layer deposition. In yet another example, the first station performs pre-processing, capping layer deposition, and post-processing. The remaining stations perform diffusion barrier formation.

The process conditions and the process flow itself can be controlled by the control unit 613 and the control unit can monitor, maintain, and control specific process variables (e.g., HF and LF power, gas flow rate and time, temperature, pressure, And / or < / RTI > For example, instructions may be included that specify the source layer deposition and the flow rate of borane and ammonia for passivation. The instructions may specify all of the parameters for performing the processes in accordance with the methods described above. For example, the instructions may include parameters for pre-cleaning, source layer deposition, formation of a passivation layer, dopant implantation into copper interconnects, and dielectric barrier diffusion barrier deposition. The controller may contain different or the same instructions for different device stations, whereby the device stations may operate independently or synchronously.

Another example of a multi-station device is shown in Fig. The multi-station device 701 includes six stations 703, 705, 707, 709, 711, and 713 residing in three separate process chambers 717, 719, and 721, It includes two stations. A robot-containing chamber 715 adjacent to the chambers 717, 719, and 721 provides a means for loading and unloading wafers into the station. A controller 723 provides instructions for operation of the multi-station device 701. The individual stations in one chamber can be isolated from each other and perform the same or different processes. In one embodiment, two wafers are simultaneously transported to stations 703 and 705, which are in one chamber 721, so that the same processes, including pre-cleaning, source layer deposition, passivation layer formation, and copper doping, Experience. After this process is completed, the two wafers are removed from the chamber 721 and simultaneously inserted into the stations 707 and 709 present in the chamber 709. In such a chamber, a layer of diffusion barrier material is deposited at the same time. Thereafter, the wafer is removed from the chamber 719 and inserted into the stations 711 and 713 present in the chamber 717, followed by further processing. In some embodiments, the formation of a protective capping layer can be performed in a multi-chamber device, and different sub-processes (e.g., source layer deposition, passivation, dopant diffusion) are performed in different chambers.

There are a number of ways in which a capping process can be implemented in a multi-station tool such as that shown in Figures 6 and 7. In general, the processes described are easily integrated into a damascene flow that does not require substantial source-consuming substrate processing, and can be performed in the same device as the insulating film diffusion barrier deposition. Moreover, the resistivity control by the emission of the adjustable dopant is particularly advantageous. The described method is also useful for forming an interconnect with improved adhesion between copper and an insulating film diffusion barrier.

Some embodiments of the described methods will now be described as a specific example.

Experimental Example

The fabrication of a copper interconnect with a boron-doped protective cap and a passivation layer containing boron and nitrogen will be illustrated in connection with the experimental example.

In the described example, the process is initiated by a plasma pre-clean operation. A partially fabricated semiconductor device with an exposed pattern of copper interconnects in an ultra low-k insulator (k = 2.5; 5,000 A thick) was obtained after the CMP process and a PECVD VECTOR ^TM Was placed in the process chamber of the device. The entire capping process was performed at one of the four-station devices. First, the substrate was pre-heated to 350 ° C. and H ₂ was injected into the process chamber at a flow rate of 4,000 sccm. H ₂ flowed at a pressure of 4 Torr for a process time of 0 seconds to 30 seconds. At a process time of 30 seconds, the HF RF plasma was subjected to high heat and maintained at a power of 1.23 W / cm < ² > The substrate was washed with H ₂ After pre-washing with plasma, H ₂ flow and plasma power were turned off, B ₂ H ₆ was injected into the process chamber and mixed with argon. The mixture had a concentration of B ₂ H ₆ of about 5% by volume and was injected at a flow rate of about 3600 sccm with N ₂ injected at a flow rate of 2400 sccm. These gases flowed for a process time of 45 seconds to 85 seconds, during which time a source layer containing BH _x was deposited on the substrate. The deposition was performed at a temperature of about 350 DEG C and a pressure of about 2.3 Torr. The thickness of the source layer deposited on top of copper is estimated to be about 215 ANGSTROM and the thickness of the source layer deposited on top of the insulating layer is estimated to be about 159 ANGSTROM. Source BH _x After the layer was deposited, the boron flow was stopped and the layer was passivated (BNH) to form _x . The passivation was carried out between 85 seconds and 90 seconds process time of about 7000sccm flow rate with the N ₂ flow rate of NH ₃ 2800sccm Infusion was accompanied. High heat was applied to the plasma with an HF component at a power level of 0.80 W / cm ² and an LF component at a power level of 0.37 W / cm ² and maintained for 90 to 96 seconds. Passivation was performed at a temperature of about 350 DEG C and a pressure of about 2.3 Torr. BH _x on the insulating film The total thickness of the layer was changed to (BNH) _x and about 25% of the thickness of the source layer present on the copper was changed to (BNH) _x . (BNH) _x layer was later analyzed using an FT IR spectrometer. Peaks at 3430 cm ^-1 (ν _NH ), 2560 cm ^-1 (υ _BH ), and 1375 cm ^-1 (ν _BN ) were observed in the IR spectrum.

Boron diffused into the copper wiring to form a boron-doped copper layer. Boron diffusion may occur before and after the upper portion of the source layer is nitrided (passivated). The thickness of the boron-doped cap present in the copper wiring was estimated to be about 25 to 75 angstroms.

At a temperature of 350 캜, the entire capping process was performed in a single station. Thereafter, at three different stations of the PECVD apparatus at 350 DEG C using tetramethylsilane, ammonia, and nitrogen as process gases in the plasma state, Si _x C _y N _z A diffusion barrier layer (about 500 ANGSTROM) was deposited on the substrate. In each of these three stations, one-third of the carbide layer thickness was deposited.

The adhesion energy for a Cu (5,000 Å) -Si _x C _y N _z (500 Å) sandwich with or without a boron-containing cap was measured using a four-point bending adhesion test. The higher adhesion energy of 28.4 J / m < ² >, compared to the bond energy of only 15.3 J / m ² obtained for a conventional sandwich structure without a B-doped cap, Was observed. It is known that improved adhesion forces are typically correlated with improved electron mobility performance.

Leakage current and saturated capacitance were measured for a structure with a B-doped protective cap and (BNH) _x passivation layer. It has been observed that these parameters are substantially unaffected by the described capping procedure.

While various details have been omitted for clarity, various design alternatives may be implemented. Accordingly, these examples are to be considered illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the claims.

Claims (23)

A method of forming a semiconductor device structure,
(a) exposing an exposed region of an oxide-free copper or copper alloy layer to an insulator film at a substrate temperature of 350 DEG C or higher to form a first layer comprising aluminum on top of both the copper or copper alloy layer and the insulator film, Contacting the substrate having an exposed area of the substrate with an aluminum-containing compound;
(b) chemically changing a portion or all of the first layer to form a passivation layer comprising aluminum; And
(c) depositing an insulating layer over the passivation layer. The method according to claim 1,
Wherein the surface of the substrate is cleaned before the step (a) so as to completely remove the copper oxide from the surface of the layer of copper or copper alloy. 3. The method of claim 2,
Wherein said cleaning is selected from the group consisting of direct plasma processing, far-field plasma processing, UV processing, and thermal processing in a gas comprising at least one of N ₂ , NH ₃ , and H ₂ . The method according to claim 1,
Wherein the step (a) comprises contacting the substrate with an organoaluminum compound in the absence of a plasma. 5. The method of claim 4,
Wherein said step (a) comprises contacting said substrate with an organoaluminum compound at a substrate temperature of at least 400 < 0 > C. 5. The method of claim 4,
Wherein the organoaluminum compound is trimethylaluminum. The method according to claim 1,
Wherein the step (b) comprises completely passivating the first layer present on the layer of copper or copper alloy without aluminum diffusing into the layer of copper. The method according to claim 1,
Wherein the step (b) comprises partially passivating the first layer present on the layer of copper or copper alloy while allowing aluminum to diffuse partially into the layer of copper. The method according to claim 1,
The forming of the passivation layer in the step (b) includes forming an immobile compound including Al-N bonds. 10. The method of claim 9,
Wherein said step (b) comprises treating said substrate with a nitrogen-containing agent, wherein said treatment is selected from the group consisting of direct plasma treatment, remote plasma treatment, UV treatment, Method of forming structures. 11. The method of claim 10,
Wherein the step (b) comprises treating the substrate with a nitrogen-containing agent in the absence of plasma. 12. The method of claim 11,
Wherein the insulating film is an ULK insulating film. The method according to claim 1,
Wherein forming the passivation layer in step (b) comprises forming an immobile compound comprising Al-O bonds. 14. The method of claim 13,
Wherein said step (b) comprises treating said substrate with an oxygen-containing agent, wherein said treatment is selected from the group consisting of direct plasma treatment, far-field plasma treatment, UV treatment, Method of forming structures. 14. The method of claim 13,
Wherein the step (b) comprises contacting the substrate with an oxygen-containing agent in the absence of plasma. 16. The method of claim 15,
Wherein the insulating film is an ULK insulating film. 14. The method of claim 13,
Wherein the step (b) comprises treating the substrate with an oxygen-containing agent selected from the group consisting of O ₂ , N ₂ O, CO ₂ , and O ₃ . The method according to claim 1,
Wherein the steps (a), (b), and (c) are performed in a chemical vapor deposition (CVD) apparatus. The method according to claim 1,
Wherein the insulating layer deposited in step (c) is an etch stop insulating layer. 20. The method of claim 19,
Wherein the etch stop insulating layer comprises a doped or undoped material selected from the group consisting of silicon nitride and silicon carbide. The method according to claim 1,
Wherein the insulating layer deposited in step (c) is an interlayer dielectric (ILD) layer deposited directly on the passivation layer. An apparatus for forming a semiconductor device structure,
(a) a process chamber having an inlet for the injection of gases or volatile metal-containing reactants;
(b) a wafer support for securing the wafer in place while depositing a metal-containing layer on the wafer substrate in the process chamber; And
(c) a controller,
The controller comprising:
(I) program instructions for processing a substrate having an exposed insulating film with exposed copper or copper alloy to remove the oxide film from the exposed copper or copper alloy;
(Ii) exposing the exposed areas of the oxide-free copper or copper alloy and the insulating film at a substrate temperature of 350 占 폚 or higher to form a first layer comprising aluminum on top of both the insulating film and the copper or copper alloy; Program instructions for contacting a substrate having a region with an aluminum-containing reactant; And
(Iii) a program instruction for chemically changing a portion or all of the first layer to form a passivation layer comprising aluminum. 23. The method of claim 22,
Wherein the controller program instruction (ii) implements a process for contacting the substrate with an aluminum-containing reactant in the absence of plasma.

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