US10049924B2 - Selective formation of metallic films on metallic surfaces - Google Patents

Selective formation of metallic films on metallic surfaces Download PDF

Info

Publication number
US10049924B2
US10049924B2 US15/609,497 US201715609497A US10049924B2 US 10049924 B2 US10049924 B2 US 10049924B2 US 201715609497 A US201715609497 A US 201715609497A US 10049924 B2 US10049924 B2 US 10049924B2
Authority
US
United States
Prior art keywords
surface
method
metal
embodiments
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/609,497
Other versions
US20180068885A1 (en
Inventor
Suvi P. Haukka
Antti Niskanen
Marko Tuominen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM International NV
Original Assignee
ASM International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US35360310P priority Critical
Priority to PCT/US2011/039970 priority patent/WO2011156705A2/en
Priority to US201313702992A priority
Priority to US14/613,183 priority patent/US9257303B2/en
Priority to US14/988,374 priority patent/US9679808B2/en
Priority to US15/609,497 priority patent/US10049924B2/en
Application filed by ASM International NV filed Critical ASM International NV
Publication of US20180068885A1 publication Critical patent/US20180068885A1/en
Application granted granted Critical
Publication of US10049924B2 publication Critical patent/US10049924B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14Deposition of only one other metal element
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02697Forming conducting materials on a substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • H01L21/32053Deposition of metallic or metal-silicide layers of metal-silicide layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883Post-treatment or after-treatment of the conductive material

Abstract

Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.

Description

REFERENCE TO RELATED APPLICATIONS

The present application is a continuation U.S. application Ser. No. 14/988,374, filed on Jan. 5, 2016, which is a continuation of U.S. application Ser. No. 14/613,183, filed on Feb. 3, 2015, now U.S. Pat. No. 9,257,303, which is a continuation of U.S. National Phase application Ser. No. 13/702,992, filed Mar. 26, 2013, now U.S. Pat. No. 8,956,971, which claims priority to International Application No. PCT/US2011/039970, filed Jun. 10, 2011 and claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 61/353,603 filed Jun. 10, 2010, each of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

Field of the Invention

The present application relates generally to the field of semiconductor fabrication.

Description of the Related Art

Integrated circuits are currently manufactured by an elaborate process in which various layers of materials are sequentially constructed in a predetermined arrangement on a semiconductor substrate.

Meeting the ever increasing electromigration (EM) requirement in copper interconnects is becoming more difficult as Moore's law progresses, resulting in smaller devices. As line dimensions shrink, critical void size for EM failure is also reduced, causing a sharp decrease in mean time to failure. A significant improvement in EM resistance is required to enable continued scaling.

The interface between the dielectric diffusion barrier and copper has been shown to be the main path for copper diffusion and the weakest link in resisting EM failure. The implementation of a selective metal cap has been challenging because of the difficulty in achieving good selectivity on copper versus the dielectric surface. Methods are disclosed herein for selective deposition on metal surfaces that decrease electromigration.

SUMMARY OF THE INVENTION

Methods for selectively depositing a film on a substrate comprising a first metal surface and a second dielectric surface are provided herein. The methods may comprise a plurality of deposition cycles, each comprising contacting the substrate with a first precursor comprising silicon or boron to selectively form a layer of first material comprising Si or B on the first metal surface relative to the second dielectric surface; and converting the first material on the first metal surface to a second metallic material by exposing the substrate to a second precursor comprising metal.

Methods for selectively depositing a film on a substrate comprising a first copper surface and a second dielectric surface are provided herein. The methods comprise a plurality of deposition cycles comprising contacting the substrate with a first precursor comprising silicon to selectively form a layer of first material comprising Si or B over the first copper surface relative to the second dielectric surface; and converting the first material to a second metallic material by subsequently exposing the substrate to a second precursor comprising a metal fluoride; wherein the temperature of the substrate is selected such that the first material forms on the first surface with a selectivity of greater than about 90% versus the second surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart generally illustrating a method for forming a metal film in accordance with one embodiment

FIG. 2 is a schematic example illustrating a method for selectively forming a metal film on a copper portion of a substrate in accordance with one embodiment;

FIG. 3 is a schematic example illustrating a method for selectively forming a Tungsten (W) film on a copper portion of a substrate using disilane and WF6 in accordance with one embodiment.

FIGS. 4a and 4b show scanning electron microscope (SEM) images of a copper surface and a low-k surface, respectively, treated in accordance with embodiments of the methods disclosed herein.

FIG. 5 shows low-energy ion scattering spectrums of four samples.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In some embodiments, methods are disclosed for selective deposition of metal on metal while avoiding deposition on dielectric materials, such as low-k materials. In some embodiments, deposition is on copper for end of the line substrate processing.

In some embodiments, the selective deposition methods disclosed herein can deposit material onto copper thereby decreasing electromigration of the copper. In some embodiments, the selective deposition is on the copper metal layers and not on dielectric materials on the substrate. Deposition on the dielectric materials is undesirable because it can decrease the effective dielectric value.

In some embodiments, the selective deposition can avoid additional processing steps, thereby saving time and decreasing the costs associated with processing the substrates. For example, lithography will be very expensive in the future for small dimensions. With 8 or more layers of Cu metallization in the chips, the time and costs savings are magnified because time is saved for each area of copper metallization during substrate processing. Also, the methods disclosed herein can obviate the need for dielectric diffusion barriers and other processing steps

In some embodiments the method comprises selectively depositing a film on a substrate comprising a first metal surface and a second dielectric surface, the method comprising a plurality of deposition cycles. The cycle comprises: contacting the substrate with a first precursor comprising silicon or boron to selectively form a layer of first material comprising Si or B over the first metal surface relative to the second dielectric surface; and converting the first material to a second metallic material by exposing the substrate to a second precursor comprising metal. The selective deposition involves forming a greater amount of material on the first metal surface relative to the second dielectric surface. The selectivity can be expressed as the ratio of material formed on the first surface to amount of material formed on the first and second surfaces combined. Preferably, the selectivity is above about 80%, more preferably above 90%, even more preferably above 95%, and most preferably about 100%. In some embodiments, multiple cycles are used to deposit material. In some embodiments the metallic layer is elemental metal. In some embodiments, the metallic layer can include additional elements, such as Si, B, N, and dopants.

The substrate can comprise various types of materials. When manufacturing integrated circuits, the substrate typically comprises a number of thin films with varying chemical and physical properties. For example and without limitation, the substrate may comprise a dielectric layer and a metal layer. In some embodiments the substrate can comprise metal carbide. In some embodiments the substrate can comprise a conductive oxide.

Preferably the substrate has a first surface comprising a metal surface. In some embodiments the first surface comprises a metal nitride. In some embodiments the first surface comprises a transition metal. The transition metal can be selected from the group: Ti, V, Cr, Mn, Nb, Mo, Ru, Rh, Pd, Ag, Au, Hf, Ta, W, Re, Os, Ir and Pt. In some embodiments the first surface preferably comprises copper. In some embodiments the first surface comprises a noble metal. The noble metal can be selected from the group: Au, Pt, Ir, Pd, Os, Ag, Re, Rh, and Ru.

The second surface is preferably a dielectric surface. In some embodiments, the dielectric comprises SiO2. In some embodiments the dielectric is a porous material. In some embodiments the porous dielectric contains pores which are connected to each other, while in other embodiments the pores are not connected to each other. In some embodiments the dielectric comprises a low-k material, defined as an insulator with a dielectric value below about 4.0. In some embodiments the dielectric value of the low-k material is below about 3.5, below about 3.0, below about 2.5 and below about 2.3.

The precursors employed in the processes disclosed herein may be solid, liquid or gaseous material under standard conditions (room temperature and atmospheric pressure), provided that the precursors are in vapor phase before being conducted into the reaction chamber and contacted with the substrate surface. Plasma conditions can also be used. Thus, plasma can be formed from the vapor phase reactants or precursors in some embodiments. “Pulsing” a vaporized precursor onto the substrate means that the precursor vapor is conducted into the chamber for a limited period of time. Typically, the pulsing time is from about 0.05 to 10 seconds. However, depending on the substrate type and its surface area, the pulsing time may be even higher than 10 seconds. Pulsing times can be on the order of minutes in some cases. In some cases to ensure full saturation of reactions, the precursor might be supplied in multiple shorter pulses rather than in one longer pulse.

The mass flow rate of the precursors can also be determined by the skilled artisan. In one embodiment, for deposition on 300 mm wafers the flow rate of precursors is preferably between about 1 and 1000 sccm without limitation, more preferably between about 100 and 500 sccm.

The pressure in the reaction chamber is typically from about 0.01 to about 20 mbar, more preferably from about 1 to about 10 mbar. However, in some cases the pressure will be higher or lower than this range, as can be readily determined by the skilled artisan.

First Precursor:

In some embodiments a first precursor is provided to the substrate such that a layer is formed on a first surface of the substrate relative to a second surface of the substrate. In some embodiments the first precursor preferably comprises silicon or boron. In some embodiments a 0.05-4 nm thick layer of Si or B is formed on the metal surface of the substrate. In some embodiments a 0.1-2 m thick layer of Si or B is formed on the metal surface of the substrate. In some embodiments less than 1 nm of Si or B can be used. Without being bound to a theory, it is believed that the metal surface on the substrate can catalyze or assist in the adsorption or decomposition of the first precursor in comparison to the reactivity of the second surface or insulator. In preferred embodiments the formation of silicon or boron on the metal surface is self-limiting. In some embodiments the silicon or boron source chemical can decompose on the copper or metal surface.

In some embodiments, the silicon source chemical is selected from the silane family SinH2n+2 (n is equal to or greater than 1) or the cyclic silane family SinH2n (n is equal to or greater than 3). In some preferred embodiments the silicon source comprises silane or disilane. Most preferably the silane is disilane Si2H6 or trisilane Si3H8. In some embodiments the silicon source can be selected from silane compounds having the formula: SiHxLy, where L is a ligand selected from the groups including: alkyl, alkenyl, alkynyl, alkoxide, and amine. In some cases L is a ligand selected from the halide group: F, Cl, Br and I.

In some embodiments the first precursor comprises boron. In some embodiments the first precursor is diborane (B2H6). Diborane has similar properties to some of the silane based compounds. For example, diborane has a lower decomposition temperature than disilane but similar thermal stability to trisilane (silcore).

Other precursors comprising boron could also be used. The availability of a vast number of boron compounds makes it possible to choose one with the desired properties. In addition, it is possible to use more than one boron compound. Preferably, one or more of the following boron compounds is used:

Boranes according to formula I or formula II.
BnHn+x,  (I)

Wherein n is an integer from 1 to 10, preferably from 2 to 6, and x is an even integer, preferably 4, 6 or 8.
BnHm  (II)

Wherein n is an integer from 1 to 10, preferably form 2 to 6, and m is an integer different than n, from 1 to 10, preferably from 2 to 6.

Of the above boranes according to formula I, examples include nido-boranes (BnHn+4), arachno-boranes (BnHn+6) and hyph-boranes (BnHn+8). Of the boranes according to formula II, examples include conjuncto-boranes (BnHm). Also, borane complexes such as (CH3CH2)3N—BH3 can be used.

Borane halides, particularly fluorides, bromides and chlorides. An example of a suitable compound is B2H5Br. Further examples comprise boron halides with a high boron/halide ratio, such as B2F4, B2Cl4 and B2Br4. It is also possible to use borane halide complexes.

Halogenoboranes according to formula III.
BnXn  (III)

Wherein X is Cl or Br and n is 4 or an integer from 8 to 12 when X is Cl, or n is an integer from 7 to 10 when X is Br.

Carboranes according to formula IV.
C2BnHn+x  (IV)

Wherein n is an integer from 1 to 10, preferably from 2 to 6, and x is an even integer, preferably 2, 4 or 6.

Examples of carboranes according to formula IV include closo-carboranes (C2BnHn+2), nido-carboranes (C2BnHn+4) and arachno-carboranes (C2BnHn+6).

Amine-borane adducts according to formula V.
R3NBX3  (V)

Wherein R is linear or branched C1 to C10, preferably C1 to C4 alkyl or H, and X is linear or branched C1 to C10, preferably C1 to C4 alkyl, H or halogen.

Aminoboranes where one or more of the substituents on B is an amino group according to formula VI.
R2N  (VI)

Wherein R is linear or branched C1 to C10, preferably C1 to C4 alkyl or substituted or unsubstituted aryl group.

An example of a suitable aminoborane is (CH3)2NB(CH3)2.

Cyclic borazine (—BH—NH—)3 and its volatile derivatives.

Alkyl borons or alkyl boranes, wherein the alkyl is typically linear or branched C1 to C10 alkyl, preferably C2 to C4 alkyl.

In some embodiments the first precursor comprises germanium. In some embodiments, the germanium source chemical is selected from the germane family GenH2n+2 (n is equal to or greater than 1) or the cyclic germane family GenH2n (n is equal to or greater than 3). In some preferred embodiments the germanium source comprises germane GeH4. In some embodiments the germanium source can be selected from germane compounds having the formula: GeHxLy, where L is a ligand selected from the groups including: alkyl, alkenyl, alkynyl, alkoxide, and amine. In some cases L is a ligand selected from the halide group: F, Cl, Br and I.

Deposition Temperature:

In some embodiments the temperature is selected to facilitate the selective deposition. Deposition is defined as selective if the amount of the deposited material per surface area or volume (e.g. at/cm2 or at/cm3) on the first surface is greater than the amount of the deposited material per surface area or volume on the second surface. The amount of material deposited on the surfaces can be determined by measuring the thicknesses of each layer. In some cases, the thickness measurement might not be possible due to non-continuous film. In some cases the selectivity can be determined by measuring the deposited atoms per surface area or volume. The selectivity can be expressed as the ratio of material formed on the first surface to amount of material formed on the first and second surfaces combined. Preferably, the selectivity is above about 80%, more preferably above 90%, even more preferably above 95%, and most preferably about 100%.

Preferably the deposition temperature is selected such that the selectivity is above about 90%. In some embodiments, the deposition temperature is selected such that a selectivity of about 100% is achieved.

In some embodiments, the deposition temperature is selected such that the first precursor comprising silicon or boron forms a layer containing silicon or boron on the first metal surface.

The particular temperature can depend on the silicon or boron precursor that is selected along with the first surface or metal and the second surface or dielectric on the substrate. Preferably, the silicon or boron source forms on the first metal surface instead of the second dielectric surface to form a layer comprising silicon or boron. Preferably, the layer comprising silicon or boron is about a monolayer or less. In some cases, more than a monolayer of silicon or boron can be formed. In some embodiments a 0.05-4 nm thick layer of silicon or boron is formed on the metal surface of the substrate. In some embodiments preferably a 0.1-2 nm thick layer of silicon or boron is formed on the metal surface of the substrate. In some embodiments the formation of silicon or boron on the metal surface is self-limiting. In some embodiments the layer comprising silicon or boron is formed by decomposition.

In some cases the silicon or boron layer can form on both the metal and dielectric surfaces at higher temperatures. Thus, the use of lower temperatures is preferred because the silicon or boron can form on the metal surface at a lower temperature than the dielectric surface. Thus, the temperature can be selected such that the silicon precursor interacts preferentially with the first surface or metal surface relative to the second surface or dielectric surface.

The deposition temperature can be selected based on the silicon or boron source and the particular substrate surfaces that are used (e.g. low k surface and copper surface).

In some embodiments the deposition temperature is preferably less than 200° C., more preferably less than about 175° C., and most preferably less than about 150° C.

In one embodiment, when using a silicon containing precursor, such as disilane, and depositing on a copper surface a selectivity of more than about 90% relative to a dielectric can be achieved with a deposition temperature of 130±15° C. In other embodiments using disilane and depositing on a copper surface, a selectivity of more than about 95% relative to a dielectric can be achieved with a deposition temperature of below 160° C. The deposition temperature for trisilane can be even lower than the deposition temperature for disilane.

If a lower selectivity is preferred the temperatures can be slightly higher than processes for more than 90% selectivity.

Metal Source Chemicals

Preferably the second reactant comprises a metal. In some embodiments the metal is a transition metal. The transition metal can be selected from the group of: Ti, V, Cr, Mn, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Os, Ir and Pt. In some embodiments the second reactant comprises W, Ta, Nb, Ti, Mo or V. In some embodiments the second reactant preferably comprises tungsten.

In some embodiments the second reactant comprises a noble metal. The noble metal can be selected from the group: Au, Pt, Ir, Pd, Os, Ag, Rh, and Ru.

In some embodiments the second reactant comprises a metal halide (F, Cl, Br, I). In some preferred embodiments the second reactant comprises a transition metal halide. In some embodiments the second reactant preferably comprises fluorine. In some embodiments, the second reactant comprises WF6, TaF5, NbF5, TiF4, MoFx, VFx. In some embodiments the second reactant comprises WF6.

The second reactant can be used to form a variety of different materials on the substrate. In some embodiments the second reactant forms a metallic material on the substrate. Any of the metals disclosed above for the second reactant can be in the film deposited on the substrate.

In some embodiments an elemental metal film can be formed. In some embodiments a metal nitride film can be formed. In some embodiments a metal silicide film can be formed.

In some embodiments a metal or elemental metal film is first formed through reaction of the Si or B on the substrate surface and the second reactant and later converted to a corresponding metal silicide or metal nitride through further processing.

In some embodiments further processing of the metallic material can be done to dope the metallic material or convert the metallic material to a metal nitride or metal silicide. In some embodiments, for example, the material can be converted to a corresponding metal nitride using plasma or a NH3-treatment. In some embodiments an electrically conductive metallic material can be converted to a more electrically resistive material or to a dielectric material by using different treatments and depending on the starting metallic material.

The substrate temperature during the provision of the second reactant can be the same as the temperature during the provision of the silicon or boron containing reactant.

In embodiments where WF6 is used as the second reactant with disilane as the first reactant a temperature of about 150° C. can be used.

In some embodiments, the temperature of the substrate can be increased when providing the second reactant to increase the conversion of the metal reactant. For example, a higher temperature can be used when TaF5 and NbF5 are used as the second reactant. For example, when using TaF5 the temperatures can be over about 300° C. When using NbF5 the temperature can be above about 250° C. This can be accomplished by heating the substrate, using a higher reaction temperature for the second material or other means known to the skilled artisan.

In some embodiments multiple pulses of the reactants can be provided prior to providing the next reactant. In some embodiments, any excess reactants can be removed prior to the provision of the next reactant. In some embodiments the process chamber can be purged prior to provision of the next reactant.

In some embodiments vapor phase precursors can be provided to the reaction space with the aid of an inert carrier gas. Removing excess reactants can include evacuating some of the contents of the reaction space or purging the reaction space with helium, nitrogen or any other inert gas. In some embodiments purging can comprise turning off the flow of the reactive gas while continuing to flow an inert carrier gas to the reaction space.

In some embodiments the substrate surface is cleaned prior to the deposition process. For example, for embodiments when the first material is copper, the copper surface can be cleaned or reduced such that pure elemental copper is on the substrate surface. The cleaning step can be done in many known ways, for example using citric acid or hydrogen containing plasma or radicals, such as H-plasma or NH3-plasma. HCl treatment is one of the known cleaning methods. Other cleaning methods are also possible and can be selected based on the material on the substrate.

In some embodiments, conditions are selected such that etching of the low-k surface is avoided or minimized. At higher temperatures metal fluorides can start fluorinating the Si—OH groups and in some cases they can etch the low-k. The deposition temperature should be selected so that etching of the low-k dielectric is avoided or eliminated.

In some embodiments, the dielectric material or insulator surface, on which deposition is to be avoided, can be treated prior to deposition. In some embodiments, the dielectric or insulator surface can be treated to enhance the selectivity of the deposition process and decrease the amount of material deposited on the insulator surface. In preferred embodiments the insulator surface is a low-k surface, which has been outgassed to remove moisture absorbed from the atmosphere. In some embodiments the low-k material can be porous. In some embodiments different kinds of low-k restoration steps can be performed before the selective deposition. U.S. Pat. No. 6,391,785 discloses various surface modifications and treatments and is incorporated herein in its entirety. In some embodiments any of the surface modifications or treatments disclosed in U.S. Pat. No. 6,391,785 can be used in the methods disclosed herein.

Some dielectric materials can have porous structures. In order to avoid diffusion, etching, and other undesirable processes the pores can be sealed or terminated with protective groups. In some embodiments the pores are sealed via silylation. Etching can in part be avoided by silylating, i.e., forming —Si(CH3)3 groups on the low-k surface prior to metal fluoride or other first reactant introduction. Also it would be beneficial to be able to block the low-k pores to avoid reactant penetration into the low-k. Silylation is accomplished through the reaction of for instance Cl—Si(CH3)3 with Si—OH terminated surface: Si—OH+Cl—Si(CH3)3->Si—O—Si(CH3)3+HCl. Also the use of silicon compounds with longer carbon containing ligands is possible. Methods for sealing the pores are disclosed, for example, in U.S. Pat. No. 6,759,325. The disclosure of sealing methods in U.S. Pat. No. 6,759,325 is hereby incorporated by reference in its entirety.

In some embodiments an organic layer can be formed by ALD on the low-k material prior to deposition to block the pores and to make the low-k surface more resistant to metal fluorides.

In some embodiments where the selectivity is imperfect or a higher selectivity is desired, an isotropic selective metal etch can be used to remove material from the insulator surface without fully removing material from the metallic surface. For example, HCl vapor or a wet etch can be used.

FIG. 1 is a flow chart 10 in accordance with one embodiment. A substrate with a metal (copper) surface and a low-k surface is first provided 11. Next, the Cu surface is cleaned to remove oxide 12. The copper surface can be reduced to pure Cu by H2 plasma at low temperatures without destroying the low-k surface.

Next, a silicon or boron source is provided to the substrate, such that a silicon or boron containing species is deposited on the Cu surface 13. In some embodiments the silicon source is disilane. In some embodiments, the disilane can be selectively decomposed on the Cu surface relative to the low-k surface using a temperature at which the silicon precursor forms silicon on the copper surface but does form silicon on the hydrophobic low-k surface. In some embodiments, the silicon or boron source reacts with the copper surface in a self limiting manner. It is believed that the Cu surface can facilitate the formation of silicon relative to the formation on the low-k surface. Silicon dioxide based surfaces like the low-k (SiOC) surfaces are not catalytically active relative to metal surfaces. In some embodiments a 0.05-4 nm thick layer of silicon or boron is formed on the metal surface of the substrate in each cycle. In some embodiments preferably a 0.1-2 nm thick layer of silicon or boron is formed on the metal surface of the substrate in each cycle. In preferred embodiments the formation of silicon or boron on the metal surface is self-limiting.

After the silicon or boron layer is deposited on the copper layer a metal halide is used to convert 14 the silicon or boron layer to the corresponding metal in the metal halide. In preferred embodiments, WF6, TaF5, NbF5 or other compounds that are able to react with the Si or B layer are introduced to the substrate surface to form a metallic layer or metal silicide. In some embodiments, the silicon or boron precursor (e.g. disilane) and metal halide pulses can be repeated 15 to form a metallic layer 16 with a desired thickness. In some embodiments the metallic layer is elemental metal. In some embodiments, the metallic layer can include additional elements, such as Si, B, N, and dopants.

The deposition cycle can be defined as providing the silicon or boron precursor and providing the second metal reactant. In some embodiments no other reactants are provided in the deposition cycle. In some embodiments the deposition cycle is repeated to form a metallic layer with a desired thickness. In some embodiments a 0.05-4 nm thick metallic layer is formed in each cycle. In some embodiments, preferably a 0.1-2 nm thick metallic layer is formed in each cycle. In some embodiments the metallic layer has a thickness of 1-2 nm. In other embodiments the thickness of the deposited metallic layer is above about 2 nm, in some cases above about 30 nm, and in some cases above about 50 nm. In preferred embodiments the layer has thickness of less than 10 nm.

In some embodiments the deposition cycle is repeated 10 or more times. In some embodiments, the deposition cycle is repeated at least 50 times. In some embodiments the deposition cycle is repeated about 100 times or more. The number of cycles can be selected based on the desired thickness of the metal layer.

In some embodiments, no other reactants are provided besides the precursor comprising silicon or boron and the second metal reactant.

In some embodiments the material in the first surface, such as copper, is not converted or reacted to form another compound during the selective deposition cycle.

In some embodiments, after the one or more deposition cycles are completed a half deposition cycle can be performed. For example, a silicon or boron precursor pulse or alternatively a second metal reactant can be provided. In some embodiments, after the one or more deposition cycles a silicon or boron precursor pulse is provided. When a silicon or boron precursor pulse is provided, the formed material can form a sacrificial layer of silicon oxide or boron oxide when exposed to air or an oxygen containing atmosphere. The sacrificial layer can prevent the metallic material underneath the silicon oxide or boron oxide layer from oxidizing when exposed to air or an oxygen containing atmosphere outside the reactor. The formed silicon oxide or boron oxide layer can be removed in further processing steps, for example with a single pulse of metal source chemicals described herein, preferably with WF6, TaF5, NbF5, TiF4, MoFx or VFx and more preferably with WF6.

The following non-limiting examples illustrate certain preferred embodiments of the invention. They were carried out in an ASM Pulsar®2000 cross-flow ALD-reactor supplied by ASM Microchemistry Oy, Espoo.

EXAMPLE 1

To selectively deposit a metallic layer on a metal surface, for example, the surface is preferably very clean. The cleaning may be conducted via gas or liquid phase. Specifically for copper, citric acid or some other later-generation cleaning agents may be used in the liquid phase to remove the commonly employed benzotriazole (BTA) passivating agent from the surface. Alternatively, NH3 plasma may be used as a gas phase approach to remove the BTA layer. Finally, H-radicals are used to ensure the surface is void of any oxidized copper.

FIGS. 2 and 3 show schematic representations in accordance with some embodiments. FIG. 2 illustrates a substrate 20 with a silicon dioxide 22 insulating region and a copper surface 24. Selective deposition (not shown) is performed to deposit metal 26 on the copper regions 24 of the substrate while avoiding deposition on the SiO2 22.

FIG. 3 shows a schematic representation of a selective deposition process using disilane and WF6. The substrate 30 has a silicon dioxide surface 32 and copper surface 34. The cleaned, pure copper surface 34 is exposed to Si2H6 (disilane) at 150° C. This temperature is too low to allow spontaneous decomposition of disilane, but high enough that when in the presence of a metal surface the formation of Si on the metal surface will take place. As a result, the copper surface 34 is covered with a layer of silicon.

Next, the silicon layer is converted to a metallic layer by exposing it to a metal fluoride (second reaction step). Suitable fluorides are, for example, WF6, NbF5, and TaF5. Of these, WF6 is reactive enough to undergo the reaction at 150° C. In the case of other metal fluorides, elevated temperatures may be required for the second reaction step. As illustrated, in FIG. 3 the WF6 reacts with the deposited silicon to form SiF4 which leaves the substrate surface and deposits tungsten. After this step, the film deposition has completed a full cycle, an additional cycle can continue with the first step, if desired. Continuing with more deposition cycles will produce a thicker metal layer 36 on the metallic substrate. The selectivity will be retained and no film will be deposited on two variants of a low-k SiO2: Low-K 3.0 and Low-K 2.3.

EXAMPLE 2

A copper piece was cut and cleaned with citric acid. The citric acid solution was prepared by mixing approximately 5 g of citric acid crystals in 50 ml of water. The solution was stirred until all crystals had dissolved. A fresh solution was prepared for each film deposition run and discarded immediately after use. The copper piece was dipped in the solution, left immersed for 30 seconds, and stirred a few times during that period. The copper piece was then lifted and dried by draining the liquid back into the solution. If the piece was dried by nitrogen blowing, water marks were produced. Finally, the back side of the copper piece was dried by placing the piece on a piece of clean room tissue. The cleaned copper piece was then placed onto an adapter wafer and loaded into a vacuum load lock within three minutes of cleaning.

After loading the copper piece into the vacuum load lock, it was transported by vacuum transport into the reaction chamber. The film deposition took place in an ASM Pulsar®2000 cross-flow ALD-reactor. The temperature of the reaction chamber was 150° C. and the substrate was left to stabilize for one minute. Next, hydrogen radicals were used for the final cleaning of the copper surface to remove any oxide possibly formed after the cleaning. The overall pressure during the H-radical cleaning step was approximately 0.4 torr, and the H2 flow rate was 400 sccm. The plasma power was 125 W and the H-radical exposure time was 1.5 minutes.

Immediately after the cleaning step, the cleaned surface was exposed to a disilane pulse of 1 s, with a 2 s purge period before the following metal fluoride pulse. The flow rate of disilane was approximately 30 sccm during the pulse. This step produced a silicon layer on the copper surface. This silicon layer was then converted into a layer of metallic tungsten (W) by exposing it to WF6. The WF6 pulse length was 0.6 s with a 2 s purge. WF6 reacts with silicon to produce metallic tungsten on the surface, and volatile SiF4 as long as there is silicon remaining. As a result, a layer of W is formed, with WF6 as the surface species. If the deposition is continued with a disilane pulse, SiF4 is initially formed followed by formation of Si on the metal surface, this time facilitated by the tungsten surface. The deposition may be continued at least up to 35 nm thick layer of W while maintaining the selectivity. The overall pressure during the deposition was approximately 2.0 torr and the overall carrier gas used was purified N2.

The selectivity was retained for at least 50 nm of tungsten and no film was deposited on two variants of low-K (SiO2): Low-K 3.0 and Low-K 2.3.

FIG. 4a shows a SEM image of 100 cycles of providing disilane and WF6 to a Cu surface. FIG. 4b shows a SEM image of 100 cycles of providing disilane and WF6 to a Low-K 2.3 surface, which was in the same reactor during the deposition as the sample analyzed in FIG. 4 a.

FIG. 5 shows a low-energy ion scattering (LEIS) spectrum of the varies copper and dielectric samples. Disilane and WF6 were provided in each cycle. A curve marked with LEIS1 represents 2 cycles on a Cu surface. A curve marked with LEIS2 represents 100 cycles on a Cu surface. It can be seen from the LEIS2 spectrum that the Cu surface is fully covered by W as indicated by the peak at about 2675 eV. A curve marked with LEIS3 represents 100 cycles on a low-K 2.3 surface. A curve marked with LEIS4 represents 100 cycles on a low-K 3.0 surface. The peaks at energy values of about 2675 eV represent the W peak and the peak total area corresponds to the amount of W in the surface of the sample. With the scale of FIG. 5, the curves for LEIS1, LEIS3, and LEIS4 do not show significant peaks for W. It can be calculated from the peak areas in the spectrums that the selectivity of the W process applied to Cu vs. low-K 2.3 is at least about 98% and at least about 92% in the case of Cu vs. low-K 3.0.

It will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the scope of the invention. Similar other modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims.

Claims (20)

What is claimed is:
1. A method for forming an integrated circuit comprising selectively depositing a film on a substrate comprising a first metal surface and a second dielectric surface, the method comprising one or more deposition cycles comprising:
contacting the substrate with a first vapor-phase precursor;
removing excess first vapor-phase precursor;
contacting the substrate with a second vapor-phase second reactant comprising a metal halide, wherein the metal halide comprises W or Mo, and
removing excess second vapor-phase reactant,
wherein the film is deposited with a selectivity for the first metal surface relative to the second dielectric surface of above 80%.
2. The method of claim 1, wherein the second vapor-phase reactant is WF6.
3. The method of claim 1, wherein the first vapor-phase precursor is a silane or borane.
4. The method of claim 1, wherein the film comprises a metal nitride.
5. The method of claim 1, wherein the film comprises a metal silicide.
6. The method of claim 1, wherein the film consists essentially of elemental metal.
7. The method of claim 1, wherein the first metal surface comprises copper.
8. The method of claim 1, wherein the first metal surface comprises a noble metal.
9. The method of claim 1, wherein the second surface comprises a low-k material.
10. The method of claim 9, wherein the low-k material has a dielectric value of less than about 4.
11. The method of claim 1, wherein the second surface comprises SiO2.
12. The method of claim 1, wherein the selectivity is above 90%.
13. The method of claim 1, wherein the deposition cycle is repeated two or more times in succession.
14. The method of claim 1, wherein the one or more deposition cycles are carried out at a deposition temperature of less than about 200° C.
15. The method of claim 14, wherein the deposition temperature is less than about 150° C.
16. The method of claim 1, further comprising cleaning the substrate prior to the one or more deposition cycles.
17. The method of claim 16, wherein cleaning comprises removing a passivation layer from the first metal surface.
18. The method of claim 16, wherein cleaning comprises exposing the first metal surface to NH3 plasma.
19. The method of claim 1, further comprising treating the second surface prior to the one or more deposition cycles.
20. The method of claim 19, wherein treating comprises silylation.
US15/609,497 2010-06-10 2017-05-31 Selective formation of metallic films on metallic surfaces Active US10049924B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US35360310P true 2010-06-10 2010-06-10
PCT/US2011/039970 WO2011156705A2 (en) 2010-06-10 2011-06-10 Selective formation of metallic films on metallic surfaces
US201313702992A true 2013-03-26 2013-03-26
US14/613,183 US9257303B2 (en) 2010-06-10 2015-02-03 Selective formation of metallic films on metallic surfaces
US14/988,374 US9679808B2 (en) 2010-06-10 2016-01-05 Selective formation of metallic films on metallic surfaces
US15/609,497 US10049924B2 (en) 2010-06-10 2017-05-31 Selective formation of metallic films on metallic surfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/609,497 US10049924B2 (en) 2010-06-10 2017-05-31 Selective formation of metallic films on metallic surfaces

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/988,374 Continuation US9679808B2 (en) 2010-06-10 2016-01-05 Selective formation of metallic films on metallic surfaces

Publications (2)

Publication Number Publication Date
US20180068885A1 US20180068885A1 (en) 2018-03-08
US10049924B2 true US10049924B2 (en) 2018-08-14

Family

ID=45098694

Family Applications (4)

Application Number Title Priority Date Filing Date
US13/702,992 Active 2031-11-02 US8956971B2 (en) 2010-06-10 2011-06-10 Selective formation of metallic films on metallic surfaces
US14/613,183 Active US9257303B2 (en) 2010-06-10 2015-02-03 Selective formation of metallic films on metallic surfaces
US14/988,374 Active US9679808B2 (en) 2010-06-10 2016-01-05 Selective formation of metallic films on metallic surfaces
US15/609,497 Active US10049924B2 (en) 2010-06-10 2017-05-31 Selective formation of metallic films on metallic surfaces

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US13/702,992 Active 2031-11-02 US8956971B2 (en) 2010-06-10 2011-06-10 Selective formation of metallic films on metallic surfaces
US14/613,183 Active US9257303B2 (en) 2010-06-10 2015-02-03 Selective formation of metallic films on metallic surfaces
US14/988,374 Active US9679808B2 (en) 2010-06-10 2016-01-05 Selective formation of metallic films on metallic surfaces

Country Status (4)

Country Link
US (4) US8956971B2 (en)
KR (2) KR20180112118A (en)
TW (2) TWI529808B (en)
WO (1) WO2011156705A2 (en)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5507909B2 (en) * 2009-07-14 2014-05-28 東京エレクトロン株式会社 Film formation method
TWI529808B (en) 2010-06-10 2016-04-11 Asm Int Method for selectively depositing film on substrate
US9112003B2 (en) 2011-12-09 2015-08-18 Asm International N.V. Selective formation of metallic films on metallic surfaces
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9460997B2 (en) 2013-12-31 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for semiconductor devices
US9895715B2 (en) 2014-02-04 2018-02-20 Asm Ip Holding B.V. Selective deposition of metals, metal oxides, and dielectrics
US10047435B2 (en) 2014-04-16 2018-08-14 Asm Ip Holding B.V. Dual selective deposition
KR20160059810A (en) 2014-11-19 2016-05-27 에이에스엠 아이피 홀딩 비.브이. Method of depositing thin film
KR20160076208A (en) 2014-12-22 2016-06-30 에이에스엠 아이피 홀딩 비.브이. Semiconductor device and manufacuring method thereof
US9816180B2 (en) 2015-02-03 2017-11-14 Asm Ip Holding B.V. Selective deposition
US9490145B2 (en) 2015-02-23 2016-11-08 Asm Ip Holding B.V. Removal of surface passivation
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10204790B2 (en) 2015-07-28 2019-02-12 Asm Ip Holding B.V. Methods for thin film deposition
US10121699B2 (en) 2015-08-05 2018-11-06 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US9842734B2 (en) * 2015-12-21 2017-12-12 Imec Vzw Method of forming a feature of a target material on a substrate
US9981286B2 (en) 2016-03-08 2018-05-29 Asm Ip Holding B.V. Selective formation of metal silicides
US9892913B2 (en) 2016-03-24 2018-02-13 Asm Ip Holding B.V. Radial and thickness control via biased multi-port injection settings
US10204782B2 (en) 2016-04-18 2019-02-12 Imec Vzw Combined anneal and selective deposition process
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US10190213B2 (en) 2016-04-21 2019-01-29 Asm Ip Holding B.V. Deposition of metal borides
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
KR20170129475A (en) 2016-05-17 2017-11-27 에이에스엠 아이피 홀딩 비.브이. Method of forming metal interconnection and method of fabricating semiconductor device using the same
US9805974B1 (en) 2016-06-08 2017-10-31 Asm Ip Holding B.V. Selective deposition of metallic films
US9803277B1 (en) 2016-06-08 2017-10-31 Asm Ip Holding B.V. Reaction chamber passivation and selective deposition of metallic films
US10014212B2 (en) 2016-06-08 2018-07-03 Asm Ip Holding B.V. Selective deposition of metallic films
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US10177025B2 (en) 2016-07-28 2019-01-08 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel
US10229833B2 (en) 2016-11-01 2019-03-12 Asm Ip Holding B.V. Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US10134757B2 (en) 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
US20180158686A1 (en) * 2016-11-23 2018-06-07 Applied Materials, Inc. Deposition Of Metal Films
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate
TW201833362A (en) * 2017-01-31 2018-09-16 美商應用材料股份有限公司 Selectively depositing on the pattern of the application program
US10103040B1 (en) 2017-03-31 2018-10-16 Asm Ip Holding B.V. Apparatus and method for manufacturing a semiconductor device
USD830981S1 (en) 2017-04-07 2018-10-16 Asm Ip Holding B.V. Susceptor for semiconductor substrate processing apparatus
US20180342395A1 (en) * 2017-05-26 2018-11-29 Applied Materials, Inc. Selective deposition of metal silicides
US9947582B1 (en) 2017-06-02 2018-04-17 Asm Ip Holding B.V. Processes for preventing oxidation of metal thin films
US10249524B2 (en) 2017-08-09 2019-04-02 Asm Ip Holding B.V. Cassette holder assembly for a substrate cassette and holding member for use in such assembly
US10236177B1 (en) 2017-08-22 2019-03-19 ASM IP Holding B.V.. Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures

Citations (146)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863879A (en) 1987-12-16 1989-09-05 Ford Microelectronics, Inc. Method of manufacturing self-aligned GaAs MESFET
US4948755A (en) 1987-10-08 1990-08-14 Standard Microsystems Corporation Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
EP0469456A1 (en) 1990-07-30 1992-02-05 Mitsubishi Gas Chemical Company, Inc. Process for producing copper-clad laminate
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
US5633036A (en) 1995-04-21 1997-05-27 The Board Of Trustees Of The University Of Illinois Selective low temperature chemical vapor deposition of titanium disilicide onto silicon regions
EP0880168A2 (en) 1997-05-22 1998-11-25 Sharp Corporation System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides
US5869135A (en) 1997-10-03 1999-02-09 Massachusetts Institute Of Technology Selective chemical vapor deposition of polymers
US5925494A (en) 1996-02-16 1999-07-20 Massachusetts Institute Of Technology Vapor deposition of polymer films for photolithography
US6046108A (en) 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US20010019803A1 (en) 1999-12-06 2001-09-06 The Regents Of The University Of California Mitigation of substrate defects in reflective reticles using sequential coating and annealing
US20010025205A1 (en) 1994-11-14 2001-09-27 Applied Materials, Inc. Construction of a film on a semiconductor wafer
US20020068458A1 (en) 2000-12-06 2002-06-06 Chiang Tony P. Method for integrated in-situ cleaning and susequent atomic layer deposition within a single processing chamber
US20020090777A1 (en) 2001-01-05 2002-07-11 Leonard Forbes Methods of forming capacitor structures, and capacitor structures
US6482740B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH
US20030027431A1 (en) 1999-12-22 2003-02-06 Ofer Sneh Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition
US20030066487A1 (en) 2001-09-28 2003-04-10 Nobumasa Suzuki Plasma processing system and surface processing method
WO2002045167A3 (en) 2000-11-30 2003-05-30 Asm Inc Thin films for magnetic devices
US6586330B1 (en) 2002-05-07 2003-07-01 Tokyo Electron Limited Method for depositing conformal nitrified tantalum silicide films by thermal CVD
US20030143839A1 (en) 2000-05-15 2003-07-31 Ivo Raaijmakers Sealing porous structures
US20030181035A1 (en) 2001-12-21 2003-09-25 Applied Materials, Inc. Selective deposition of abarrier layer on a metal film
US6679951B2 (en) 2000-05-15 2004-01-20 Asm Intenational N.V. Metal anneal with oxidation prevention
KR20040056026A (en) 2002-12-23 2004-06-30 주식회사 하이닉스반도체 Method of forming a capping layer
US6811448B1 (en) 2003-07-15 2004-11-02 Advanced Micro Devices, Inc. Pre-cleaning for silicidation in an SMOS process
US20040219746A1 (en) 2003-04-29 2004-11-04 Micron Technology, Inc. Systems and methods for forming metal oxide layers
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US6878628B2 (en) 2000-05-15 2005-04-12 Asm International Nv In situ reduction of copper oxide prior to silicon carbide deposition
US20050136604A1 (en) 2000-08-10 2005-06-23 Amir Al-Bayati Semiconductor on insulator vertical transistor fabrication and doping process
US20050223989A1 (en) 2004-03-31 2005-10-13 Lee Chung J System for forming composite polymer dielectric film
US6958174B1 (en) 1999-03-15 2005-10-25 Regents Of The University Of Colorado Solid material comprising a thin metal film on its surface and methods for producing the same
US20060019493A1 (en) 2004-07-15 2006-01-26 Li Wei M Methods of metallization for microelectronic devices utilizing metal oxide
US20060047132A1 (en) 2004-09-02 2006-03-02 Rohm And Haas Electronic Materials Llc Method
US7067407B2 (en) 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US20060141155A1 (en) 2002-11-15 2006-06-29 Havard University Atomic layer deposition using metal amidinates
US7084060B1 (en) 2005-05-04 2006-08-01 International Business Machines Corporation Forming capping layer over metal wire structure using selective atomic layer deposition
US20060199399A1 (en) 2005-02-22 2006-09-07 Muscat Anthony J Surface manipulation and selective deposition processes using adsorbed halogen atoms
US7118779B2 (en) 2003-05-09 2006-10-10 Asm America, Inc. Reactor surface passivation through chemical deactivation
US20060226409A1 (en) 2005-04-06 2006-10-12 International Business Machines Corporation Structure for confining the switching current in phase memory (PCM) cells
US20060292845A1 (en) 2004-09-17 2006-12-28 Chiang Tony P Processing substrates using site-isolated processing
US20070063317A1 (en) 2005-06-24 2007-03-22 Samsung Electronics Co., Ltd. Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device
US20070099422A1 (en) 2005-10-28 2007-05-03 Kapila Wijekoon Process for electroless copper deposition
US20070241390A1 (en) 2006-04-14 2007-10-18 Masayuki Tanaka Semiconductor device and method for manufacturing the same
US7323411B1 (en) 2003-09-26 2008-01-29 Cypress Semiconductor Corporation Method of selective tungsten deposition on a silicon surface
US20080066680A1 (en) 1996-06-21 2008-03-20 Asm America, Inc. Sequential chemical vapor deposition
US20080072819A1 (en) 1998-09-11 2008-03-27 Asm International N.V. Metal oxide films
US7405143B2 (en) 2004-03-25 2008-07-29 Asm International N.V. Method for fabricating a seed layer
US20080179741A1 (en) 2007-01-31 2008-07-31 Christof Streck Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride
US7425350B2 (en) 2005-04-29 2008-09-16 Asm Japan K.K. Apparatus, precursors and deposition methods for silicon-containing materials
US20080241575A1 (en) 2007-03-28 2008-10-02 Lavoie Adrein R Selective aluminum doping of copper interconnects and structures formed thereby
US20080282970A1 (en) 2005-11-16 2008-11-20 Peter Nicholas Heys Cyclopentadienyl Type Hafnium and Zirconium Precursors and Use Thereof in Atomic Layer Deposition
US7476618B2 (en) 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US20090035949A1 (en) 2001-08-03 2009-02-05 Jaakko Niinisto Method of depositing rare earth oxide thin films
US7494927B2 (en) 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
US20090071505A1 (en) 2007-09-19 2009-03-19 Hitachi-Kokusai Electric Inc. Cleaning method and substrate processing apparatus
US20090081385A1 (en) 2007-09-14 2009-03-26 Peter Nicholas Heys Methods of atomic layer deposition using hafnium and zirconium-based precursors
US20090203222A1 (en) 2006-06-02 2009-08-13 Christian Dussarrat Method of forming dielectric films, new precursors and their use in semiconductor manufacturing
US7595271B2 (en) 2005-12-01 2009-09-29 Asm America, Inc. Polymer coating for vapor deposition tool
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US20090274887A1 (en) 2008-05-02 2009-11-05 Millward Dan B Graphoepitaxial Self-Assembly of Arrays of Downward Facing Half-Cylinders
US20100015756A1 (en) 2008-07-16 2010-01-21 Applied Materials, Inc. Hybrid heterojunction solar cell fabrication using a doping layer mask
US20100147396A1 (en) 2008-12-15 2010-06-17 Asm Japan K.K. Multiple-Substrate Transfer Apparatus and Multiple-Substrate Processing Apparatus
US7754621B2 (en) 2000-04-14 2010-07-13 Asm International N.V. Process for producing zirconium oxide thin films
US20100248473A1 (en) 2009-03-31 2010-09-30 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
US20100270626A1 (en) 2009-04-27 2010-10-28 Raisanen Petri I Atomic layer deposition of hafnium lanthanum oxides
US20110053800A1 (en) 2009-09-01 2011-03-03 Sungkyunkwan University Foundation For Corporate Collaboration Method of manufacturing patterned subtrate for culturing cells, patterned subtrate for culturing cells, patterning method of culturing cells, and patterned cell chip
US7910177B2 (en) 2001-02-13 2011-03-22 Mosaid Technologies Incorporated Sequential pulse deposition
US7914847B2 (en) 2003-05-09 2011-03-29 Asm America, Inc. Reactor surface passivation through chemical deactivation
US7927942B2 (en) 2008-12-19 2011-04-19 Asm International N.V. Selective silicide process
US20110124192A1 (en) 2006-04-11 2011-05-26 Seshadri Ganguli Process for forming cobalt-containing materials
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US20110221061A1 (en) 2008-12-01 2011-09-15 Shiva Prakash Anode for an organic electronic device
JP2011187583A (en) 2010-03-05 2011-09-22 Tokyo Electron Ltd Method of manufacturing semiconductor device
WO2011156705A2 (en) 2010-06-10 2011-12-15 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20110311726A1 (en) 2010-06-18 2011-12-22 Cambridge Nanotech Inc. Method and apparatus for precursor delivery
US20120032311A1 (en) 2010-08-09 2012-02-09 International Business Machines Corporation Multi component dielectric layer
US20120046421A1 (en) 2010-08-17 2012-02-23 Uchicago Argonne, Llc Ordered Nanoscale Domains by Infiltration of Block Copolymers
US20120088369A1 (en) 2010-10-06 2012-04-12 Applied Materials, Inc. Atomic Layer Deposition Of Photoresist Materials And Hard Mask Precursors
US20120189868A1 (en) 2009-07-31 2012-07-26 Akzo Nobel Chemicals International B.V. Process for the preparation of a coated substrate, coated substrate, and use thereof
US20120219824A1 (en) 2011-02-28 2012-08-30 Uchicago Argonne Llc Atomic layer deposition of super-conducting niobium silicide
US20120264291A1 (en) 2001-07-25 2012-10-18 Applied Materials, Inc. Process for forming cobalt-containing materials
US8293658B2 (en) 2010-02-17 2012-10-23 Asm America, Inc. Reactive site deactivation against vapor deposition
US20120269970A1 (en) 2011-03-29 2012-10-25 Tokyo Electron Limited Cleaning method and film depositing method
KR20120120902A (en) 2011-04-22 2012-11-02 에이에스엠 인터내셔널 엔.브이. Metal silicide, metal germanide, methods for making the same and nickel thin film depositions
US20130005133A1 (en) 2011-06-28 2013-01-03 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
US20130089983A1 (en) 2010-07-01 2013-04-11 Tokyo Electron Limited Method of manufacturing semiconductor device
US20130095664A1 (en) 2011-10-12 2013-04-18 ASM International. N.V. Atomic layer deposition of antimony oxide films
US8425739B1 (en) 2008-09-30 2013-04-23 Stion Corporation In chamber sodium doping process and system for large scale cigs based thin film photovoltaic materials
US20130115768A1 (en) 2008-12-19 2013-05-09 Viljami J. Pore Methods for depositing nickel films and for making nickel silicide and nickel germanide
US20130146881A1 (en) 2000-08-10 2013-06-13 Semiconductor Energy Laboratory Co., Ltd. Area sensor and display apparatus provided with an area sensor
US20130196502A1 (en) 2011-12-09 2013-08-01 ASM International. N.V. Selective formation of metallic films on metallic surfaces
US20130203267A1 (en) 2012-02-06 2013-08-08 Asm Ip Holding B.V. Multiple vapor sources for vapor deposition
US20130280919A1 (en) 2010-11-19 2013-10-24 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus
US20130284094A1 (en) 2009-12-15 2013-10-31 Primestar Solar, Inc. Modular System for Continuous Deposition of a Thin Film Layer on a Substrate
US20130316080A1 (en) 2012-05-28 2013-11-28 Tokyo Electron Limited Film forming method
US20140001572A1 (en) 2012-06-29 2014-01-02 Mark T. Bohr Through gate fin isolation
US20140024200A1 (en) 2012-07-20 2014-01-23 Tokyo Electron Limited Film deposition apparatus and film deposition method
US20140091308A1 (en) 2012-09-28 2014-04-03 Sansaptak DASGUPTA Self-aligned structures and methods for asymmetric gan transistors & enhancement mode operation
US20140120738A1 (en) 2012-11-01 2014-05-01 Asm Ip Holding B.V. Method of depositing thin film
JP2014093331A (en) 2012-10-31 2014-05-19 Tokyo Electron Ltd Deposition method of polymerized film, environment maintenance method of deposition device, deposition device and manufacturing method of electronic product
US20140152383A1 (en) 2012-11-30 2014-06-05 Dmitri E. Nikonov Integrated circuits and systems and methods for producing the same
US20140190409A1 (en) 2009-07-22 2014-07-10 Tokyo Electron Limited Device and method for forming film
US20140193598A1 (en) 2011-08-10 2014-07-10 3M Innovative Properties Company Multilayer Adhesive Film, in Particular for Bonding Optical Sensors
US8778815B2 (en) 2012-05-28 2014-07-15 Tokyo Electron Limited Film forming method
US20140205766A1 (en) 2013-01-24 2014-07-24 Jennifer Lynn Lyon Surface nanoreplication using polymer nanomasks
US20140209022A1 (en) 2013-01-31 2014-07-31 Tokyo Electron Limited Raw material gas supply device, film forming apparatus, raw material gas supply method, and non-transitory storage medium
US20140227461A1 (en) 2013-02-14 2014-08-14 Dillard University Multiple Beam Pulsed Laser Deposition Of Composite Films
US20140273527A1 (en) 2013-03-13 2014-09-18 Asm Ip Holding B.V. Methods for forming silicon nitride thin films
US20140273290A1 (en) 2013-03-15 2014-09-18 Tokyo Electron Limited Solvent anneal processing for directed-self assembly applications
WO2014156782A1 (en) 2013-03-28 2014-10-02 東京エレクトロン株式会社 Method for manufacturing hollow structure
US8890264B2 (en) 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
WO2014209390A1 (en) 2013-06-28 2014-12-31 Intel Corporation Selective epitaxially grown iii-v materials based devices
US20150004806A1 (en) 2006-11-01 2015-01-01 Lam Research Corporation Low-k oxide deposition by hydrolysis and condensation
US20150011032A1 (en) 2010-02-17 2015-01-08 Japan Display Inc. Method for fabricating a liquid crystal display device comprising an alignment film that includes a photolytic polymer and a non-photolytic polymer
US20150037972A1 (en) 2013-07-30 2015-02-05 Lam Research Corporation Methods and apparatuses for atomic layer cleaning of contacts and vias
US20150064931A1 (en) 2013-09-02 2015-03-05 Tokyo Electron Limited Film formation method and film formation apparatus
US8980418B2 (en) 2011-03-24 2015-03-17 Uchicago Argonne, Llc Sequential infiltration synthesis for advanced lithography
US20150087158A1 (en) 2012-04-27 2015-03-26 Tokyo Electron Limited Method for depositing a film and film deposition apparatus
US8993404B2 (en) 2013-01-23 2015-03-31 Intel Corporation Metal-insulator-metal capacitor formation techniques
US20150093890A1 (en) 2013-09-27 2015-04-02 James M. Blackwell Cobalt metal precursors
WO2015047345A1 (en) 2013-09-27 2015-04-02 Intel Corporation Forming layers of materials over small regions by selective chemical reaction including limiting encroachment of the layers over adjacent regions
US20150097292A1 (en) 2005-06-03 2015-04-09 Intel Corporation Interconnects having sealing structures to enable selective metal capping layers
US20150118863A1 (en) 2013-10-25 2015-04-30 Lam Research Corporation Methods and apparatus for forming flowable dielectric films having low porosity
US20150162214A1 (en) 2013-12-09 2015-06-11 Applied Materials, Inc. Methods Of Selective Layer Deposition
US20150170961A1 (en) 2013-12-18 2015-06-18 Patricio E. Romero Selective area deposition of metal films by atomic layer deposition (ald) and chemical vapor deposition (cvd)
US20150179798A1 (en) 2013-12-24 2015-06-25 Scott B. Clendenning Conformal thin film deposition of electropositive metal alloy films
WO2015094305A1 (en) 2013-12-19 2015-06-25 Intel Corporation Self-aligned gate edge and local interconnect and method to fabricate same
US9067958B2 (en) 2013-10-14 2015-06-30 Intel Corporation Scalable and high yield synthesis of transition metal bis-diazabutadienes
US20150217330A1 (en) 2014-02-04 2015-08-06 Asm Ip Holding B.V. Selective deposition of metals, metal oxides, and dielectrics
US20150240121A1 (en) 2014-02-27 2015-08-27 Tokyo Electron Limited Method for Improving Chemical Resistance of Polymerized Film, Polymerized Film Forming Method, Film Forming Apparatus, and Electronic Product Manufacturing Method
WO2015147858A1 (en) 2014-03-28 2015-10-01 Intel Corporation Selective epitaxially grown iii-v materials based devices
WO2015147843A1 (en) 2014-03-27 2015-10-01 Intel Corporation Precursor and process design for photo-assisted metal atomic layer deposition (ald) and chemical vapor deposition (cvd)
US20150299848A1 (en) 2014-04-16 2015-10-22 Asm Ip Holding B.V. Dual selective deposition
US20150371866A1 (en) 2014-06-19 2015-12-24 Applied Materials, Inc. Highly selective doped oxide removal method
US20150376211A1 (en) 2015-03-30 2015-12-31 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Si-CONTAINING FILM FORMING PRECURSORS AND METHODS OF USING THE SAME
US20160075884A1 (en) 2014-02-10 2016-03-17 National Tsing Hua University Inorganic-organic Hybrid Oxide Polymer and Manufacturing Method thereof
US20160186004A1 (en) 2014-12-30 2016-06-30 Rohm And Haas Electronic Materials Llc Copolymer formulation for directed self assembly, methods of manufacture thereof and articles comprising the same
US20160222504A1 (en) 2015-02-03 2016-08-04 Asm Ip Holding B.V. Selective deposition
US20160247695A1 (en) 2015-02-23 2016-08-25 Asm Ip Holding B.V. Removal of surface passivation
US20160293398A1 (en) 2015-04-03 2016-10-06 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US20170040164A1 (en) 2015-08-05 2017-02-09 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US20170037513A1 (en) 2015-08-03 2017-02-09 Asm Ip Holding B.V. Selective deposition on metal or metallic surfaces relative to dielectric surfaces
US20170100743A1 (en) 2015-10-09 2017-04-13 Asm Ip Holding B.V. Vapor phase deposition of organic films
US20170100742A1 (en) 2015-10-09 2017-04-13 Asm Ip Holding B.V. Vapor phase deposition of organic films
US20170154806A1 (en) 2015-08-05 2017-06-01 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US9803277B1 (en) 2016-06-08 2017-10-31 Asm Ip Holding B.V. Reaction chamber passivation and selective deposition of metallic films
US20170323776A1 (en) 2016-05-05 2017-11-09 Asm Ip Holding B.V. Selective deposition using hydrophobic precursors
US9911595B1 (en) 2017-03-17 2018-03-06 Lam Research Corporation Selective growth of silicon nitride

Patent Citations (172)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948755A (en) 1987-10-08 1990-08-14 Standard Microsystems Corporation Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
US4863879A (en) 1987-12-16 1989-09-05 Ford Microelectronics, Inc. Method of manufacturing self-aligned GaAs MESFET
EP0469456A1 (en) 1990-07-30 1992-02-05 Mitsubishi Gas Chemical Company, Inc. Process for producing copper-clad laminate
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
US20010025205A1 (en) 1994-11-14 2001-09-27 Applied Materials, Inc. Construction of a film on a semiconductor wafer
US5633036A (en) 1995-04-21 1997-05-27 The Board Of Trustees Of The University Of Illinois Selective low temperature chemical vapor deposition of titanium disilicide onto silicon regions
US5925494A (en) 1996-02-16 1999-07-20 Massachusetts Institute Of Technology Vapor deposition of polymer films for photolithography
US20080066680A1 (en) 1996-06-21 2008-03-20 Asm America, Inc. Sequential chemical vapor deposition
EP0880168A2 (en) 1997-05-22 1998-11-25 Sharp Corporation System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides
US20020047144A1 (en) 1997-05-22 2002-04-25 Tue Nguyen Integrated circuit prepared by selectively cleaning copper substrates, in-situ, to remove copper oxides
US5869135A (en) 1997-10-03 1999-02-09 Massachusetts Institute Of Technology Selective chemical vapor deposition of polymers
US20080072819A1 (en) 1998-09-11 2008-03-27 Asm International N.V. Metal oxide films
US6958174B1 (en) 1999-03-15 2005-10-25 Regents Of The University Of Colorado Solid material comprising a thin metal film on its surface and methods for producing the same
US6046108A (en) 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US20010019803A1 (en) 1999-12-06 2001-09-06 The Regents Of The University Of California Mitigation of substrate defects in reflective reticles using sequential coating and annealing
US20030027431A1 (en) 1999-12-22 2003-02-06 Ofer Sneh Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition
US7754621B2 (en) 2000-04-14 2010-07-13 Asm International N.V. Process for producing zirconium oxide thin films
US8536058B2 (en) 2000-05-15 2013-09-17 Asm International N.V. Method of growing electrical conductors
US6482740B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH
US7955979B2 (en) 2000-05-15 2011-06-07 Asm International N.V. Method of growing electrical conductors
US6921712B2 (en) 2000-05-15 2005-07-26 Asm International Nv Process for producing integrated circuits including reduction using gaseous organic compounds
US7241677B2 (en) 2000-05-15 2007-07-10 Asm International N.V. Process for producing integrated circuits including reduction using gaseous organic compounds
US7494927B2 (en) 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
US6759325B2 (en) 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US6887795B2 (en) 2000-05-15 2005-05-03 Asm International N.V. Method of growing electrical conductors
US6878628B2 (en) 2000-05-15 2005-04-12 Asm International Nv In situ reduction of copper oxide prior to silicon carbide deposition
US20030143839A1 (en) 2000-05-15 2003-07-31 Ivo Raaijmakers Sealing porous structures
US6679951B2 (en) 2000-05-15 2004-01-20 Asm Intenational N.V. Metal anneal with oxidation prevention
US20050136604A1 (en) 2000-08-10 2005-06-23 Amir Al-Bayati Semiconductor on insulator vertical transistor fabrication and doping process
US20130146881A1 (en) 2000-08-10 2013-06-13 Semiconductor Energy Laboratory Co., Ltd. Area sensor and display apparatus provided with an area sensor
EP1340269B1 (en) 2000-11-30 2009-02-25 Asm International N.V. Thin films for magnetic devices
JP4333900B2 (en) 2000-11-30 2009-09-16 エーエスエム インターナショナル エヌ.ヴェー.Asm International N.V. A magnetic memory cell, a method of manufacturing the magnetic structure and the magnetic element, and method for growing a magnetic structure for the metal layer
KR100869326B1 (en) 2000-11-30 2008-11-18 에이에스엠 인터내셔널 엔.브이. thin films for magnetic devices
US7220669B2 (en) 2000-11-30 2007-05-22 Asm International N.V. Thin films for magnetic device
WO2002045167A3 (en) 2000-11-30 2003-05-30 Asm Inc Thin films for magnetic devices
US20020068458A1 (en) 2000-12-06 2002-06-06 Chiang Tony P. Method for integrated in-situ cleaning and susequent atomic layer deposition within a single processing chamber
US20020090777A1 (en) 2001-01-05 2002-07-11 Leonard Forbes Methods of forming capacitor structures, and capacitor structures
US7910177B2 (en) 2001-02-13 2011-03-22 Mosaid Technologies Incorporated Sequential pulse deposition
US20120264291A1 (en) 2001-07-25 2012-10-18 Applied Materials, Inc. Process for forming cobalt-containing materials
US20090035949A1 (en) 2001-08-03 2009-02-05 Jaakko Niinisto Method of depositing rare earth oxide thin films
US20030066487A1 (en) 2001-09-28 2003-04-10 Nobumasa Suzuki Plasma processing system and surface processing method
US20030181035A1 (en) 2001-12-21 2003-09-25 Applied Materials, Inc. Selective deposition of abarrier layer on a metal film
US6586330B1 (en) 2002-05-07 2003-07-01 Tokyo Electron Limited Method for depositing conformal nitrified tantalum silicide films by thermal CVD
US20060141155A1 (en) 2002-11-15 2006-06-29 Havard University Atomic layer deposition using metal amidinates
KR20040056026A (en) 2002-12-23 2004-06-30 주식회사 하이닉스반도체 Method of forming a capping layer
US20040219746A1 (en) 2003-04-29 2004-11-04 Micron Technology, Inc. Systems and methods for forming metal oxide layers
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7914847B2 (en) 2003-05-09 2011-03-29 Asm America, Inc. Reactor surface passivation through chemical deactivation
US7799135B2 (en) 2003-05-09 2010-09-21 Asm America, Inc. Reactor surface passivation through chemical deactivation
US7118779B2 (en) 2003-05-09 2006-10-10 Asm America, Inc. Reactor surface passivation through chemical deactivation
US6811448B1 (en) 2003-07-15 2004-11-02 Advanced Micro Devices, Inc. Pre-cleaning for silicidation in an SMOS process
US7067407B2 (en) 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US7323411B1 (en) 2003-09-26 2008-01-29 Cypress Semiconductor Corporation Method of selective tungsten deposition on a silicon surface
US7405143B2 (en) 2004-03-25 2008-07-29 Asm International N.V. Method for fabricating a seed layer
US20050223989A1 (en) 2004-03-31 2005-10-13 Lee Chung J System for forming composite polymer dielectric film
US20060019493A1 (en) 2004-07-15 2006-01-26 Li Wei M Methods of metallization for microelectronic devices utilizing metal oxide
US20060047132A1 (en) 2004-09-02 2006-03-02 Rohm And Haas Electronic Materials Llc Method
US20060292845A1 (en) 2004-09-17 2006-12-28 Chiang Tony P Processing substrates using site-isolated processing
US7476618B2 (en) 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US20060199399A1 (en) 2005-02-22 2006-09-07 Muscat Anthony J Surface manipulation and selective deposition processes using adsorbed halogen atoms
US20060226409A1 (en) 2005-04-06 2006-10-12 International Business Machines Corporation Structure for confining the switching current in phase memory (PCM) cells
US7425350B2 (en) 2005-04-29 2008-09-16 Asm Japan K.K. Apparatus, precursors and deposition methods for silicon-containing materials
US7084060B1 (en) 2005-05-04 2006-08-01 International Business Machines Corporation Forming capping layer over metal wire structure using selective atomic layer deposition
US20150097292A1 (en) 2005-06-03 2015-04-09 Intel Corporation Interconnects having sealing structures to enable selective metal capping layers
US20070063317A1 (en) 2005-06-24 2007-03-22 Samsung Electronics Co., Ltd. Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device
US20070099422A1 (en) 2005-10-28 2007-05-03 Kapila Wijekoon Process for electroless copper deposition
US20080282970A1 (en) 2005-11-16 2008-11-20 Peter Nicholas Heys Cyclopentadienyl Type Hafnium and Zirconium Precursors and Use Thereof in Atomic Layer Deposition
US7595271B2 (en) 2005-12-01 2009-09-29 Asm America, Inc. Polymer coating for vapor deposition tool
US20110124192A1 (en) 2006-04-11 2011-05-26 Seshadri Ganguli Process for forming cobalt-containing materials
US20070241390A1 (en) 2006-04-14 2007-10-18 Masayuki Tanaka Semiconductor device and method for manufacturing the same
US20090203222A1 (en) 2006-06-02 2009-08-13 Christian Dussarrat Method of forming dielectric films, new precursors and their use in semiconductor manufacturing
US20090311879A1 (en) 2006-06-02 2009-12-17 L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Method of forming high-k dielectric films based on novel titanium, zirconium, and hafnium precursors and their use for semiconductor manufacturing
US20150004806A1 (en) 2006-11-01 2015-01-01 Lam Research Corporation Low-k oxide deposition by hydrolysis and condensation
US20080179741A1 (en) 2007-01-31 2008-07-31 Christof Streck Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride
US20080241575A1 (en) 2007-03-28 2008-10-02 Lavoie Adrein R Selective aluminum doping of copper interconnects and structures formed thereby
US20090081385A1 (en) 2007-09-14 2009-03-26 Peter Nicholas Heys Methods of atomic layer deposition using hafnium and zirconium-based precursors
US20090071505A1 (en) 2007-09-19 2009-03-19 Hitachi-Kokusai Electric Inc. Cleaning method and substrate processing apparatus
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US20090274887A1 (en) 2008-05-02 2009-11-05 Millward Dan B Graphoepitaxial Self-Assembly of Arrays of Downward Facing Half-Cylinders
US20100015756A1 (en) 2008-07-16 2010-01-21 Applied Materials, Inc. Hybrid heterojunction solar cell fabrication using a doping layer mask
US8425739B1 (en) 2008-09-30 2013-04-23 Stion Corporation In chamber sodium doping process and system for large scale cigs based thin film photovoltaic materials
US20110221061A1 (en) 2008-12-01 2011-09-15 Shiva Prakash Anode for an organic electronic device
US20100147396A1 (en) 2008-12-15 2010-06-17 Asm Japan K.K. Multiple-Substrate Transfer Apparatus and Multiple-Substrate Processing Apparatus
US7927942B2 (en) 2008-12-19 2011-04-19 Asm International N.V. Selective silicide process
US9129897B2 (en) 2008-12-19 2015-09-08 Asm International N.V. Metal silicide, metal germanide, methods for making the same
US20130115768A1 (en) 2008-12-19 2013-05-09 Viljami J. Pore Methods for depositing nickel films and for making nickel silicide and nickel germanide
US8293597B2 (en) 2008-12-19 2012-10-23 Asm International N.V. Selective silicide process
US20100248473A1 (en) 2009-03-31 2010-09-30 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
US20100270626A1 (en) 2009-04-27 2010-10-28 Raisanen Petri I Atomic layer deposition of hafnium lanthanum oxides
US20140190409A1 (en) 2009-07-22 2014-07-10 Tokyo Electron Limited Device and method for forming film
US20120189868A1 (en) 2009-07-31 2012-07-26 Akzo Nobel Chemicals International B.V. Process for the preparation of a coated substrate, coated substrate, and use thereof
US20110053800A1 (en) 2009-09-01 2011-03-03 Sungkyunkwan University Foundation For Corporate Collaboration Method of manufacturing patterned subtrate for culturing cells, patterned subtrate for culturing cells, patterning method of culturing cells, and patterned cell chip
US20130284094A1 (en) 2009-12-15 2013-10-31 Primestar Solar, Inc. Modular System for Continuous Deposition of a Thin Film Layer on a Substrate
US20150011032A1 (en) 2010-02-17 2015-01-08 Japan Display Inc. Method for fabricating a liquid crystal display device comprising an alignment film that includes a photolytic polymer and a non-photolytic polymer
US8293658B2 (en) 2010-02-17 2012-10-23 Asm America, Inc. Reactive site deactivation against vapor deposition
JP2011187583A (en) 2010-03-05 2011-09-22 Tokyo Electron Ltd Method of manufacturing semiconductor device
US9257303B2 (en) * 2010-06-10 2016-02-09 Asm International N.V. Selective formation of metallic films on metallic surfaces
US8956971B2 (en) * 2010-06-10 2015-02-17 Asm International N.V. Selective formation of metallic films on metallic surfaces
US9679808B2 (en) * 2010-06-10 2017-06-13 Asm International N.V. Selective formation of metallic films on metallic surfaces
WO2011156705A2 (en) 2010-06-10 2011-12-15 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20130189837A1 (en) 2010-06-10 2013-07-25 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20160276208A1 (en) 2010-06-10 2016-09-22 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20110311726A1 (en) 2010-06-18 2011-12-22 Cambridge Nanotech Inc. Method and apparatus for precursor delivery
US20130089983A1 (en) 2010-07-01 2013-04-11 Tokyo Electron Limited Method of manufacturing semiconductor device
US20120032311A1 (en) 2010-08-09 2012-02-09 International Business Machines Corporation Multi component dielectric layer
US20120046421A1 (en) 2010-08-17 2012-02-23 Uchicago Argonne, Llc Ordered Nanoscale Domains by Infiltration of Block Copolymers
US20120088369A1 (en) 2010-10-06 2012-04-12 Applied Materials, Inc. Atomic Layer Deposition Of Photoresist Materials And Hard Mask Precursors
US20130280919A1 (en) 2010-11-19 2013-10-24 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus
US20120219824A1 (en) 2011-02-28 2012-08-30 Uchicago Argonne Llc Atomic layer deposition of super-conducting niobium silicide
US8980418B2 (en) 2011-03-24 2015-03-17 Uchicago Argonne, Llc Sequential infiltration synthesis for advanced lithography
US20120269970A1 (en) 2011-03-29 2012-10-25 Tokyo Electron Limited Cleaning method and film depositing method
KR20120120902A (en) 2011-04-22 2012-11-02 에이에스엠 인터내셔널 엔.브이. Metal silicide, metal germanide, methods for making the same and nickel thin film depositions
US20130005133A1 (en) 2011-06-28 2013-01-03 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
US20140193598A1 (en) 2011-08-10 2014-07-10 3M Innovative Properties Company Multilayer Adhesive Film, in Particular for Bonding Optical Sensors
US20130095664A1 (en) 2011-10-12 2013-04-18 ASM International. N.V. Atomic layer deposition of antimony oxide films
US9112003B2 (en) 2011-12-09 2015-08-18 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20170069527A1 (en) 2011-12-09 2017-03-09 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20130196502A1 (en) 2011-12-09 2013-08-01 ASM International. N.V. Selective formation of metallic films on metallic surfaces
US9502289B2 (en) 2011-12-09 2016-11-22 Asm International N.V. Selective formation of metallic films on metallic surfaces
US20130203267A1 (en) 2012-02-06 2013-08-08 Asm Ip Holding B.V. Multiple vapor sources for vapor deposition
US20150087158A1 (en) 2012-04-27 2015-03-26 Tokyo Electron Limited Method for depositing a film and film deposition apparatus
US8778815B2 (en) 2012-05-28 2014-07-15 Tokyo Electron Limited Film forming method
US20130316080A1 (en) 2012-05-28 2013-11-28 Tokyo Electron Limited Film forming method
US20140001572A1 (en) 2012-06-29 2014-01-02 Mark T. Bohr Through gate fin isolation
US20140024200A1 (en) 2012-07-20 2014-01-23 Tokyo Electron Limited Film deposition apparatus and film deposition method
US8890264B2 (en) 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US20140091308A1 (en) 2012-09-28 2014-04-03 Sansaptak DASGUPTA Self-aligned structures and methods for asymmetric gan transistors & enhancement mode operation
JP2014093331A (en) 2012-10-31 2014-05-19 Tokyo Electron Ltd Deposition method of polymerized film, environment maintenance method of deposition device, deposition device and manufacturing method of electronic product
US20140120738A1 (en) 2012-11-01 2014-05-01 Asm Ip Holding B.V. Method of depositing thin film
US20140152383A1 (en) 2012-11-30 2014-06-05 Dmitri E. Nikonov Integrated circuits and systems and methods for producing the same
US8993404B2 (en) 2013-01-23 2015-03-31 Intel Corporation Metal-insulator-metal capacitor formation techniques
US20140205766A1 (en) 2013-01-24 2014-07-24 Jennifer Lynn Lyon Surface nanoreplication using polymer nanomasks
US20140209022A1 (en) 2013-01-31 2014-07-31 Tokyo Electron Limited Raw material gas supply device, film forming apparatus, raw material gas supply method, and non-transitory storage medium
US20140227461A1 (en) 2013-02-14 2014-08-14 Dillard University Multiple Beam Pulsed Laser Deposition Of Composite Films
US20140273527A1 (en) 2013-03-13 2014-09-18 Asm Ip Holding B.V. Methods for forming silicon nitride thin films
US20140273290A1 (en) 2013-03-15 2014-09-18 Tokyo Electron Limited Solvent anneal processing for directed-self assembly applications
WO2014156782A1 (en) 2013-03-28 2014-10-02 東京エレクトロン株式会社 Method for manufacturing hollow structure
WO2014209390A1 (en) 2013-06-28 2014-12-31 Intel Corporation Selective epitaxially grown iii-v materials based devices
US20150037972A1 (en) 2013-07-30 2015-02-05 Lam Research Corporation Methods and apparatuses for atomic layer cleaning of contacts and vias
US20150064931A1 (en) 2013-09-02 2015-03-05 Tokyo Electron Limited Film formation method and film formation apparatus
WO2015047345A1 (en) 2013-09-27 2015-04-02 Intel Corporation Forming layers of materials over small regions by selective chemical reaction including limiting encroachment of the layers over adjacent regions
US20150093890A1 (en) 2013-09-27 2015-04-02 James M. Blackwell Cobalt metal precursors
US9067958B2 (en) 2013-10-14 2015-06-30 Intel Corporation Scalable and high yield synthesis of transition metal bis-diazabutadienes
US20150118863A1 (en) 2013-10-25 2015-04-30 Lam Research Corporation Methods and apparatus for forming flowable dielectric films having low porosity
US20150162214A1 (en) 2013-12-09 2015-06-11 Applied Materials, Inc. Methods Of Selective Layer Deposition
US20150170961A1 (en) 2013-12-18 2015-06-18 Patricio E. Romero Selective area deposition of metal films by atomic layer deposition (ald) and chemical vapor deposition (cvd)
US9236292B2 (en) 2013-12-18 2016-01-12 Intel Corporation Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
WO2015094305A1 (en) 2013-12-19 2015-06-25 Intel Corporation Self-aligned gate edge and local interconnect and method to fabricate same
US20150179798A1 (en) 2013-12-24 2015-06-25 Scott B. Clendenning Conformal thin film deposition of electropositive metal alloy films
US20150217330A1 (en) 2014-02-04 2015-08-06 Asm Ip Holding B.V. Selective deposition of metals, metal oxides, and dielectrics
US20160075884A1 (en) 2014-02-10 2016-03-17 National Tsing Hua University Inorganic-organic Hybrid Oxide Polymer and Manufacturing Method thereof
US20150240121A1 (en) 2014-02-27 2015-08-27 Tokyo Electron Limited Method for Improving Chemical Resistance of Polymerized Film, Polymerized Film Forming Method, Film Forming Apparatus, and Electronic Product Manufacturing Method
WO2015147843A1 (en) 2014-03-27 2015-10-01 Intel Corporation Precursor and process design for photo-assisted metal atomic layer deposition (ald) and chemical vapor deposition (cvd)
US20170058401A1 (en) 2014-03-27 2017-03-02 Intel Corporation Precursor and Process Design for Photo-Assisted Metal Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD)
WO2015147858A1 (en) 2014-03-28 2015-10-01 Intel Corporation Selective epitaxially grown iii-v materials based devices
US20150299848A1 (en) 2014-04-16 2015-10-22 Asm Ip Holding B.V. Dual selective deposition
US20150371866A1 (en) 2014-06-19 2015-12-24 Applied Materials, Inc. Highly selective doped oxide removal method
US20160186004A1 (en) 2014-12-30 2016-06-30 Rohm And Haas Electronic Materials Llc Copolymer formulation for directed self assembly, methods of manufacture thereof and articles comprising the same
US20160222504A1 (en) 2015-02-03 2016-08-04 Asm Ip Holding B.V. Selective deposition
US9490145B2 (en) 2015-02-23 2016-11-08 Asm Ip Holding B.V. Removal of surface passivation
US20160247695A1 (en) 2015-02-23 2016-08-25 Asm Ip Holding B.V. Removal of surface passivation
US20150376211A1 (en) 2015-03-30 2015-12-31 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Si-CONTAINING FILM FORMING PRECURSORS AND METHODS OF USING THE SAME
US20160293398A1 (en) 2015-04-03 2016-10-06 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US20170037513A1 (en) 2015-08-03 2017-02-09 Asm Ip Holding B.V. Selective deposition on metal or metallic surfaces relative to dielectric surfaces
US20170040164A1 (en) 2015-08-05 2017-02-09 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US20170154806A1 (en) 2015-08-05 2017-06-01 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US20170100742A1 (en) 2015-10-09 2017-04-13 Asm Ip Holding B.V. Vapor phase deposition of organic films
US20170100743A1 (en) 2015-10-09 2017-04-13 Asm Ip Holding B.V. Vapor phase deposition of organic films
US20170323776A1 (en) 2016-05-05 2017-11-09 Asm Ip Holding B.V. Selective deposition using hydrophobic precursors
US9803277B1 (en) 2016-06-08 2017-10-31 Asm Ip Holding B.V. Reaction chamber passivation and selective deposition of metallic films
US9911595B1 (en) 2017-03-17 2018-03-06 Lam Research Corporation Selective growth of silicon nitride

Non-Patent Citations (60)

* Cited by examiner, † Cited by third party
Title
"Tungsten and Tungsten Silicide Chemical Vapor Deposition", TimeDomain CVD, Inc., retrieved from link: http://www.timedomaincvd.com/CVD_Fundamentals/films/W_WSI.html, Last modified Jul. 11, 2008.
Au et al., "Selective Chemical Vapor Deposition of Manganese Self-Aligned Capping Layer for Cu Interconnections in Microelectronics", Journal of the Electrochemical Society, vol. 157, No. 6, 2010, pp. D341-D345.
Bernal-Ramos, et al., "Atomic Layer Deposition of Cobalt Silicide Thin Films Studied by in Situ Infrared Spectroscopy", Chem. Mater. 2015, 27, pp. 4943-4949.
Bouteville et al., "Selective R.T.L.P.C.V.D. of Tungsten by Silane Reduction on Patterned PPQ/Si Wafers" Journal De Physique IV, Colloque C2, suppl. au Journal de Physique II, vol. 1, Sep. 1991, pp. C2-857-C2-864.
Burton, B.B. et al., "Atomic Layer Deposition of MgO Using Bis(ethylcyclopentadienyl)magnesium and H2O". J. Phys. Chem. C, 2009, 113, 1939-1946.
Burton, B.B., et al. "SiO2 Atomic Layer Deposition Using Tris(dimethylamino)silane and Hydrogen Peroxide Studied by in Situ Transmission FTIR Spectroscopy". J. Phys. Chem. C, 2009, 113, 8249-8257.
Carlsson, J., "Precursor Design for Chemical Vapour Deposition", Acta Chemica Scandinavica, vol. 45, 1991, pp. 864-869.
Chang et al, "Influences of damage and contamination from reactive ion etching on selective tungsten deposition in a low-pressure chemical-vapor-deposition reactor", J. Appl. Phys., vol. 80, No. 5, Sep. 1, 1996, pp. 3056-3061.
Chen et al., Highly Stable Monolayer Resists for Atomic Layer Deposition on Germanium and Silicon, Chem. Matter, vol. 18, No. 16, pp. 3733-3741, 2006.
Coclite, et al.; 25th Anniversary Article: CVD Polymers: A New Paradigm for Surface Modification and Device Fabrication; Advanced Materials; Oct. 2013; 25; pp. 5392-5423.
Elam et al., "Kinetics of the WF6 and Si2H6 surface reactions during tungsten atomic layer deposition", Surface Science, vol. 479, 2001, pp. 121-135.
Elam et al., "Nucleation and growth during tungsten atomic layer deposition on SiO2 surfaces", Thin Solid Films, vol. 386, 2001 pp. 41-52.
Fabreguette et al., Quartz crystal microbalance study of tungsten atomic layer deposition using WF6 and Si2H6, Thin Solid Films, vol. 488, 2005, pp. 103-110.
Farr, Isaac Vincent; Synthesis and Characterization of Novel Polyimide Gas Separation Membrane Material Systems, Chapter 2; Virginia Tech Chemistry PhD Dissertation; URN# etd-080999-123034; Jul. 26, 1999.
File History of U.S. Appl. No. 13/702,992, filed Mar. 26, 2013.
File History of U.S. Appl. No. 13/708,863, filed Dec. 7, 2012.
File History of U.S. Appl. No. 15/177,195, filed Jun. 8, 2016.
George, Steven M.; Atomic Layer Deposition: An Overview; Chem. Rev. 2010, 110, pp. 111-131; Steven M.; Atomic Layer Deposition: An Overview; Chem. Rev. 2010, 110, pp. 111-131; Feb. 12, 2009.
Ghosal et al., Controlling Atomic Layer Deposition of TiO2 in Aerogels through Surface Functionalization, Chem. Matter, vol. 21, pp. 1989-1992, 2009.
Grubbs et al., "Nucleation and growth during the atomic layer deposition of W on Al2O3 and Al2O3 on W", Thin Solid Films, vol. 467, 2004, pp. 16-27.
Hymes et al., "Surface cleaning of copper by thermal and plasma treatment in reducing and inert ambients", J. Vac. Sci. Technol. B, vol. 16, No. 3, May/Jun. 1998, pp. 1107-1109.
International Search Report and Written Opinion dated Feb. 17, 2012 in Application No. PCT/US2011/039970, filed Jun. 10, 2011.
King, Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects, ECS Journal of Solid State Science and Technology, vol. 4, Issue 1, pp. N3029-N3047, 2015.
Klaus et al., "Atomic layer deposition of tungsten using sequential surface chemistry with a sacrificial stripping reaction", Thin Solid Films, vol. 360, 2000, pp. 145-153.
Klaus et al., "Atomically controlled growth of tungsten and tungsten nitride using sequential surface reactions", Applied Surface Science 162-163, 2000, pp. 479-491.
Lee et al., Area-Selective Atomic Layor Deposition Using Self-Assembled Monolayer and Scanning Probe Lithography, Journal of the Electrochemical Society, vol. 156, Issue 9, pp. G125-G128, 2009.
Lei et al., "Real-time observation and opitimization of tungsten atomic layer deposition process cycle", J. Vac. Sci. Technol. B, vol. 24, No. 2, Mar./Apr. 2006, pp. 780-789.
Lemonds, A.M., "Atomic layer deposition of TaSix thin films on SiO2 using TaF5 and Si2H6", Thin Solid Films, 488, 2005 pp. 9-14.
Lemonds, Andrew Michael, "Atomic Layer Deposition and Properties of Refractory Transition Metal-Based Copper-Diffusion Barriers for ULSI Interconnect", The University of Texas at Austin, 2003, pp. 1-197.
Leusink et al., "Growth kinetics and inhibition of growth of chemical vapor deposited thin tungsten films on silicon from tungsten hexafluoride", J. Appl. Phys., vol. 72, No. 2, Jul. 15, 1992, pp. 490-498.
Liang, Xuehai, et al., "Growth of Ge Nanofilms Using Electrochemical Atomic Layer Deposition, with a "Bait and Switch" Surface-Limited Reaction". Journal of American Chemical Society, 2011, 133, 8199-8024.
Lohokare et al., "Reactions of Disilane on Cu(111): Direct Observation of Competitive Dissociation, Disproportionation, and Thin Film Growth Processes", Langmuir 1995, vol. 11, pp. 3902-3912.
Low et al., Selective deposition of CVD iron on silicon dioxide and tungsten, Microelectronic Engineering 83, pp. 2229-2233, 2006.
Mackus et al., Influence of Oxygen Exposure on the Nucleation of Platinum Atomic Layer Deposition: Consequences for Film Growth, Nanopatterning, and Nanoparticle Synthesis, Chem. Matter, vol. 25, pp. 1905-1911, 2013.
Mackus et al., Local deposition of high-purity Pt nanostructures by combining electron beam induced deposition and atomic layer deposition, Journal of Applied Physics, vol. 107, pp. 116102-1-116102-3, 2010.
Maluf et al., "Selective tungsten filling of sub-0.25μm trenches for the fabrication of scaled contacts and x-ray masks", J. Vac. Sci. Technol. B, vol. 8, No. 3, May/Jun. 1990, pp. 568-569.
Norrman, et al.; 6 Studies of Spin-Coated Polymer Films; Annu. Rep. Prag. Chem.; Sect. C; 2005; 101; pp. 174-201.
Notice of Allowance dated Apr. 5, 2017 in U.S. Appl. No. 15/177,195.
Office Action dated Aug. 29, 2014 in U.S. Appl. No. 13/702,992.
Office Action dated Jun. 8, 2017 in Korean Application No. 2013-7000596.
Office Action dated Nov. 7, 2014 in U.S. Appl. No. 13/708,863.
Overhage et al., Selective Atomic Layer Deposition (SALD) of Titanium Dioxide on Silicon and Copper Patterned Substrates, Journal of Undergraduate Research 4, 29, Mar. 2011 in 4 pages.
Parulekar et al., Atomic Layer Deposition of Zirconium Oxide on Copper Patterned Silicon Substrate, Journal of Undergraduate Research, vol. 7, pp. 15-17, 2014.
Parulekar et al., Selective atomic layer deposition of zirconium oxide on copper patterned silicon substrate, pp. 1-6, 2013.
Prasittichai et al., "Area Selective Molecular Layer Deposition of Polyurea Film", Applied Materials & Interfaces, 2013, vol. 5, pp. 13391-13396.
Proslier et al., "Atomic Layer Deposition and Superconducting Properties of NbSi Films", The Journal of Physical Chemistry C, 2011, vol. 115, No. 50, pp. 1-26.
Putkonen, et al.; Atomic Layer Deposition of Polyimide Thin Films; Journal of Materials Chemistry; 2007, 17, pp. 664-669.
Ratta, Varun; Crystallization, Morphology, Thermal Stability and Adhesive Properties of Novel High Performance Semicrystalline Polyimides, Chapter 1; Virginia Tech Chemistry PhD Dissertation; URN # etd-051799-162256; Apr. 26, 1999.
Roberts et al., "Selective Mn deposition on Cu lines", poster presentation, 12th International Conference on Atomic Layer Deposition, Jun. 19, 2012, Dresden, Germany.
Sapp, et al.; Thermo-Mechanical and Electrical Characterization of Through-Silicon Vias with a Vapor Deposited Polyimide Dielectric Liner; IEEE; 2012.
Schmeißer, Decomposition of formic acid, Chemnitz University of Technology, pp. 1-13, Aug. 31, 2011.
Schmeißer, Reduction of Copper Oxide by Formic Acid an ab-initio study, Chemnitz University of Technology, pp. 1-42, Sep. 2011.
Selvaraj et al., Selective atomic layer deposition of zirconia on copper patterned silicon substrates using ethanol as oxygen source as well as copper reductant, Journal of Vacuum Science & Technology A, vol. 32, No. 1, pp. 010601-1-010601-4, Jan. 2014.
Senesky et al., "Aluminum nitride as a masking material for the plasma etching of silicon carbide structures," 2010, IEEE, pp. 352-355.
Sundberg, et al.; Organic and Inorganic-Organic Thin Film Structures by Molecular Layer Deposition: A Review; Beilstein J. Nanotechnol; 2014, 5, pp. 1104-1136.
Toirov, et al.; Thermal Cyclodehydration of Polyamic Acid Initiated by UV-Irradiation; Iranian Polymer Journal; vol. 5, No. 1; pp. 16-22; 1996; Iran.
Vallat et al., Selective deposition of Ta205 by adding plasma etching super-cycles in plasma enhanced atomic layer deposition steps, Journal of Vacuum Science & Technology A, vol. 35, No. 1, pp. 01B104-1-016104-7, Jan. 2017.
Vervuurt et al., "Area-selective atomic layer deposition of platinum using photosensitive polyimide", Nanotechnology 27, 2016, in 6 pages.
Yu et al., "Gas/surface reactions in the chemical vapor deposition of tungsten using WF6/SiH4 mixtures", J. Vac. Sci. Technol. A, vol. 7, No. 3, May/Jun. 1989, pp. 625-629.
Zhou, et al.; Fabrication of Organic Interfacial Layers by Molecular Layer Deposition: Present Status and Future Opportunities; Journal of Vacuum Science & Technology; A 31 (4), 040801-1 to 040801-18; 2013.

Also Published As

Publication number Publication date
US20180068885A1 (en) 2018-03-08
US20130189837A1 (en) 2013-07-25
US9679808B2 (en) 2017-06-13
WO2011156705A2 (en) 2011-12-15
TWI529808B (en) 2016-04-11
WO2011156705A3 (en) 2012-04-05
TW201203370A (en) 2012-01-16
TW201546900A (en) 2015-12-16
KR101906588B1 (en) 2018-10-10
KR20180112118A (en) 2018-10-11
TWI509695B (en) 2015-11-21
US20150187600A1 (en) 2015-07-02
US20160276208A1 (en) 2016-09-22
KR20130075764A (en) 2013-07-05
US8956971B2 (en) 2015-02-17
US9257303B2 (en) 2016-02-09

Similar Documents

Publication Publication Date Title
US7157798B1 (en) Selective refractory metal and nitride capping
EP2228465B1 (en) Methods for making dielectric films comprising silicon
US6835674B2 (en) Methods for treating pluralities of discrete semiconductor substrates
US8367546B2 (en) Methods for forming all tungsten contacts and lines
US8409987B2 (en) Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US7220461B2 (en) Method and apparatus for forming silicon oxide film
JP6452292B2 (en) Deposition Si precursor SiN at low temperatures
US6468924B2 (en) Methods of forming thin films by atomic layer deposition
US6013575A (en) Method of selectively depositing a metal film
US7410666B2 (en) Metal nitride carbide deposition by ALD
JP5196915B2 (en) Method of forming a ruthenium film for metal wiring structure
US20040142557A1 (en) Deposition of tungsten nitride
US6902763B1 (en) Method for depositing nanolaminate thin films on sensitive surfaces
US7329590B2 (en) Method for depositing nanolaminate thin films on sensitive surfaces
JP5376361B2 (en) Method and apparatus for producing a tungsten film
JP6146948B2 (en) Selective cobalt deposition on the copper surface
US8268722B2 (en) Interfacial capping layers for interconnects
US20060014384A1 (en) Method of forming a layer and forming a capacitor of a semiconductor device having the same layer
JP3937892B2 (en) Method of manufacturing a thin film forming method and a semiconductor device
JP5048476B2 (en) A method of forming an insulating film or a metal film
JP4738178B2 (en) A method of manufacturing a semiconductor device
US20080286589A1 (en) Incorporation of nitrogen into high k dielectric film
JP4813480B2 (en) Method of manufacturing a semiconductor device, a substrate processing method and substrate processing apparatus
US6399490B1 (en) Highly conformal titanium nitride deposition process for high aspect ratio structures
US7476618B2 (en) Selective formation of metal layers in an integrated circuit

Legal Events

Date Code Title Description
CC Certificate of correction