JP2011119324A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2011119324A JP2011119324A JP2009273148A JP2009273148A JP2011119324A JP 2011119324 A JP2011119324 A JP 2011119324A JP 2009273148 A JP2009273148 A JP 2009273148A JP 2009273148 A JP2009273148 A JP 2009273148A JP 2011119324 A JP2011119324 A JP 2011119324A
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- H01L2924/19041—Component type being a capacitor
Abstract
【解決手段】一方の主面に於ける半導体素子領域2内に複数の機能素子が配設された半導体基板1と、半導体基板1の一方の主面上に配設され、複数の配線層3と複数の絶縁層4とを含む多層配線層2と、多層配線層2上に形成された第1の有機絶縁物層6と、第1の有機絶縁物層上に形成され、配線層に電気的に接続された他の配線層と、第1の有機絶縁物層6上に、他の配線層を覆うように形成された第2の有機絶縁物層10とを具備し、半導体素子領域を囲む半導体基板領域に、多層配線層を貫く溝が半導体素子領域を囲繞して配設されており、溝内には、前記有機絶縁物層6、有機絶縁物層10のいずれからも分離された有機絶縁物が配設されている。
【選択図】図1
Description
本発明による半導体装置の第1の実施形態について、その製造方法と共に説明する。
本発明の第1の実施の形態に於ける半導体装置100を、図1及び図2に示す。
前記本第1の実施形態に於ける半導体装置100の製造方法について、図3乃至図10を用いて説明する。
しかる後、前記金属層14に於ける銅(Cu)層上に、フォトレジスト層32を形成する。
[第2実施形態]
本発明による半導体装置の第2の実施形態について、その製造方法と共に説明する。
本発明の第2の実施の形態に於ける半導体装置200を、図11に示す。尚、図11は、前記図2に示す部位に対応する箇所の断面を示している。
次に、本第2の実施形態に於ける半導体装置200の製造方法について、図12乃至図15を用いて説明する。
しかる後、前記有機絶縁物層10上に、露光用マスク44を配置する。
[第3実施形態]
本発明による半導体装置の第3の実施形態について、その製造方法と共に説明する。
本発明の第3の実施の形態に於ける半導体装置300を、図16に示す。尚、図16は、前記図2に対応する箇所の断面を示している。
次に、本第3の実施形態に於ける半導体装置300の製造方法について、図17乃至図20を用いて説明する。
[第4実施形態]
本発明による半導体装置の第4の実施形態について、その製造方法と共に説明する。
本発明の第4の実施の形態に於ける半導体装置400を、図21に示す。尚、図21は、前記図2に示す部位に対応する箇所の断面を示している。
次に、本第4の実施形態に於ける半導体装置の製造方法について、図22乃至図25を用いて説明する。
[第5実施形態]
本発明による半導体装置の第5の実施形態について説明する。
本発明の第5の実施の形態に於ける半導体装置500を、図25に示す。尚、図25は、前記図2に示す部位に対応する箇所の断面を示している。
上記実施形態に限らず種々の変形が可能である。
複数の機能素子が配設された半導体素子領域が主面に形成された半導体基板と、
前記半導体基板の前記主面上に配設された多層配線層と、
前記多層配線層上に配設された第1の有機絶縁物層と、
前記半導体素子領域を囲繞するスクライブ領域上の前記多層配線層を貫通した溝と、
前記第1の有機絶縁物層とは離間して、前記溝内に配設された有機絶縁物と
を有することを特徴とする半導体装置。
さらに、前記第1の有機絶縁物層上に配設された配線層と、
前記配線層を覆って配設された第2の有機絶縁物層と
を有することを特徴とする付記1記載の半導体装置。
前記溝内に配設された有機絶縁物は、前記第1の有機絶縁物層を形成する有機絶縁物と同一の材料からなる
ことを特徴とする付記1の半導体装置。
前記溝は、前記スクライブ領域上の前記多層配線層に並行して複数本設けられている
ことを特徴とする付記1記載の半導体装置。
前記溝は、第1の溝と、
前記第1の溝から離間して、且つ前記半導体素子領域を囲繞する第2の溝と
からなり、
前記第2の溝内に配設された有機絶縁物は、前記半導体基板の側面に表出されている
ことを特徴とする付記1記載の半導体装置。
前記多層配線層に含まれる層間絶縁層は、低誘電率絶縁物からなる
ことを特徴とする付記1記載の半導体装置。
付記1乃至7のいずれかに記載の半導体装置において、
前記有機絶縁物層、前記溝内の有機絶縁物は、
ポリイミド、ベンゾシクロブテン、フェノール樹脂、エポキシ樹脂、ポリベンゾオキサゾール、又は、ビスマレイミド樹脂を含む
ことを特徴とする半導体装置。
半導体基板の主面上の複数の半導体素子領域のそれぞれに機能素子を形成する工程と、
前記半導体基板の前記主面上に多層配線層を形成する工程と、
前記半導体素子領域の周囲のスクライブ領域上の前記多層配線層に、前記半導体素子領域を囲繞し且つ前記多層配線層を貫く溝を形成する工程と、
前記多層配線層上及び前記溝の中に有機絶縁物層を形成する工程と、
前記半導体素子領域上の前記多層配線層を覆う有機絶縁物層と前記溝内に形成された有機絶縁物を分離する工程と、
前記スクライブ領域に於いて前記半導体基板を切断する工程と
を有することを特徴とする半導体装置の製造方法。
前記半導体素子領域の周囲のスクライブ領域上の前記多層配線層に、前記半導体素子領域を囲繞し且つ前記多層配線層を貫く溝を形成する工程において、
複数の溝を形成する
ことを特徴とする付記8記載の半導体装置の製造方法。
付記8記載の半導体装置の製造方法において、
前記有機絶縁物層は、ポジ型の感光性の有機絶縁物層であり、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程は、前記スクライブ領域内の前記第1の有機絶縁物層のうちの前記溝内を除く部分の前記有機絶縁物層を感光させる工程と、感光した部分の前記有機絶縁物層を現像により除去する工程とを有する
ことを特徴とする半導体装置の製造方法。
付記8記載の半導体装置の製造方法において、
前記有機絶縁物層は、ポジ型の感光性の有機絶縁物層であり、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程は、前記スクライブ領域のうちの前記溝が形成された領域を除く領域を感光させる工程と、感光した部分の前記有機絶縁物層を現像により除去する工程と
を有することを特徴とする半導体装置の製造方法。
付記8記載の半導体装置の製造方法において、
前記有機絶縁物層は、ネガ型の感光性の有機絶縁物層であり、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程は、前記スクライブ領域のうちの前記溝が形成された領域を感光させる工程と、未感光の部分の前記有機絶縁物層を現像により除去する工程と
を有することを特徴とする半導体装置の製造方法。
付記8記載の半導体装置の製造方法において、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程の後、前記半導体基板を切断する工程の前に、
前記半導体素子領域内の前記有機絶縁物層上に、前記多層配線層に電気的に接続された配線層を形成する工程と、
前記半導体基板上に、前記配線層を覆うように他の有機絶縁物層を形成する工程と、
前記スクライブ領域内の少なくとも一部の前記他の有機絶縁物層を除去する工程とを更に有し、
前記溝を形成する工程では、各々の前記スクライブ領域内に複数の前記溝を並行するように形成し、
前記スクライブ領域内の少なくとも一部の前記他の有機絶縁物層を除去する工程では、前記他の有機絶縁物層の周縁部が、前記複数の溝のうちの最も前記半導体素子領域に近接している溝よりも前記半導体素子領域側に位置するように、前記スクライブ領域内の前記他の有機絶縁物層を除去する
ことを特徴とする半導体装置の製造方法。
付記8記載の半導体装置の製造方法において、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程の後、前記半導体基板を切断する工程の前に、
前記半導体素子領域内の前記有機絶縁物層上に、前記多層配線層に電気的に接続された配線層を形成する工程と、
前記半導体基板上に、前記配線層を覆うように他の有機絶縁物層を形成する工程と、
前記スクライブ領域内の少なくとも一部の前記他の有機絶縁物層を除去する工程とを更に有し、
前記半導体素子領域上の前記多層配線層を覆う前記有機絶縁物層と前記溝内に形成された前記有機絶縁物を分離する工程では、前記溝内の前記有機絶縁物層のうちの上部が除去され、
前記スクライブ領域内の少なくとも一部の前記他の有機絶縁物層を除去する工程では、前記溝内のうちの前記有機絶縁物層上の部分に前記他の有機絶縁物層が残存する
ことを特徴とする半導体装置の製造方法。
I…半導体素子領域
II…スクライブ領域
1…半導体基板
2…多層配線層
3…配線層
4…層間絶縁膜
5…表面保護層
6…有機絶縁物層
7…再配線層
10…有機絶縁物層
12…外部接続用端子
13…溝
31,32,34…フォトレジスト層
41,42,43,44,45,46,47…露光用マスク
51…ダイシングブレード
Claims (8)
- 複数の機能素子が配設された半導体素子領域が主面に形成された半導体基板と、
前記半導体基板の前記主面上に配設された多層配線層と、
前記多層配線層上に配設された第1の有機絶縁物層と、
前記半導体素子領域を囲繞するスクライブ領域上の前記多層配線層を貫通した溝と、
前記第1の有機絶縁物層とは離間して、前記溝内に配設された有機絶縁物と
を有することを特徴とする半導体装置。 - さらに、前記第1の有機絶縁物層上に配設された配線層と、
前記配線層を覆って配設された第2の有機絶縁物層と
を有することを特徴とする請求項1記載の半導体装置。 - 前記溝内に配設された有機絶縁物は、前記第1の有機絶縁物層を形成する有機絶縁物と同一の材料からなる
ことを特徴とする請求項1記載の半導体装置。 - 前記溝は、前記スクライブ領域上の前記多層配線層に並行して複数本設けられている
ことを特徴とする請求項1記載の半導体装置。 - 前記溝は、第1の溝と、
前記第1の溝から離間して、且つ前記半導体素子領域を囲繞する第2の溝と
からなり、
前記第2の溝内に配設された有機絶縁物は、前記半導体基板の側面に表出されている
ことを特徴とする請求項1記載の半導体装置。 - 前記多層配線層に含まれる層間絶縁層は、低誘電率絶縁物からなる
ことを特徴とする請求項1記載の半導体装置。 - 半導体基板の主面上の複数の半導体素子領域のそれぞれに機能素子を形成する工程と、
前記半導体基板の前記主面上に多層配線層を形成する工程と、
前記半導体素子領域の周囲のスクライブ領域上の前記多層配線層に、前記半導体素子領域を囲繞し且つ前記多層配線層を貫く溝を形成する工程と、
前記多層配線層上及び前記溝の中に有機絶縁物層を形成する工程と、
前記半導体素子領域上の前記多層配線層を覆う有機絶縁物層と前記溝内に形成された有機絶縁物を分離する工程と、
前記スクライブ領域に於いて前記半導体基板を切断する工程と
を有することを特徴とする半導体装置の製造方法。 - 前記半導体素子領域の周囲のスクライブ領域上の前記多層配線層に、前記半導体素子領域を囲繞し且つ前記多層配線層を貫く溝を形成する工程において、
複数の溝を形成する
ことを特徴とする請求項7記載の半導体装置の製造方法。
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KR1020100117883A KR101135995B1 (ko) | 2009-12-01 | 2010-11-25 | 반도체 장치 및 그 제조 방법 |
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JP6084139B2 (ja) * | 2013-09-05 | 2017-02-22 | オリンパス株式会社 | 半導体基板およびその製造方法 |
JP6421083B2 (ja) * | 2015-06-15 | 2018-11-07 | 株式会社東芝 | 半導体装置の製造方法 |
US20170062240A1 (en) * | 2015-08-25 | 2017-03-02 | Inotera Memories, Inc. | Method for manufacturing a wafer level package |
KR102557402B1 (ko) | 2018-10-19 | 2023-07-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
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JP2020004881A (ja) * | 2018-06-29 | 2020-01-09 | 三菱電機株式会社 | 半導体装置の製造方法 |
CN113517205A (zh) * | 2020-04-27 | 2021-10-19 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
KR20210133110A (ko) * | 2020-04-27 | 2021-11-05 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 웨이퍼 싱귤레이션을 위한 패시베이션 스킴 설계 |
KR102524727B1 (ko) * | 2020-04-27 | 2023-04-21 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 그 형성 방법 |
US11699663B2 (en) | 2020-04-27 | 2023-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation scheme design for wafer singulation |
US11942436B2 (en) | 2020-04-27 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation scheme design for wafer singulation |
WO2024053521A1 (ja) * | 2022-09-05 | 2024-03-14 | 株式会社レゾナック | 半導体装置の製造方法、及び構造体 |
WO2024052968A1 (ja) * | 2022-09-05 | 2024-03-14 | 株式会社レゾナック | 半導体装置の製造方法、及び構造体 |
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TW201135820A (en) | 2011-10-16 |
KR20110061481A (ko) | 2011-06-09 |
US8324714B2 (en) | 2012-12-04 |
TWI435382B (zh) | 2014-04-21 |
JP5532870B2 (ja) | 2014-06-25 |
US20110127647A1 (en) | 2011-06-02 |
KR101135995B1 (ko) | 2012-04-17 |
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